JPH06119729A - Disk driving device - Google Patents

Abstract

PURPOSE:To prevent misseek by delaying the following driving pulses after a 2nd driving pulse by a prescribed time and outputting them to a head driving means when a step pulse has not been supplied for more than a prescribed time. CONSTITUTION:When a 1st step pulse signal a1 from a host computer device is supplied to a delay circuit 1, a step pulse b1 is generated, and afterward an output terminal +Q of a flip-flop 3 on this line side is set for H, while the other -Q for L, and then a multiplexer 4 is changed from its state of selecting a step pulse signal (from a host device) (a) as an output (g) to its state of selecting and outputting a delayed step pulse signal (b) from the delay circuit 1 as the output (g). By this method, accurate seek operation is performed without lowering operating speed of a step motor 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk drive device, and more particularly, it is suitable for use in a head feeding device of a disk drive device.

[0002]

2. Description of the Related Art Conventionally, a step motor is used as a drive source for head feeding in a floppy disk drive device or the like, and is used for moving a head supplied from the outside such as a host computer to which the disk drive device is connected. The head is moved (seek operation) to an arbitrary recording track on the disk in response to the step pulse signal.

[0003]

However, for example, when the interval between step pulse signals supplied from the host computer, that is, the step plate, becomes short, a phenomenon (mis-seek) that the target track cannot be reached occurs. This is the rise of the operation of the mechanical part in response to a step signal due to static friction, inertia, mechanical rattle, etc. between a carriage equipped with a step motor and a head and a mechanism for transmitting the driving force of the step motor to the carriage. Is due to the delay.

In recent years, as disk drives have become thinner and smaller, the step motors have become smaller, resulting in a reduction in driving force. Also, the drive transmission mechanism from the step motors to the carriages has become smaller and the cost has been reduced. As a result, there is a tendency in that there is a disadvantage in terms of accuracy, and the delay in the rise of the above-mentioned operation tends to increase. Further, the tendency tends to be strong in an environment, especially at a low temperature, and even when the disk drive device is driven by a battery, the above problem is apt to occur due to a decrease in voltage of the step motor and a decrease in torque of the step motor due to battery consumption. is expected.

The above-mentioned mis-seek may occur for step pulses in the latter half of 2 msec to about 3 msec which are often used in actual products, which is not preferable in terms of reliability in recording / reproduction.

Here, the delay of the rising edge of the seek operation is
Considering the cause of mis-seek when the step plate is short, if the step pulse signal is supplied in the stationary state of the carriage, step motor, etc., the stable position expected by the excitation of the step motor driver by the first step pulse is obtained. The next step pulse signal is supplied when the step motor has not reached, that is, the head has not moved to the target track.

As a result, the excitation phase of the step motor driver is switched by the second step pulse signal while the step motor remains in an unstable position, resulting in a decrease in torque of the step motor, a decrease in operating speed, and a movement to an incorrect position. Occurs, the target track cannot be reached, resulting in a miss seek.

[0008]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems, and is characterized in that a head is transferred to a disk-shaped recording medium in a predetermined step unit. The apparatus further comprises a head drive means and a drive pulse generation means for generating a drive pulse for operating the head drive means based on a step pulse supplied from the outside, wherein the drive pulse generation means has the step pulse for a predetermined period. If not supplied, the disk drive device is configured to delay the second drive pulse and the subsequent drive pulses by a predetermined time when the step pulse is supplied next, and output the delayed drive pulse to the head drive means.

[0009]

As a result, the follow-up performance for the step pulse signal is improved, and even if the interval between the supplied step pulse signals is short, the head can be surely reached to the target track and mis-seek can be prevented. it can.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a disk drive device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a disk drive device according to the present invention, and FIG. 2 is a timing chart showing signals relating to head movement of the disk drive device according to the present invention.

In FIG. 1, STEP is a step pulse signal CKL for head movement, which is supplied from the host computer device to which the present disk drive device is connected.
Is a clock pulse signal supplied from a clock oscillator (not shown) provided in the disk drive device, and POR is a power-on reset signal supplied when the power is turned on.

Reference numeral 1 denotes a step signal (in FIG. 2) supplied by a host computer (not shown) in negative logic in this embodiment.
2A, a delay circuit 2 for generating a negative logic step signal (FIG. 2B) delayed by a predetermined time t2 as shown in FIG. 2 is a clock pulse CLK supplied from the host computer device (FIG. 2B). f)) is counted and reset at the "L" level of the step pulse signal (a). For example, in the present embodiment, the step pulse signal (a) is supplied for 5.5 msec (the setting of this time will be described later) or more. If not, it outputs a positive logic pulse,
The counter resets the flip-flop 3 via the OR circuit 9 at the timing e1 in the signal (e) of FIG.

Reference numeral 3 is reset by the output (e) of the OR circuit 9, and the step signal (a) output from the delay circuit 1 is delayed by time t1 to output + Q (at the trailing edge of the step pulse signal (b). 2 (c)) is "H", output-Q
(FIG. 2 (d)) is a flip-flop set to "L", 4 is an output signal (c), (d) of the flip-flop 3.
The output signal (g) to the step pulse signal (a),
A multiplexer 5 for selecting and supplying any one of the delayed pulse signals (b) is a step motor drive pulse for driving the step motor 7 based on the step pulse signal supplied from the output signal (g) of the multiplexer 4. Is a driver control circuit for controlling the driver 6 that generates

Reference numeral 8 denotes a known transmission mechanism for transmitting the driving force of the step motor 7 to a carriage 11 having a head 12 for writing and reading.

Reference numeral 10 is a disk-shaped recording medium having a predetermined format, Tr0, Tr1, ..., TrN.
Indicates each track position on the recording medium 10. Also (i)
1 shows the moving direction of the head 12 on the carriage 11, and FIG. 2 shows the track position of the head.

The disk drive device of the present invention is constructed as described above, and its operation will be described below with reference to the drawings.

When the host computer device to which the disk drive device is connected is powered on, the disk drive device is also powered on at the same time, the power-on reset signal POR becomes "H", and the delay circuit 1 operates. At the same time, the flip-flop 3 is reset via the OR circuit 9 (e1 in FIG. 2). As a result, the delay circuit 1
Output of the flip-flop 3 is "L", and the output + Q of the flip-flop 3 is "L" and -Q is "H".

After the reset is completed, the power-on reset signal POR becomes "L", the clock CLK starts to oscillate, and the delay circuit 1 and the counter 2 wait for the step signal (a) from the host computer device (not shown). The flip-flop 3 waits for the delayed step signal (b) output from the delay circuit 1.

When the first first step signal (a1 in FIG. 2) is supplied from the host computer device, the outputs + Q and -Q of the flip-flop 3 are set to (c) and (d) in the reset state until then. Output as shown +
Since Q and -Q are "L" and "H" respectively,
The multiplexer 4 outputs the input step pulse signal a of (a)
1 is selected and input to the driver control circuit 5, and then a driver drive signal is output from the driver control circuit 5 and supplied to the driver 6. As a result, the driver 6 outputs the step motor excitation phase signal shown in FIG. 2 (h), and the step motor 7 is driven.

Then, the carriage 11 is driven via the drive transmission mechanism 8, and the head 12 starts moving to the target track on the recording medium. In addition, according to the present embodiment, a case will be described in which the medium that has been formatted is moved from the track Tr0 to the inner circumferential direction for simplification. However, there is no limitation on the position on the medium, and the arbitrary position can be changed from any position. Can be operated against.

By the way, due to the inertia of the step motor 7 and the carriage 11, the mechanical "rattle" of the transmission mechanism, etc., the actual head, that is, the movement of the carriage is started with respect to the step pulse signal a1 shown in FIG. 2 (a). Time t1
It is from the position of P0 shown in FIG. The delay time t1 of the delay circuit 1 described above is set so as to substantially correspond to the rising delay time caused by inertia, rattle, etc. existing between the step motor and the carriage.

On the other hand, the first from the host computer device
2 is supplied to the delay circuit 1, a step pulse b1 delayed by the time t1 shown in FIG. 2B is generated, and the output terminal + Q of the flip-flop 3 is "H",-on the trailing edge side. Q is set to "L", and the multiplexer 4 selects the delayed step pulse signal (b) from the delay circuit 1 as the output (g) from the state in which the above step pulse signal (a) is selected as the output (g). And output.

By the way, the counter 2 is reset by the step pulse signal (a) being inputted to the reset terminal RST and starts counting the clock pulse CLK. For example, a preset time t3 (5. Although it is set to 5 msec, this value is the time which is considered to be sufficient for the step motor and head to reach the target track position expected to be moved by the step pulse signal in the disk drive device. If the step pulse signal (a) is not input again within a different value depending on the device,
The output becomes "H", the flip-flop 3 is reset via the OR circuit 9, and the multiplexer 4 returns to the state in which the step pulse signal (a) from the host computer device not via the delay circuit 1 is selected.

Here, after the step pulse interval supplied from the above-mentioned host computer device is short and the first step pulse signal a1 is input, the second step pulse signal a2, the head 12 and the head 12 of FIG. As shown in (i), at the position P1 in the middle of the operation from the track Tr0 to Tr1, that is, the first step pulse signal a1.
When a time t2 has elapsed from the beginning, the head 12 moves to the target track Tr1 shown in FIG. 2 (i), which is expected to be moved by the first step a1 due to the operation start delay time t1. Not reached at this stage. Further, the step motor 7 is also in an unstable position, and has not yet reached a stable position with respect to the excitation phase (h).

Therefore, according to the conventional device, even if the second step pulse a2 is immediately supplied as it is, the step motor 7 does not operate and the head 12 stops without reaching the target track. As mentioned above, there is a risk of being damaged.

Here, the present invention operates as follows. That is, the second step pulse signal a
2 is the head 12 is the P1 between the tracks Tr0 and Tr1
, The interval t2 between the step pulse signals a1 and a2 supplied from the host computer device side is 5.5 msec or less, the flip-flop 3 is not reset and the multiplexer 4 is not reset.
Output (g) of the step pulse signal a2 is t
A delayed step pulse signal b2 delayed by 1 is output (pulse g2 shown in FIG. 2 (g)).

Since the pulse signal g2 output from the multiplexer 4 is delayed from the second step pulse signal a2 by t1 corresponding to the operation delay time of the head described above, the head 12 is output when g2 is output. Has reached P2 on the track Tr1, and both the step motor 7 and the head 12 have reached the target track position expected to be moved by the first step pulse signal a1.

Therefore, the output of the driver control circuit 5 is changed by the pulse signal g2, and the step motor 7 drives the head 12 by the excitation phase output (h) from the driver 6 to move it from the track Tr1 to the track Tr2. At the position P2, the step motor 7, the drive transmission mechanism 8, the carriage 11
Is located at the target position and is in the operating state, there is no delay as at time t1, so that the track is smoothly moved to the track Tr2, and the third delay step signal b3.
It is possible to operate smoothly with respect to the pulse signal g3 based on.

On the other hand, as shown in FIG. 2, the interval t3 from the third step pulse signal a3 to the step pulse signal a4.
Is 5.5 msec or more, that is, when the step pulse signal is not input from the host computer side for a certain period, the operation of the head 12 has reached the track Tr3 expected by a3, and the step motor 7
Since there is a possibility that the carriage 11 and the transmission mechanism 8 have finished their operations and become stationary, they are output by counting 5.5 msec of the counter 2 as shown in (e) of FIG. The flip-flop 3 is reset by the output signal e2, and the fourth step pulse signal a4 shown in FIG. 2 is treated the same as the first step pulse signal a1 again. The step pulse signal a4 is not delayed and the pulse signal g4 is unchanged. The delayed step pulse signal b5 is set to g5 with respect to the fifth step pulse signal a5 supplied to the driver control circuit 5 after the time t2 from the step pulse signal a4, and the step operation is performed.

According to the above method, when the head is in a stationary state or in a state in which the step pulse is not input for more than a predetermined time and is almost stationary, there is a delay from the step motor being driven to the start of the operation of the carriage equipped with the head. Since the step motor is driven by the delayed step pulse signal obtained by delaying the step pulse signals of the second and subsequent shots by the time, the rattling of the transmission mechanism is sufficient for the step pulse signals of the second and subsequent shots. Since it is delayed until absorbed, it is supplied to the step motor.
When the delayed step pulse after the occurrence is supplied,
The step motor and head on the carriage have reached the target track and are in a stable position. Therefore, the operation speed of the step motor is not lowered and the step motor is not moved to an incorrect position, and an accurate seek operation is performed.

[0032]

As described above, according to the disk drive apparatus of the present invention, the step motor is unstable due to inertia of the step motor and the carriage and transmission mechanism, static friction, and delay in starting the step drive operation due to backlash. In this condition, when the step pulse signal is input, the problem that the target track cannot be reached is solved, and smooth head movement becomes possible, and the step motor is sent to the step motor with the first step pulse signal as before. Even if the step pulse interval becomes short, there will be no inconvenience that the next step pulse is supplied within the mechanical delay time due to rattling of the transmission mechanism after driving the It is possible to always realize accurate and reliable head movement control.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a head drive control circuit of a disk drive device according to the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

Claims (1)

[Claims] 1. A head drive means for transferring a head to a disk-shaped recording medium in a predetermined step unit, and a drive for generating a drive pulse for operating the head drive means based on a step pulse supplied from the outside. Pulse drive means, the drive pulse generation means, when the step pulse is not supplied for a predetermined period or more, when the step pulse is next supplied, delays the second drive pulse and the subsequent drive pulses by a predetermined time. The disk drive device is configured to output to the head drive means.