JP2593449B2 - Disk drive - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk drive, and more particularly, to a disk drive (hereinafter abbreviated as FDD) for positioning a head by a double step drive of a stepping motor. Things.

[Prior Art] There is a method in which a magnetic head is positioned by a double step operation of a stepping motor in an FDD.

In this method, the time from the step pulse applied from the outside to the step pulse generated inside the FDD, that is, the intermediate step rate is set to the interval between the step pulses applied from the outside, that is, 1/2 of the step rate, to reduce the noise and reduce the step-out. I'm trying not to happen.

[Problems to be Solved by the Invention] By the way, when a plurality of disks having different recording densities are loaded and the step rate changes, the intermediate step rate is fixed. Since the time between the intermediate step rate, which is the time of the step pulse, and the next step pulse applied from the outside after the internally generated step pulse is not equal, the stepping motor moves irregularly, the noise increases, and the step-out occurs. There is a problem that there is a risk of occurrence.

Therefore, an object of the present invention is to solve the above-mentioned problems and to take into account that a plurality of disk drives are usually connected to a host computer in many cases. An object of the present invention is to provide a disk drive device which is designed so that unnecessary noise is not generated as a result of performing a useless operation in which a disk drive is generated.

[Means for Solving the Problems] In the present invention, in order to solve the above-described problems,
In a disk drive device for step-driving a head by a stepping motor, a control circuit that outputs a step pulse for driving the stepping motor supplied from the outside via an interface and generates a driving pulse for driving the stepping motor, The cycle of the step pulse is determined based on information of an intermediate step rate supplied from the outside via the interface, connected to the control circuit, and the timing of the step pulse is determined at a substantially intermediate position within one cycle of the step pulse. An intermediate pulse generating circuit that controls the driving pulse generated by the control circuit to be a pulse signal obtained by combining the step pulse and the intermediate pulse by causing the control circuit to generate an intermediate pulse; The disk drive is selected A drive select signal indicating whether or not the disk drive has been selected, and a state of a write gate signal for controlling the writing of the head. And a gate circuit for supplying the step pulse to the control circuit only when writing is prohibited in the non-active state.

[Operation] With the above configuration, the time from the externally applied step pulse to the internally generated step pulse is equal to the time from the internally generated step pulse to the externally applied step pulse. It is possible to control and reduce the seek noise of the stepping motor and prevent step-out.

Further, by performing the operation of generating the intermediate pulse only when the drive device is selected and writing is prohibited, useless intermediate pulse can be prevented from being generated. If the drive is not selected, the supply of the step pulse is performed. Even if there is no drive, only the intermediate pulse is generated on its own, preventing the stepping motor from malfunctioning.

EXAMPLES Hereinafter, the details of the present invention will be described based on examples shown in the drawings.

1 and 2 illustrate an embodiment of the present invention. FIG. 1 shows a block diagram of a control circuit.

1 is a stepping motor, which is driven by a driver 2.

The driver 2 is controlled by a control circuit 3, which is connected to an intermediate step rate setting circuit 4 which provides information on the intermediate step rate.

On the other hand, reference numeral 7 denotes an interface connector, which is provided with a drive select signal line 8, a write gate signal line 9, and a step signal line 10.

The drive select signal line 8 and the step signal line 10 are directly input to the NOR gate 5, and the write gate signal line 9 is input to the NOR gate 5 via the inverter 6. The output of the NOR gate 5 is input to the control circuit 3.

Further, the interface connector 7 is provided with a plurality of signal lines 11 for setting an intermediate step rate.
It is connected to the intermediate step rate setting circuit 4.

On the other hand, FIG. 2 shows a timing chart of the signals of each part of the control circuit shown in FIG.

In FIG. 2, reference numeral 12 denotes a signal applied to the step signal line 10, reference numeral 13 denotes an intermediate step pulse generated inside the stepping motor control circuit 3, and reference numeral 14 denotes a phase output of the stepping motor control circuit 3.

 Next, the operation configured as described above will be described.

First, the intermediate step rate setting circuit 4 transmits the intermediate step rate information sent by the intermediate step rate setting signal line 11 to the control circuit 3 of the stepping motor.

When the drive select signal line 8 is active (LOW level) and the write gate signal line 9 is non-active (HIGHT level), the step pulse of the step signal line 10 becomes valid and the stepping motor control circuit 3 Sends the stepping motor phase output to the driver 2 of the stepping motor.

The driver 2 of the stepping motor drives the stepping motor 1 by the phase output.

On the other hand, according to the intermediate step rate information given to the control circuit 3, the control circuit 3 sends the stepping motor phase output to the driver 2 after waiting for the time of the intermediate step rate from the step pulse fetched from the step signal line 10. Drive.

The double step operation of the stepping motor is performed as described above.

In the above-described double step operation, the time between the step pulse signals 12 applied from outside, that is, the step rate
And T _1, so that the time until the step pulse 13 generated inside the control circuit 3 from the step pulse applied I or external, i.e. T ₁ = 2T ₂ relationship between the intermediate step rate T ₂ holds T
Medium setting step rate by a value of _1, producing an intermediate step rate T ₂ to change the logic level of the signal line.

Therefore it is possible to set an intermediate step rate T ₂ by a single intermediate step rate setting signal line 11 for the two threads plates T _1.

Also, signal lines for setting N intermediate step rates
11 can be set intermediate step rate T ₂ for 2 ^N step rate T ₁ of the be provided.

As described above, since the intermediate step rate can be controlled so as to be ス テ ッ プ of the step rate according to the step rate, no step-out of the stepping motor occurs, and the noise during head seek can be reduced.

[Effect] As is clear from the above description, according to the disk drive of the present invention, by adding the intermediate pulse and changing the cycle, the supplied step pulse is supplied to the stepping motor. There is an effect that the drive pulse is prevented from being interrupted as much as possible, and seek noise is reduced and step-out is prevented.

The drive select signal is activated by the gate circuit that controls the supply of the step pulse to the control circuit to the control circuit and the cutoff according to the state of the drive select signal and the write gate signal. Also, the step pulse is supplied to the control circuit only when the write gate signal is in a non-active state and writing is prohibited. Therefore, when the drive device is not selected, or when supplied from outside. An unnecessary operation such as adding an intermediate pulse to the step pulse to be performed or driving the stepping motor can be prevented.

Even if the drive is not selected and the step pulse is not supplied, only the intermediate pulse is generated arbitrarily, thereby preventing the step motor from malfunctioning.

As a result, unnecessary pulse generation and head movement can be prevented, various noises can be prevented, and power consumption can be reduced.

Also, an intermediate pulse is added to the drive pulse of the step motor only when the write gate signal is non-active and writing is not performed, so that the head continuously moves largely in a write-inhibited state. This is effective in preventing noise during a seek operation or an initialization operation in which the head moves over the entire area of the disk to perform reference position alignment.

[Brief description of the drawings]

1 illustrates an embodiment of the present invention. FIG. 1 is a block diagram of a control circuit, and FIG. 2 is a timing chart. DESCRIPTION OF SYMBOLS 1 ... Stepping motor 2 ... Driver 3 ... Control circuit 4 ... Intermediate step rate setting circuit 5 ... NOR gate, 6 ... Inverter 7 ... Interface connector 8 ... Drive select signal line 9 ... Write gate Signal line 10: Step signal line 11: Signal line for intermediate step rate setting 12: Signal to step signal line 13: Intermediate step pulse 14: Phase output of control circuit

Claims (1)

(57) [Claims] 1. A disk drive device for driving a head step by a stepping motor, wherein a step pulse for driving the stepping motor supplied from the outside via an interface is input to generate a driving pulse for driving the stepping motor. A control circuit that is connected to the control circuit and determines a cycle of the step pulse based on information on an intermediate step rate supplied from the outside via the interface; An intermediate pulse generation circuit that controls the control circuit to generate an intermediate pulse at a timing of a position so that the drive pulse generated by the control circuit is a pulse signal obtained by combining the step pulse and the intermediate pulse. And the disk drive supplied from outside A drive select signal indicating whether or not the device is selected, and a state of a write gate signal for controlling writing of the head are identified, and the drive select signal is active and the disk device is selected. And a gate circuit for supplying the step pulse to the control circuit only when the write gate signal is in a non-active state and writing is prohibited.