JPH06112822A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To form a low-order comparator section with a considerably less number of components in an A/D converter circuit by comparing both of 1st and 2nd noninverting comparison output currents and 1st and 2nd inverting comparison output currents respectively with a comparison output current which is the inversion to a synthesis output current CONSTITUTION:A synthesis noninverting output voltage IE synthesizing 1st and 2nd noninverting comparison output currents IA, IC at a prescribed rate is respectively compared with 1st and 2nd inverting comparison output currents IB, ID in an interpolation output stage comprising low-order comparison sections CD 51-CD 58 of an A/D converter circuit 50. A synthesis inverting output current IF being a synthesis of the currents IB, ID at a prescribed rate is compared with 1st and 2nd noninverting comparison output currents IA, IC respectively. Thus, number of transistors(TRs) required for forming the low-order comparison sections CD 51-CD 58 is considerably reduced and the circuit area of the A/D converter circuit 50 is far reduced.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 12) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 and 8 to 10) Action (FIG. 7) Example (FIGS. 1 to 11) (1) Overall configuration of the embodiment (FIGS. 1 to 8) (1-1) Configuration of AD conversion circuit 50 (FIGS. 1 to 3) (1-2) Current shunt in lower comparators CD51 to CD58 Interpolation Principle Used (FIGS. 4 to 7) (1-3) Configuration of Lower Comparators CD51 to CD58 (FIG. 8) (2) Operation of Embodiment (3) Effect of Embodiment (4) Other Embodiment (FIGS. 9 to 11) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog digital conversion circuit, and is particularly suitable for application to a serial / parallel type analog digital conversion circuit.

[0003]

2. Description of the Related Art Conventionally, in various fields such as audio equipment and measuring instruments, an analog digital conversion circuit (hereinafter referred to as an AD conversion circuit) for digitally processing various analog signals such as audio signals to be recorded or reproduced. Say)
Is generally used to convert to digital data, and various conversion methods are considered depending on the application field, required accuracy, speed, and the like.

In particular, when high speed operation and high accuracy are required, a parallel (flash) type AD conversion circuit and a serial / parallel (subranging) type A / D conversion circuit are generally used. In particular, the serial-parallel A-D conversion circuit has an advantage that the number of elements can be significantly reduced as compared with the parallel-type A-D conversion circuit.

This serial-parallel A / D converter circuit has an input signal V
IN is divided into two stages, upper bit and lower bit, and converted to digital data. This type of serial-parallel type A-
The 2-step parallel type A-D conversion circuit 40 is mainly used when the video signal is to be processed even in the D conversion circuit (FIG. 12).

The A-D conversion circuit 40 is a reference voltage generation circuit 4 constructed by connecting 16 reference resistors R in series.
1, the reference voltages VU1 and VU corresponding to the upper two bits
U2 and VU3 are generated, and these three sets of reference voltages VU1 and VU are generated.
U2, VU3 and the input signal VIN are connected to the upper comparator CU.
1, CU2 and CU3 are compared. Then, by supplying the comparison output to the upper encoder 42, the highest bit D1 is generated.

The upper encoder 42 switches the switch group SW based on the comparison output of the upper comparators CU1, CU2, and CU3 to divide the voltage band to which the upper two bits belong and the upper side and the lower side of the voltage band. A total of eight reference voltages VD1, VD2, ..., VD8 for the redundancy correction are prepared.

The lower comparators CD1, CD2,
..., these eight reference voltages VD1 and VD in CD8
D2, ..., VD8 are compared with the input signal VIN, and the comparison output is supplied to the lower encoder 43 to generate the remaining lower three bits D2, D3, and D4.

[0009]

However, the resolution is 10
When it becomes as small as ~ 12 bits, the voltage of the least significant digit (1LSB) required for the A / D conversion circuit 40 becomes very small, about 1 [mV], and as the number of bits increases, the lower comparators CD1, CD2, ... The influence of the base-emitter voltage ΔVBE of the transistors forming the differential pair of CD8 cannot be ignored.

Therefore, a plurality of comparison outputs of the comparators are combined and compared to obtain a comparison output between the intermediate potential of the adjacent reference potentials and the input signal VIN by interpolation, and this interpolation processing is necessary for signal comparison. An interpolating method for eliminating the influence of the base-emitter voltage ΔVBE by reducing the number of special comparators has been studied.

As one of such interpolation methods, the load resistance of the differential amplifier circuit which constitutes the comparator is set as a resistance string of resistances having a predetermined resistance ratio, and an output voltage obtained as a difference voltage between connection taps of the respective resistances. An interpolating method has been proposed which obtains a comparison output of an input signal and an intermediate potential that equally divides a reference potential by combining

In this case, however, an additional differential amplifier stage for interpolation is required, and since a plurality of differential outputs having different resistance values are compared, there is a difference in output speed due to a difference in time constant. Therefore, it is unsuitable for use in a lower comparator constituted by a serial / parallel A / D conversion circuit.

The present invention has been made in consideration of the above points, and it is possible to obtain a comparison output of a plurality of virtual reference potentials for dividing the reference potential with a remarkably smaller number of elements than in the prior art and an input signal. The present invention intends to propose an AD conversion circuit having a comparison circuit capable of performing the above.

[0014]

In order to solve such a problem, according to the present invention, in a serial-parallel type analog digital conversion circuit which executes a conversion operation from an analog signal to digital data by dividing it into a plurality of stages, the conversion is performed. The lower comparison unit used for the operation receives the first reference signal VREF1 and the input signal VIN, and outputs the first reference signal VREF1 to the first reference signal VREF1.
Inversion comparison output current IB and first in-phase comparison output current I
A first differential input stage for outputting A and a second reference signal VRE
A second differential input stage that inputs F2 and the input signal VIN and outputs a second inverted comparison output current ID and a second in-phase comparison output current IC with respect to the second reference signal VREF2;
Inversion comparison output currents IB, ID and in-phase comparison output current I
Flow dividing means for dividing A and IC at predetermined ratios, respectively,
The divided first and second inverted comparison output currents IB and ID are added at a predetermined ratio to generate a synthetic inverted output current IF, and the first and second in-phase comparison output currents IA and IC are generated. A combined in-phase output current IE is generated by adding at a predetermined ratio, and the first and second in-phase comparative output currents IA and IC that are in opposite phase to the combined inverted output current IF and the combined in-phase output current are generated. First and second inverted comparison output currents IB and ID
To compare the first and second reference signals VREF1
And an interpolating output stage for obtaining a result of comparison of the input signal VIN with respect to a virtual reference signal existing between VREF2 and VREF2.

According to the present invention, the first and second differential input stages Q10, Q11 and Q2 for comparing the first and second reference signals VREF1 and VREF2 with the input signal VIN, respectively.
0, Q21 and the first and second inverted comparison output currents IB,
Dividing means Q12 to Q14, Q14N to Q12N and Q for dividing the ID and the in-phase comparison output currents IA and IC, respectively.
22 to Q24 and Q24N to Q22N are shared (Q72 to Q74, Q74N to Q72N and Q82).
-Q84, Q84N-Q82N).

Further, in the present invention, the first differential input stage comprises a differential pair of first and second transistors Q10 and Q11, and has an input signal VIN and a first reference signal VREF1.
And outputs the result of comparison with the first inversion comparison output current IB and the first in-phase comparison output current IA, and the second differential input stage outputs the differential pair of the third and fourth transistors Q20 and Q21. Then, the comparison result of the input signal VIN and the second reference signal VREF2 is output as the second inverted comparison output current ID and the second in-phase comparison output current IC, and the shunt means is connected to the first differential input stage. 5th, 6th, and 6th grounded bases connected in cascade
Seventh, eighth, ninth, and tenth transistors Q12, Q
13, Q14 and Q14N, Q13N, Q12N and second
11th, 12th, and 13th cascaded to the differential input stage of
And the fourteenth, fifteenth, and sixteenth transistors Q22, Q
23, Q24 and Q24N, Q23N, Q22N, and divides the first inversion comparison output current IB and the first in-phase comparison output current IA at a ratio of 1: 1: 2 respectively, and at the same time the second inversion comparison output current The ID and the second in-phase comparison output current IC are shunted at a ratio of 1: 1: 2, respectively, and the interpolation output stage has the first and second inversion comparison output currents IB and I.
Composite inverted output current I obtained by adding D at a rate of 1/2
F is generated by commonly connecting the collectors of the sixth and eleventh transistors Q13 and Q22, and the combined inverting output current IF and the first and second in-phase comparison output currents IA are generated.
And IC, and a combined in-phase output current IE obtained by adding the first and second in-phase comparison output currents IA and IC at a ratio of ½, the collectors of the tenth and fourteenth transistors Q13N and Q24N. Is generated by common connection and is present between the first and second reference signals VREF1 and VREF2 by comparing the combined in-phase output current IE and the first and second inverted comparison output currents IB and ID. The comparison result of the input signal VIN with respect to the virtual reference signal is obtained.

Further, in the present invention, the interpolation output stage is
Combined inverted output current IF, first inverted comparison output current I
B, the combined in-phase output current IE, the output terminal through which the first in-phase comparative output current IA respectively flows, and the shunt transistors (Q13, Q22), Q14, (Q13N, Q24).
N) and Q12N have the same emitter area and the bases are grounded so that the seventeenth, eighteenth, nineteenth and twentieth transistors Q43, Q44, Q43N, Q42N are connected in cascade.

[0018]

In the interpolation output stage of the lower comparison section which constitutes the analog digital conversion circuit, the combined output currents IE and IF of the first and second in-phase comparison output currents IA, IC and inverting comparison output currents IB, ID are compared. Then, the comparison output currents IB, ID and IA, IC which are in opposite phase are compared with each other. As a result, the number of transistors required to form the comparison circuit is markedly reduced as compared with the conventional case, and as a result, the circuit area of the analog digital conversion circuit can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall configuration of the embodiment (1-1) Configuration of A-D conversion circuit 50 In FIG. 1, reference numeral 50 indicates a so-called 2-step parallel type serial-parallel A-D conversion circuit as a lower comparator. Current interpolation type lower comparators CD51 to CD58
Is used to reduce the number of differential pairs forming the first-stage circuit of the lower comparator, thereby forming an A-D conversion circuit having a resolution of 6 bits without reducing the voltage required for the least significant digit (1LSB). It is done like this.

Here, the A / D conversion circuit 50 uses the reference voltages VRT and VRB generated in the reference voltage generation circuit 51 as four reference potential sections (VRB to VU1, VU1 to VU2,
VU2 to VU3, VU3 to VRT) reference voltage V
U1, VU2, VU3 and the input signal VIN are compared in the upper comparators CU51 to CU53, and the comparison result is given to the upper encoder 52 (FIG. 2).

In the case of this embodiment, the upper encoder 52 outputs the code values which can be selected as the highest bit D1 by the redundancy correction function to the selection output section 53 as three sets of line signals SA, SB and SC, and also the switch. SW1
The lower reference potential selection signals X1 to X5 for switching SW4 and SD1 to SD16 are output to the reference voltage generation circuit 51,
The reference potential applied to the lower comparators CD51 to CD58 is switched.

At this time, the lower comparators CD51 to CD
Reference numeral 58 (FIG. 3) indicates the input signal V when the upper bit is encoded.
Switches SW1 to SW1 are used as reference potentials that divide the reference potential section detected as belonging to IN and the section for redundancy interpolation into eight.
Input is made via the switching blocks SD1 to SD16 which also serve as switches and a differential pair at the first stage of SW4 or a lower comparator.

Here, the lower comparators CD51 to CD5
8 is a comparison of each reference potential and the input signal VIN using a first stage differential pair. When a plurality of grounded base transistors cascode-connected to the differential pair are used, collector currents are divided into plural shunt collector currents having different current ratios. The output voltage generated by the combination of the divided shunt collector currents is compared.

The lower comparators CD51 to CD5
The reference numeral 8 outputs to the lower encoder 54 four sets of comparison outputs corresponding to the comparison output of the input signal VIN with respect to the virtual reference potential that divides the adjacent reference potentials into four.

The lower encoder 54 inputs these 32 (= 4) from the lower comparators CD51 to CD58.
X8) Lower 5 bits D2 to D6 based on the comparison output of the set
Is encoded and output.

The lower encoder 54 also generates selection signals XA, XB, and XC for correcting the code value of the highest bit D1 by the redundancy correction function and outputs the selection signals to the selection output unit 53, and the line signals SA, SB, and SC. One of them is output as the highest bit D1.

As a result, the A-D conversion circuit 50 operates as a 6-bit resolution A-D conversion circuit with a small linearity error.

(1-2) Lower Comparator CD51-C
Interpolation Principle Using Current Shunt in D58 In the case of this embodiment, the comparison output of a plurality of virtual reference potentials between two reference potentials and the input signal is a comparator to which the input signal VIN and the reference potential VREF1 are input. Input signal V
A composite current obtained by adding two sets of in-phase outputs of the comparator, to which IN and the reference potential VREF2 (= VREF1 + ΔV) are input, at a predetermined ratio, and one of the two sets of negative-phase outputs is compared with the opposite-phase output. Required by

This principle will be described using the two differential pairs 1 and 2 shown in FIG. Here, the differential pair 1 is the transistor Q
1 and Q2, the input signal VIN and the reference potential VREF1 are input to the base. The differential pair 2 is composed of transistors Q3 and Q4, and is adapted to input the input signal VIN and the reference potential VREF2 to the base.

At this time, the transistors Q1, Q2 and Q
Assuming that the collector currents flowing in 3 and Q4 are IA, IB, IC, and ID, respectively, the current values of the collector currents IA, IB, IC, and ID are inverted at the reference potentials VREF1 and VREF2, respectively, as shown in FIG. .

Therefore, the output voltages VA and VB appearing at the connection midpoints of the load resistors R1 and R2 through which the collector currents IA and IB flow and the transistors Q1 and Q2 are compared with each other by a comparator to input the input signal V to the reference potential VREF1.
The comparison output of IN can be obtained.

Further, the output voltages VC and VD appearing at the connection midpoints of the load resistors R3 and R4 through which the collector currents IC and ID flow and the transistors Q3 and Q4 are compared by a comparator, and the input signal VIN to the reference potential VREF2 is compared.
The comparison output of can be obtained.

Similarly, the collector currents IA and ID are inverted at an intermediate potential V2 (= VREF1 + ΔV / 2) between the reference potential VREF1 and the reference potential VREF2 (= VREF1 + ΔV), and the collector currents IB and IC are changed to the reference potential VREF2. Of the intermediate reference potential V2 (= VREF1 + ΔV / 2), the output voltages VA and VD or the output voltages VB and VC are compared using a comparator.
It is possible to obtain a comparison output of the input signal VIN for / 2).

It is considered to use this relationship to obtain a comparison output of the input signal VIN with respect to a virtual reference potential that divides the reference potential VREF1 and the reference potential VREF2 (= VREF1 + ΔV) into four.
Here, three currents of collector currents IA, IB and IC are used.

At this time, there is a characteristic that the collector current linearly increases and decreases between the difference voltage and the collector current in the range where the difference voltage is small. As shown in FIG. 6, they are substantially parallel to each other, and the collector current IB, which is the antiphase output of the differential pair 1, intersects in a range that can be regarded as a substantially straight line.

Therefore, if a combined collector current IE (that is, IA / 2 + IB / 2) can be generated by adding together the collector currents IA and IC at a ratio of ½, this combined collector current IE will be generated. The collector current IB and the combined collector current IE are equal to the currents IA and IC and parallel to the collector currents IA and IB. Therefore, the collector current IB and the combined collector current IE are divided into four reference potentials VREF1 and VREF2 by a virtual reference potential V1 (= VREF1 + ΔV / 4 ) At the border.

Therefore, if the output voltage VB generated by the collector current IB and the output voltage VE generated by the combined collector current IE are compared, a virtual reference potential V1 (= VREF1 + ΔV
It is possible to obtain a comparison output of the input signal VIN for / 4).

Since the same relationship holds for the three currents of collector currents IA, IB and ID, a combined collector current IF (that is, IB) is obtained by adding the collector currents IB and ID at a ratio of one half. / 2 + I
D / 2) is generated, and the output voltage VC generated by the collector current IC and the output voltage VF generated by the combined collector current IF are compared, the virtual reference potential V3 (= VREF1 + 3.
A comparison output of the input signal VIN with respect to ΔV / 4) can be obtained (FIG. 7).

That is, in this embodiment, two adjacent two
In-phase output IA, IC (or I of one of the two differential pairs)
B, ID) combined collector current IE (or IF) at a ratio of 1/2, and collector currents IB and I having a reverse phase relationship to the combined collector current IE (or IF).
The comparison output of the input signal VIN with respect to the virtual reference potentials V1, V2, V3 that divides the reference potentials VREF1 and VREF2 into four equal parts is interpolated on the basis of the comparison with D (or IA, IC) respectively.

(1-3) Lower Comparator CD51-C
Structure of D58 In FIG. 8, reference numeral 10 generally indicates a lower comparator section using this principle, and three adjacent reference potentials VREF are provided.
Virtually divides the reference potentials VREF1 and VREF2 and VREF2 and VREF3 into four equal parts by dividing the collector current, which is a comparison output of 1, VREF2 and VREF3 and the input signal VIN, at a current ratio of 1: 2, and then adding them in combination. A comparison output of the input signal VIN with respect to the reference potential is obtained.

In the case of this embodiment, each of the differential input stages 11, 12 and 13 forming the first stage circuit of the lower comparator has the same structure, and one of the transistors Q10 and Q20 forming a differential pair. And input signal V to Q30
Input IN and the other transistors Q11, Q21, Q2
By supplying the reference potentials VREF1, VREF2 and VREF3 to 2, the collector current corresponding to the signal level of the input signal VIN with respect to each reference potential is drawn.

Here, a transistor (Q1
0, Q11), (Q20, Q21) and (Q30, Q3
The collector of 1) has a base-grounded shunt transistor (Q12, Q13, whose emitter area ratio is 1: 1: 2).
Q14, Q14N, Q13N, Q12N), (Q22,
Q23, Q24, Q24N, Q23N, Q22N) and (Q32, Q33, Q34, Q34N, Q33N, Q3
2N) are respectively cascode-connected to divide the comparison collector current according to the emitter area ratio.

Further, in each differential input stage, the collectors of the shunt transistors (Q13, Q22) and (Q13N, Q24N) for shunting the collector current to one quarter of the adjacent differential input stages are commonly connected. Is done like
An output voltage is obtained by combining two sets of shunt collector currents that are in phase with each other.

As a result, the transistors Q14 and Q24
Assuming that the shunt collector currents flowing in the IA and IC are IA and IC, the load resistor R13 connected to the common collector of the transistors Q13 and Q22 is a combined collector current IE obtained by combining the shunt collector currents IA and IC at a ratio of ½. (= IA / 2 + IC / 2) flows.

Similarly, assuming that the shunt collector currents flowing in the transistors Q12 and Q22N are IB and ID, the shunt collector currents IB and ID are supplied to the load resistor R13N connected to the common collector of the transistors Q13N and Q24N.
Therefore, a combined collector current IF (= IB / 2 + ID / 2), which is a combination of 1 and 2, will flow.

Incidentally, the transistors (Q13, Q
14, Q13N, Q12N), (Q23, Q24, Q2
3N, Q22N) ... have load resistors (R13, R14, R13N, R12N), (R2) having the same resistance value.
(3, R24, R23N, R22N) ... are connected, the output voltage corresponding to the current value of the shunt collector current and the combined collector current shunted according to the ratio of the transistor emitter area is connected to each load resistor. can get.

In the case of this embodiment, the reference potentials VREF1 and VREF
The comparison output for the virtual reference potential that divides the potential between REF2 into four is obtained by comparing the output voltage of each load resistor. That is, the comparison output of the input signal VIN with respect to the reference potentials VREF1 and VREF2 is determined by comparing the output voltages of the load resistor R14 and the load resistor R12N, respectively, and
4 and the output voltage of the load resistance R22N.

Further, by comparing the output voltages of the load resistors R12N and R24, two reference potentials VREF1 and VREF1 are obtained.
Virtual reference potential V2 (= VREF1 + ΔV /
It is designed to obtain a comparative output of the input signal VIN for 2).

The load resistance R through which the combined collector current flows
13 is compared with the output voltage of the load resistor R12N through which the shunt collector current flows, to divide the reference potential VREF1 and the intermediate potential V2 into two (that is, divide the reference potential VREF1 and VREF2 into four), which is a virtual reference potential V1 (= VREF1 + ΔV /
It is arranged to obtain a comparative output of the input signal VIN with respect to 4).

Similarly, the output voltage of the load resistor R13N through which the combined collector current flows and the output voltage of the load resistor R24 through which the shunt collector current flows are compared to divide the reference potential VREF2 and the intermediate potential V2 into two (that is, the reference potentials VREF1 and VREF1).
Virtual reference potential V3 (= VREF1 + 3 that divides REF2 into four)
・ A comparison output of the input signal VIN with respect to ΔV / 4) is obtained.

(2) Operation of the embodiment In the above-mentioned configuration, the AD conversion circuit 50 inputs the input signal VIN to the upper comparators CU51 to CU53, compares it with the reference voltages VU1 to VU3, and outputs the lines according to the comparison output. The signals SA to SC are supplied to the selection output section 53, and
At this time, the reference potential to which the input signal VIN belongs and the reference potential for dividing the redundancy correction section into eight are switched by the lower reference potential selection signals X1 to X5, and the lower comparator C
It is given to the first stage differential pair of D51 to CD58.

At this time, eight pairs of lower comparators CD51
Of CD58, lower comparators CD51 and CD53
And the reference potentials VREF1 and VREF2 to the first differential pair of CD55.
And VREF3, the input signal VIN will be referred to as the reference potential VREF1 and the adjacent reference potentials VREF2 and VREF3.
The interpolating operation of the four-division interpolation type comparison circuit when increasing the number of components will be described.

First, when the input signal VIN exceeds the reference potential VREF1 (intersection P1 in FIG. 7), the current difference between the shunt collector current IA flowing through the load resistor R14 and the shunt collector current IB flowing through the load resistor R12N gradually decreases, When the voltage value of the input signal VIN exceeds the reference potential VREF1, the load resistance R
14 and the comparison output of the comparator for comparing the output voltage of the load resistor R12N are inverted.

Further, when the voltage value of the input signal VIN is gradually increased, the shunt collector current IB flowing through the load resistor R12N and the combined collector current (IA) flowing through the load resistor R13.
/ 2 + IC / 2) gradually decreases, and when the voltage value of the input signal VIN exceeds a virtual reference potential V1 that divides the reference potentials VREF1 and VREF2 into four equal parts, the output voltage of the load resistor R12N and the load resistor R13 is changed. The comparison output of the comparator to be compared is newly inverted.

When the voltage value of the input signal VIN is further increased, first, when the voltage value of the input signal VIN exceeds the virtual reference potential V2, the current values of the shunt collector current IB and the IC are inverted, and the load resistance R12N and the load resistance R24. The comparison output of the comparator that compares the output voltages will be inverted.

Similarly, when the voltage value of the input signal VIN exceeds the virtual reference potential V3, the current values of the shunt collector current IC and the combined collector current (IB / 2 + ID / 2) are inverted,
The comparison output of the comparator that compares the output voltages of the load resistor R13N and the load resistor R24 is inverted. When the voltage value of the input signal VIN exceeds the virtual reference potential VREF2, the shunt collector currents IC and ID are inverted, and the comparison output of the comparator that compares the output voltages of the load resistor R23 and the load resistor R22N is inverted.

As described above, the lower comparator section 10 adds two reference potentials VREF1 and VREF2 that are actually applied and virtual reference potentials V1, V2, and V3 that divide these into four.
A comparison output for can be obtained.

Next, adjacent reference potentials VREF2 and VREF3
As for the interval, the load resistor R21 through which the shunt collector current IC flows and the load resistor R23 through which the shunt collector current ID flows.
It is possible to detect that the voltage value of the input signal VIN exceeds the virtual reference potential VREF2 by the reversal of the output voltage of the load current R23N and the shunt collector current I which flow the combined collector current IH.
It can be determined that the input signal VIN exceeds the virtual reference potential V11 by the inversion of the output voltage of the load resistor R23 through which C flows.

Similarly, the input signal VIN exceeds the virtual reference potential V12 from the comparison output of the output voltages of the load resistors R22N and R32, and the input signal VIN is the virtual reference from the comparison output of the output voltages of the load resistors R23N and R32. It can be sequentially obtained that the potential V13 has been exceeded.

In this way, the reference potentials VREF1 and VREF2 adjacent to each other are compared with the input signal VIN, respectively, and the shunt collector currents IA, IB and IC are obtained by shunting the collector currents.
Among the IDs, the output voltages given by the shunt collector currents having the opposite phases to each other are compared, and the shunt collector currents IA, IC and IB, and ID are combined by a ratio of one half. By comparing the output voltages applied to the differential input stages 11 and 12 with each other, the input signal VIN to the virtual reference potentials V1, V2 and V3 that divides the reference potentials VREF1 and VREF2 into four equal parts, respectively.
The comparison output of can be obtained.

Other lower comparators CD53, CD54
The same comparison output is obtained for CD58 to CD58, and the lower encoder 54 has eight lower comparators CD51-C.
Four comparison outputs are input from D58.

As a result, the A / D conversion circuit 50 has the reference voltage generation circuit 51 having the same structure as the conventional reference voltage generation circuit 41.
Can be used to obtain an A / D converted output with 6-bit resolution.

(3) Effects of the Embodiments According to the above configuration, among the comparison outputs of the reference potentials VREF1 and VREF2 and the input signal VIN, the shunt collector currents IA, IC and IB, ID of the same phase are halved. The output voltage generated by the combined collector currents (IA / 2 + IC / 2) and (IB / 2 + ID / 2), which are added together in the ratio of, and the shunt collector currents IB and IC that are in the opposite phase to the combined collector current By comparing each with the generated output voltage, the reference potential VREF1 actually given
And virtual reference potentials V1, V2, V3 that divide VREF2 into four equal parts
It is possible to obtain a comparison output of the input signal VIN with respect to.

As a result, the number of elements required to form the lower comparator of the AD conversion circuit 50 may be six when using transistors having different emitter area ratios when looking at one differential input stage. , 8 if the transistors with the same emitter area are used, and the number of transistors required in the case of the conventional circuit (14 if the transistors with different emitter area ratios are used, 32 if the emitter areas are equal). This can be realized with a smaller number of elements, and the circuit area required for the comparator can be reduced to about 1/4.

(4) Other Embodiments In the above embodiment, the load resistors R13, R14, R13N, R12N ... Are directly connected to the collectors of the shunt transistors Q13, Q14, Q13N, Q12N. Although the case has been described, the present invention is not limited to this, and as shown in FIG.
Q14, Q13N, Q12N ... and load resistors R13, R
Transistor Q4 having the same emitter area between 14, R13N, R12N, ...
3, Q44, Q43N, Q42N ... May be cascaded.

In this way, the parasitic capacitance parasitic on the output end is apparently one, and can be reduced to half the capacitance value of the parasitic capacitance parasitic in the above-mentioned embodiment. As a result, the lower comparator section 20 can be operated at a higher speed.

In the above embodiment, the reference potential V
REF1 ... And transistors Q10 and Q11 forming a differential pair for comparing the input signal VIN and base-grounded transistor Q12 for shunting the collector current as a comparison output,
Although the case where Q13, Q14, ... Are separately configured has been described, the present invention is not limited to this, and as shown in FIG. 10, the transistors Q10 and Q11 configuring the differential input stage 11 and the collector currents connected to the collectors thereof are connected. Transistors Q12, Q13, Q14, Q14N, Q13N,
Q12N is a transistor Q73, Q74, Q75 and Q75N, Q74 having an emitter area ratio of 1: 1: 2.
Alternatively, N and Q73N may be used in common.

In this case, the number of elements required to form the lower comparator section can be realized with a much smaller number of elements, and the circuit area required for the comparator can be reduced.

Further, in the above embodiment, two adjacent
4 reference potentials VREF1 and VREF2 (= VREF1 + ΔV)
The case where the comparison output of the input signal VIN with respect to the divided virtual reference potentials V1, V2, V3 is obtained by interpolation has been described, but the present invention is not limited to this, and generally N (N is a natural number).
It can be widely applied to the case where the comparison output of the input signal VIN with respect to the divided virtual reference potential is obtained by interpolation.

In this case, two reference potentials VREF1 and VREF2
Dividing the difference voltage ΔV of N into N means that the intermediate potential ΔV / 2 of this difference voltage and the reference potential VREF1 or VREF2 are divided into N of 2 minutes. For example, when the voltage is divided into eight, it means that the difference voltage ΔV / 2 is divided into four as shown in FIG.

Therefore, the following equation

[Equation 1] Shunt collector current IA and shunt collector current I based on
If a combined collector current that internally divides B into (N / 2) -k: k (k = 0, 1 ... N / 2) is generated and these combined collector currents and the shunt collector current IB are compared, It is possible to divide the reference potential VREF1 and the intermediate potential (VREF1 + ΔV / 2) into N by 2 minutes.

Similarly, the shunt collector current IB and the shunt collector current ID are (N / 2) -k: k (k = 0, 1 ... N /
By generating a composite collector current internally divided in 2) and comparing each of these composite collector currents with the shunt collector current IC, it is possible to divide the intermediate potential (VREF1 + ΔV / 2) and the reference potential VREF2 into N of 2 minutes. it can.

Further, in the above-described embodiment, a pair of transistors Q1 and Q2, Q21 and Q2 forming a differential pair.
The case where a plurality of transistors having different emitter area ratios are directly cascode-connected to shunt the collector current has been described in 2 ..., but the present invention is not limited to this, and is used for shunting in order to reduce variations in the current ratio. An emitter resistance may be added to the emitter of the transistor.

Further, in the above embodiment, a plurality of cascode transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9 (Q3N, Q3N,
Q4N, Q5N, Q6N, Q7N, Q8N, Q9N) has been described for the case where the emitter area ratio is set to 1: 2: 3: 4: 3: 2: 1, but the present invention is not limited to this and other ratios are used. It may be set to.

Further, in the above-mentioned embodiments, the case where the present invention is used in the 2-step parallel type A-D conversion circuit has been described, but the present invention is not limited to this, and is widely applied as a series-parallel type comparison stage. obtain.

[0077]

As described above, according to the present invention, the first and second in-phase comparison output currents are combined at a predetermined ratio in the interpolation output stage forming the lower comparison unit of the analog digital conversion circuit. The combined in-phase output current and the first and second inverted comparison output currents having opposite phases to the combined output current are compared, and the first and second inverted comparison outputs are compared with the combined inverted output current at a predetermined ratio. The first and second in-phase comparison output currents that are in opposite phase to the combined output current are compared. As a result, the number of transistors required to form the lower comparison unit is significantly reduced as compared with the conventional case, and the circuit area of the analog digital conversion circuit can be further reduced.

[Brief description of drawings]

FIG. 1 is an analog digital conversion circuit 50 according to the present invention.
FIG. 3 is a block diagram showing one example.

FIG. 2 is a schematic connection diagram for explaining the reference voltage generating circuit.

FIG. 3 is a schematic connection diagram for explaining the lower comparator.

FIG. 4 is a connection diagram for explaining a principle of interpolation by shunting a collector current in a lower comparator.

FIG. 5 is a characteristic curve diagram showing a relationship between a collector current flowing in a differential pair to which different reference potentials are applied and an input signal.

FIG. 6 is a characteristic curve diagram showing a relationship between a combined collector current combined at a predetermined ratio and a collector current flowing with respect to a reference potential.

FIG. 7 is a characteristic curve diagram for explaining an interpolation process of a virtual reference potential using a combined collector current.

FIG. 8 is a connection diagram showing a configuration of a lower comparator.

FIG. 9 is a connection diagram for explaining another embodiment.

FIG. 10 is a connection diagram for explaining another embodiment.

FIG. 11 is a characteristic curve diagram for explaining N-division interpolation.

FIG. 12 is a schematic connection diagram for explaining a conventional serial-parallel AD conversion circuit.

[Explanation of Codes] 50 ... A / D conversion circuit, 52 ... Upper encoder, 5
3 ... Selection output section, 54 ... Lower encoder, CU, C
D: Comparison section, VIN: Input analog signal, VREF1, V
REF2, VREF3 ... Reference potential, V1, V2, V3 ... Virtual reference potential.

Claims (4)

[Claims] 1. In a serial-parallel type analog digital conversion circuit which executes a conversion operation from an analog signal to digital data by dividing it into a plurality of stages and executes the conversion operation, a lower comparison section used for the conversion operation is the same as the first reference signal. A first differential input stage that inputs an input signal and outputs a first inverted comparison output current and a first in-phase comparison output current with respect to the first reference signal, a second reference signal and the input signal. A second differential input stage for inputting and outputting a second inverted comparison output current and a second in-phase comparison output current with respect to the second reference signal, and the first and second inverted comparison output currents and an in-phase The shunting means for shunting the comparative output currents at a predetermined ratio respectively, and the combined inverting output currents are generated by adding the shunted first and second inverting comparative output currents at a predetermined ratio. And a second in-phase comparison output current are added together at a predetermined ratio to generate a combined in-phase output current, and the first and second in-phase comparison output currents having the opposite phase to the combined inverted output current and the combined current. Comparing the input signal with respect to a virtual reference signal existing between the first and second reference signals by comparing first and second inverted comparison output currents that are in opposite phase with respect to the inverted output current, respectively. An analog digital conversion circuit having an interpolation output stage for obtaining a result. 2. The first and second differential input stages for respectively comparing the first and second reference signals with the input signal, the first and second inverting comparison output currents, and the in-phase comparison output. 2. The analog digital conversion circuit according to claim 1, wherein the analog digital conversion circuit is also used as a shunt means for shunting a current at a predetermined ratio. 3. The first differential input stage includes a differential pair of first and second transistors, and outputs a comparison result of the input signal and the first reference signal as a first inverted comparison output. Current and a first in-phase comparison output current, the second differential input stage comprises a differential pair of third and fourth transistors and compares the input signal with the second reference signal. The result is output as a second inverted comparison output current and a second in-phase comparison output current, and the shunting means are fifth, sixth and seventh grounded bases that are cascade-connected to the first differential input stage. And 8th, 9th, 1st
0th transistor and the 11th, 12th, 13th and 14th, 15th, 1st which are cascade-connected to the second differential input stage.
6 transistors, and the first inversion comparison output current and the first in-phase comparison output current are 1: 1:
The second inverting comparison output current and the second in-phase comparison output current are shunted to a ratio of 1: 1: 2, respectively, and the interpolation output stage is configured to A combined inverted output current obtained by adding the inverted compared output currents at a rate of ½ is generated by commonly connecting the collectors of the sixth and eleventh transistors, and the combined inverted output current and the first and first While comparing with the in-phase comparison output current of 2,
The combined in-phase output current obtained by adding the first and second in-phase comparative output currents at a ratio of ½ is the tenth and first
4 is generated by commonly connecting the collectors of the four transistors, and is compared between the combined in-phase output current and the first and second inversion comparison output currents to generate a virtual signal existing between the first and second reference signals. The analog digital conversion circuit according to claim 1, wherein a comparison result of the input signal with respect to the reference signal is obtained. 4. The interpolation output stage includes an output terminal through which the composite inverted output current, the first inverted comparison output current and the composite in-phase output current, and the first in-phase comparison output current respectively flow and each for shunting. The seventeenth, eighteenth and first bases having the same emitter area between the transistors and having their bases grounded
The analog digital conversion circuit according to claim 1, wherein the ninth and twentieth transistors are connected in series.