JP3219213B2 - Analog digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIG. 12) Problems to be Solved by the Invention Means for Solving Problems (FIGS. 1, 8 to 10) Action (FIG. 7) Example (FIGS. 1 to 11) (1) Overall Configuration of Embodiment (FIGS. 1 to 8) (1-1) Configuration of A / D Converter Circuit 50 (FIGS. 1 to 3) (1-2) Current Shunt in Lower Comparators CD51 to CD58 Interpolation Principle Used (FIGS. 4 to 7) (1-3) Configuration of Lower Comparators CD51 to CD58 (FIG. 8) (2) Operation of Embodiment (3) Effects of Embodiment (4) Other Embodiments (FIG. 9 to 11) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter and, more particularly, to an analog-to-digital converter suitable for use in a serial-parallel analog-to-digital converter.

[0003]

2. Description of the Related Art Conventionally, in various fields such as audio equipment and measuring instruments, an analog digital conversion circuit (hereinafter referred to as an AD conversion circuit) for digitally processing various analog signals such as audio signals to be recorded or reproduced. That)
Is generally converted to digital data by using, and various conversion methods are considered according to the application field, required accuracy, speed, and the like.

In particular, when high-speed operation and high accuracy are required, a parallel (flash) type A / D conversion circuit and a series-parallel (subranging) type A / D conversion circuit are generally used. In particular, the serial-parallel A / D converter has an advantage that the number of elements can be greatly reduced as compared with the parallel A / D converter.

[0005] This serial-parallel A / D conversion circuit uses an input signal V
IN is converted into digital data in two stages of upper bits and lower bits, and this type of serial-parallel A-
When a video signal is to be processed also in the D conversion circuit, a two-step parallel A / D conversion circuit 40 is mainly used (FIG. 12).

The A / D conversion circuit 40 has a reference voltage generation circuit 4 composed of 16 reference resistors R connected in series.
1, the reference voltages VU1 and VU corresponding to the upper two bits.
U2, VU3, and the three sets of reference voltages VU1, VU
U2, VU3 and the input signal VIN are connected to the upper comparator CU.
1, CU2 and CU3 compare. Then, by supplying the comparison output to the upper encoder 42, the most significant bit D1 is generated.

The upper encoder 42 switches the switch group SW based on the comparison output of the upper comparators CU1, CU2 and CU3, thereby subdividing the voltage band to which the upper two bits belong, and the upper and lower sides of the voltage band. A total of eight reference voltages VD1, VD2,..., VD8, which are the reference voltages for redundancy correction prepared in FIG.

The lower comparators CD1, CD2,
.., And these eight reference voltages VD1, VD in CD8
D2,..., VD8 are compared with the input signal VIN, and the comparison output is supplied to the lower encoder 43 to generate the remaining lower three bits D2, D3, D4.

[0009]

However, the resolution is 10
When the bit becomes as small as ~ 12 bits, the voltage of the least significant digit (1 LSB) required for the A / D conversion circuit 40 becomes very small at about 1 [mV], and as the number of bits increases, the lower comparators CD1, CD2,. .., The effect of the base-emitter voltage ΔVBE of the transistor constituting the differential pair of CD8 cannot be ignored.

Therefore, the comparison output of the input signal VIN and the intermediate potential of adjacent reference potentials is obtained by interpolation by combining and comparing a plurality of comparison outputs of the comparator, and this interpolation processing is necessary for signal comparison. An interpolation method for eliminating the influence of the base-emitter voltage ΔVBE by reducing the number of comparators is under study.

As one of such interpolation methods, a load resistance of a differential amplifier circuit constituting a comparator is formed as a resistor string of resistors having a predetermined resistance ratio, and an output voltage obtained as a difference voltage between connection taps of each resistor. Have been proposed to obtain a comparison output between an input signal and an intermediate potential that equally divides a reference potential by combining.

In this case, however, an extra differential amplifying stage for interpolation is required one by one, and a plurality of differential outputs with different resistance values are compared. As a result, it is not suitable for use in a lower comparator constituted by a serial-parallel A / D conversion circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a comparison output between an input signal and a plurality of virtual reference potentials which divide the reference potential with a significantly smaller number of elements than in the prior art. It is intended to propose an A / D conversion circuit having a comparison circuit which can perform the following.

[0014]

According to the present invention, there is provided a serial-to-parallel analog-to-digital conversion circuit for performing a conversion operation of converting an analog signal into digital data in a plurality of stages. The first reference signal VREF1 and the input signal VIN are input to the lower comparison unit used for the operation, and the first inverted comparison output current (IB + IB / 2 + IB /) for the first reference signal VREF1 is input.
2) and the first in-phase comparison output current (IA + IA / 2 + I
A / 2), a second differential input stage 11, a second reference signal VREF2 and an input signal VIN, and a second inversion comparison output current (ID +) for the second reference signal VREF2.
ID / 2 + ID / 2) and the second common-mode comparison output current (I
C + IC / 2 + IC / 2), and the first and second inverted comparison output currents (IB + IB /
2 + IB / 2), (ID + ID / 2 + ID / 2) and the first and second in-phase comparison output currents (IA + IA / 2 + IA /
2) Dividing means (Q14N, Q13N, Q12) for dividing (IC + IC / 2 + IC / 2) at predetermined ratios, respectively.
N), (Q24N, Q23N, Q22N) and (Q1
2, Q13, Q14), (Q22, Q23, Q24)
And the first and second inverted comparison output currents IB / 2 and ID / 2 divided at the predetermined ratio to generate a combined inverted output current IF, and the second inverted divided output current IF divided at the predetermined ratio. The first and second in-phase comparison output currents IA /
2 and IC / 2 are added to generate a combined in-phase output current IE, and the first and second in-phase comparison output currents IA and IB shunted at a predetermined ratio that is opposite in phase to the combined inversion output current IF IC and the first and second currents shunted at a predetermined ratio that are opposite in phase to the combined in-phase output current IE.
And an interpolation output stage that obtains a comparison result of the input signal VIN with respect to a virtual reference signal existing between the first and second reference signals VREF1 and VREF2 by comparing the inverted comparison output currents IB and ID, respectively. I made it.

Further, in the present invention, the first and second differential input stages Q10, Q11 and Q for comparing the first and second reference signals VREF1 and VREF2 with the input signal VIN, respectively.
20, Q21 and the first and second inverted comparison output currents (IB
+ IB / 2 + IB / 2), (ID + ID / 2 + ID /
2) and the first and second common-mode comparison output currents (IA + IA /
2 + IA / 2) and (IC + IC / 2 + IC / 2) at predetermined ratios.
14N to Q12N, Q22 to Q24 and Q24N to Q2
2N and QN (Q72N-Q74N, Q
74N to Q72N and Q82 to Q84, Q84N to Q8
2N.

Further, in the present invention, the first differential input stage 11 includes first and second transistors Q10 and Q1.
1 differential pair, and the input signal VIN and the first reference signal V
The result of comparison with REF1 is converted to the first inverted comparison output current (IB + I
B / 2 + IB / 2) and the first common-mode comparison output current (IA
+ IA / 2 + IA / 2), and the second differential input stage 12 includes third and fourth transistors Q20 and Q2.
1 differential pair, the input signal VIN and the second reference signal V
The result of comparison with REF2 is converted to a second inverted comparison output current (ID + I
D / 2 + ID / 2) and the second common-mode comparison output current (IC
+ IC / 2 + IC / 2), and the shunt means includes a fifth, sixth, seventh, eighth, ninth, and tenth transistor Q14N having a common base cascade-connected to the first differential input stage 11. , Q13N, Q12N and Q12, Q13, Q
Fourteenth, twelfth, thirteenth and fourteenth, sixteenth and sixteenth transistors Q24N, Q23N, Q22N, and Q2 having a common base cascade-connected to the second and fourth differential input stages.
2, the first inversion comparison output current (IB + IB / 2 + IB / 2) and the first in-phase comparison output current (IA + IA / 2 + IA / 2) are 1: 1:
2 and the second inverted comparison output current (ID + ID / 2 + ID / 2) and the second in-phase comparison output current (IC + IC / 2 + IC / 2) are respectively 1: 1:
2, and the interpolation output stage outputs first and second inverted comparison output currents (IB + IB / 2 + IB / 2) and (ID
+ ID / 2 + ID / 2) at a rate of 1/4 to generate a combined inverted output current IF (= IB / 2 + ID / 2) by commonly connecting the collectors of the sixth and eleventh transistors Q13N and Q24N. Then, while comparing the combined inverted output current IF with the divided first and second common-mode comparison output currents IA and IC, the first and second common-mode comparison output currents (IA + IA / 2 + IA / 2) and ( IC + IC / 2 + IC / 2) is added at a quarter ratio to generate a combined in-phase output IE (= IA / 2 + IC / 2) by connecting the collectors of the ninth and fourteenth transistors Q13 and Q22 in common. By comparing the combined common-mode output current IE with the divided first and second inverted comparison output currents IB and ID, the first and second reference signals VREF1 and VREF1 are compared. The comparison result of the input signal VIN with respect to the virtual reference signal existing between REF2 is obtained.

Further, in the present invention, the interpolation output stage comprises:
The combined inverted output current IF, the first and second inverted comparison output currents IB and ID divided at a predetermined ratio, the combined in-phase output current IE, and the first and second in-phase comparison output currents divided at a predetermined ratio The same emitter area is provided between the output terminals through which the IA and IC flow, and the respective transistors (Q13N, Q24N) and (Q12N, Q22N) and (Q13, Q22) and (Q14, Q24) for shunting, and the grounded base. 17th and 18th, 19th, 20th, 21st, and 22nd transistors Q43N and Q43
42N, Q52N and Q43 and Q44, Q54 are cascaded.

[0018]

The first and second in-phase comparison output currents IA and IC divided at a predetermined ratio and the first and second inversion comparison outputs at the interpolation output stage of the lower-order comparison unit constituting the analog digital conversion circuit. The first and second in-phase comparison output currents IA which are opposite in phase to the combined inverted output current IF and combined in-phase output current IE among the currents IB and ID
And IC and first and second inverted comparison output currents IB and I
And D respectively. As a result, the number of transistors required to configure the comparison circuit can be significantly reduced as compared with the conventional case, and as a result, the circuit area of the analog-to-digital conversion circuit can be reduced.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Overall Configuration of Embodiment (1-1) Configuration of A / D Converter Circuit 50 In FIG. 1, reference numeral 50 denotes a so-called two-step parallel type serial / parallel A / D converter circuit as a whole. Current interpolation type lower comparators CD51 to CD58
Is used to reduce the number of differential pairs constituting the first stage circuit of the lower comparator, and to form an A / D converter having a resolution of 6 bits without reducing the voltage required for the least significant digit (1 LSB). It has been made like that.

Here, the AD conversion circuit 50 converts the reference voltages VRT and VRB generated by the reference voltage generation circuit 51 into four reference potential sections (VRB to VU1, VU1 to VU2,
VU2 to VU3, VU3 to VRT)
U1, VU2, and VU3 are compared with the input signal VIN in the upper comparators CU51 to CU53, and the comparison result is given to the upper encoder 52 (FIG. 2).

In the case of this embodiment, the upper encoder 52 outputs code values that can be selected as the most significant bit D1 by the redundancy correction function to the selection output unit 53 as three sets of line signals SA, SB, and SC, and switches. SW1
SW4 and lower reference potential selection signals X1 to X5 for switching SD1 to SD16 are output to the reference voltage generation circuit 51;
The reference potentials applied to the lower comparators CD51 to CD58 are switched.

At this time, the lower comparators CD51 to CD51
58 (FIG. 3) indicates the input signal V when encoding the upper bits.
Switches SW1 to SW4 are used to divide a reference potential section detected as belonging to IN and a reference potential section for dividing a section for redundancy interpolation into eight.
SW4 or the first stage differential pair of the lower comparator and the switch are used for inputting via switching blocks SD1 to SD16.

Here, the lower comparators CD51 to CD5
8 compares each reference potential with the input signal VIN using a first-stage differential pair, and uses a plurality of common-base transistors cascode-connected to this differential pair to generate a plurality of shunt collector currents having different current ratios. And the output voltages generated by the combination of the divided shunt collector currents are compared.

The lower comparators CD51 to CD5
Reference numeral 8 denotes to the lower encoder 54 four sets of comparison outputs corresponding to the comparison output of the input signal VIN with respect to the virtual reference potential for dividing the adjacent reference potential into four.

The lower encoder 54 receives these 32 (= 4) input from the respective lower comparators CD51 to CD58.
× 8) Lower 5 bits D2 to D6 based on comparison output of set
Is encoded and output.

The lower encoder 54 generates selection signals XA, XB, XC for correcting the code value of the most significant bit D1 by the redundancy correction function, outputs the selection signals to the selection output section 53, and outputs the line signals SA, SB, SC. Is output as the most significant bit D1.

Thus, the A / D conversion circuit 50 operates as a 6-bit resolution A / D conversion circuit having a small linearity error.

(1-2) Lower Comparators CD51-CD
Interpolation Principle Using Current Dividing in D58 In the case of this embodiment, a comparison output between a plurality of virtual reference potentials between two reference potentials and an input signal is determined by a comparator to which an input signal VIN and a reference potential VREF1 are input. Input signal V
A composite current obtained by adding two sets of in-phase outputs of a comparator to which IN and the reference potential VREF2 (= VREF1 + ΔV) are input at a predetermined ratio is compared with one of the two sets of negative-phase outputs. It is required by

The principle will be described with reference to two differential pairs 1 and 2 shown in FIG. Here, the differential pair 1 is a transistor Q
1 and Q2. The input signal VIN and the reference potential VREF1 are input to the base. Further, the differential pair 2 is constituted by transistors Q3 and Q4, and the input signal VIN and the reference potential VREF2 are inputted to the base.

At this time, the transistors Q1, Q2 and Q
3, if the collector currents flowing through Q4 are IA, IB, IC, and ID, respectively, as shown in FIG. 5, the current values of the collector currents IA, IB, IC, and ID are inverted around the reference potentials VREF1 and VREF2, respectively. .

Accordingly, the output signals VA and VB appearing at the connection midpoint between the transistors Q1 and Q2 and the load resistors R1 and R2 through which the collector currents IA and IB flow are compared by a comparator, whereby the input signal V for the reference potential VREF1 is obtained.
The comparison output of IN can be obtained.

The output voltages VC and VD appearing at the connection point between the transistors Q3 and Q4 and the load resistors R3 and R4, through which the collector currents IC and ID flow, are compared by a comparator, so that the input signal VIN with respect to the reference potential VREF2 is obtained.
Can be obtained.

Similarly, the collector currents IA and ID are inverted at an intermediate potential V2 (= VREF1 + .DELTA.V / 2) between the reference potential VREF1 and the reference potential VREF2 (= VREF1 + .DELTA.V). The output voltages VA and VD or the output voltages VB and VC are compared using an intermediate potential V2 (= VREF1 + ΔV / 2) as a boundary, so that the virtual reference potential V2 (= VREF1 + ΔV)
/ 2) can be obtained as a comparison output of the input signal VIN.

Using this relationship, consider obtaining a comparison output of the input signal VIN with respect to a virtual reference potential that divides the reference potential VREF1 and the reference potential VREF2 (= VREF1 + ΔV) into four.
Here, three currents of the collector currents IA, IB and IC are used.

At this time, since the collector current linearly increases and decreases between the difference voltage and the collector current in a range where the difference voltage is small, the collector currents IA and IC which are the in-phase outputs of the differential pairs 1 and 2 are equal to each other. As shown in FIG. 6, the collector currents IB, which are substantially in parallel with each other and output in opposite phases of the differential pair 1, intersect in a range that can be regarded as a substantially straight line.

Therefore, if a combined collector current IE (ie, IA / 2 + IC / 2) can be generated by adding the collector currents IA and IC at a ratio of 1/2, respectively, the combined collector current IE is equal to both collectors. Since the collector current IB and the combined collector current IE are equal to the currents IA and IC and are expressed as a straight line parallel to both collector currents IA and IC, the virtual reference potential V1 (= VREF1 + ΔV / 4) which divides the reference potentials VREF1 and VREF2 into four. ).

Accordingly, when the output voltage VB generated by the collector current IB is compared with the output voltage VE generated by the combined collector current IE, the virtual reference potential V1 (= VREF1 + ΔV)
/ 4) can be obtained as a comparison output of the input signal VIN.

Since the same relationship holds for the three currents of the collector currents IC, IB and ID, the combined collector current IF (that is, IB) is obtained by adding the collector currents IB and ID by a half. / 2 + I
D / 2) and comparing the output voltage VC generated by the collector current IC with the output voltage VF generated by the combined collector current IF, the virtual reference potential V3 (= VREF1 + 3 ·
ΔV / 4) can be obtained as a comparison output of the input signal VIN (FIG. 7).

That is, in this embodiment, two adjacent
Common mode output IA, IC (or I
B, ID) at a ratio of one half of the combined collector current IE (or IF) and the collector currents IB, I having an opposite phase relationship to the combined collector current IE (or IF).
The comparison output of the input signal VIN with respect to the virtual reference potentials V1, V2, and V3, which divide the reference potentials VREF1 and VREF2 into four, is interpolated based on the principle of comparing D (also IA, IC), respectively.

(1-3) Lower Comparators CD51 to CD-C
Configuration of D58 In FIG. 8, reference numeral 10 denotes a lower comparator section which uses the above principle as a whole, and three sets of adjacent reference potentials VREF
1. After shunting a collector current, which is a comparison output between VREF2 and VREF3 and the input signal VIN, at a current ratio of 1: 2, and adding them in combination, the reference potentials VREF1 and VREF2 and VREF2 and VREF3 are equally divided into four. A comparison output of the input signal VIN with respect to the reference potential is obtained.

In this embodiment, each of the differential input stages 11, 12 and 13 constituting the first stage circuit of the lower comparator has the same configuration, and one of the transistors Q10 and Q20 forming a differential pair. And the input signal V to Q30
IN, and the other transistors Q11, Q21, Q2
2 is supplied with reference potentials VREF1, VREF2 and VREF3, so that a collector current corresponding to the signal level of the input signal VIN with respect to each reference potential is drawn.

Here, the transistors (Q1
0, Q11), (Q20, Q21) and (Q30, Q3
In the collector of (1), a common base shunt transistor (Q12, Q13, Q12, Q13) having an emitter area ratio of 1: 1: 2.
Q14, Q14N, Q13N, Q12N), (Q22,
Q23, Q24, Q24N, Q23N, Q22N) and (Q32, Q33, Q34, Q34N, Q33N, Q3
2N) are cascode-connected, and shunt the comparison collector current according to the emitter area ratio.

In each differential input stage, the collectors of shunting transistors (Q13, Q22) and (Q13N, Q24N) of adjacent differential input stages for shunting the collector current to one fourth are respectively connected in common. It is made as
An output voltage is obtained by combining two sets of shunt collector currents having an in-phase relationship with each other.

As a result, the transistors Q14 and Q24
Is a combined collector current IE obtained by combining the shunt collector currents IA and IC at a ratio of 1/2, respectively, to the load resistor R13 connected to the common collector of the transistors Q13 and Q22. (= IA / 2 + IC / 2) flows.

Similarly, transistors Q12N and Q22N
Are the shunt collector currents IB and ID, the load resistor R13N connected to the common collector of the transistors Q13N and Q24N has the shunt collector currents IB and I
A combined collector current IF (= IB / 2 + ID / 2), which is obtained by combining D at a ratio of 1/2, flows.

The reason is that each of the shunt transistors (Q13, Q
14, Q13N, Q12N), (Q23, Q24, Q2
3N, Q22N) are load resistors (R13, R14, R13N, R12N) and (R2
, R24, R23N, R22N) are connected, so that each load resistance has an output voltage corresponding to the current value of the shunt collector current divided according to the ratio of the emitter area of the transistor and the combined collector current. can get.

In the case of this embodiment, the reference potentials VREF1 and VREF1
The comparison output with respect to the virtual reference potential which divides the potential between REF2 into four is obtained by comparing the output voltage of each load resistor. That is, the comparison output of the input signal VIN with respect to the reference potentials VREF1 and VREF2 is obtained by comparing the output voltages of the load resistors R14 and R12N, respectively.
4 and a comparison output of the output voltage of the load resistor R22N.

Further, by comparing the output voltages of the load resistors R12N and R24, two reference potentials VREF1 and VREF1 are obtained.
Virtual reference potential V2 (= VREF1 + ΔV /
A comparison output of the input signal VIN with respect to 2) is obtained.

The load resistance R through which the combined collector current flows
13 and the output voltage of the load resistor R12N through which the shunt collector current flows, thereby dividing the reference potential VREF1 and the intermediate potential V2 into two (that is, dividing the reference potentials VREF1 and VREF2 into four), the virtual reference potential V1 (= VREF1 + ΔV /
A comparison output of the input signal VIN with respect to 4) is obtained.

Similarly, the output voltage of the load resistor R13N through which the combined collector current flows is compared with the output voltage of the load resistor R24 through which the shunt collector current flows, and the reference potential VREF2 and the intermediate potential V2 are divided into two (that is, the reference potentials VREF1 and VREF).
Virtual reference potential V3 (= VREF1 + 3)
.DELTA.V / 4) to obtain a comparison output of the input signal VIN.

(2) Operation of Embodiment In the above configuration, the AD converter circuit 50 inputs the input signal VIN to the upper comparators CU51 to CU53, compares the input signal VIN with the reference voltages VU1 to VU3, and outputs a signal corresponding to the comparison output. While supplying the signals SA to SC to the selection output unit 53,
At this time, the reference potential section to which the input signal VIN belongs and the reference potential for dividing the section for redundancy correction into eight are switched by the lower reference potential selection signals X1 to X5, and the lower comparator C
D51 to CD58.

At this time, the eight lower-order comparators CD51
To CD58, the lower comparators CD51 and CD53
And reference potentials VREF1, VREF2 to the differential pair at the first stage of CD55.
And VREF3, the input signal VIN is sequentially changed from the reference potential VREF1 to the adjacent reference potentials VREF2 and VREF3.
The interpolation operation of the four-division interpolation type comparison circuit when increasing the number will be described.

First, when the input signal VIN exceeds the reference potential VREF1 (intersection P1 in FIG. 7), the current difference between the shunt collector current IA flowing through the load resistor R14 and the shunt collector current IB flowing through the load resistor R12N gradually decreases. When the voltage value of the input signal VIN exceeds the reference potential VREF1, the load resistance R
The comparison output of the comparator that compares the output voltage of the load resistor 14 with the output voltage of the load resistor R12N is inverted.

Further, when the voltage value of the input signal VIN is gradually increased, the shunt collector current IB flowing to the load resistor R12N and the combined collector current (IA) flowing to the load resistor R13.
/ 2 + IC / 2) gradually decreases, and when the voltage value of the input signal VIN exceeds the virtual reference potential V1, which divides the reference potentials VREF1 and VREF2 into four, the output voltages of the load resistors R12N and R13 are reduced. The comparison output of the comparator to be compared is newly inverted.

When the voltage value of the input signal VIN is further increased, first, when the voltage value of the input signal VIN exceeds the virtual reference potential V2, the current values of the shunt collector current IB and the IC are inverted, and the load resistances of the load resistors R12N and R24 are inverted. The comparison output of the comparator that compares the output voltages is inverted.

Similarly, when the voltage value of the input signal VIN exceeds the virtual reference potential V3, the current values of the shunt collector current IC and the combined collector current (IB / 2 + ID / 2) are inverted.
The comparison output of the comparator that compares the output voltages of the load resistor R13N and the load resistor R24 is inverted. When the voltage value of the input signal VIN exceeds the virtual reference potential VREF2, the shunt collector currents IC and ID are inverted, and the comparison output of the comparator that compares the output voltages of the load resistors R24 and R22N is inverted.

As described above, the lower comparator section 10 provides the virtual reference potentials V1, V2, and V3 for dividing the reference potentials VREF1 and VREF2 into four in addition to the actually applied reference potentials VREF1 and VREF2.
Can be obtained.

Subsequently, adjacent reference potentials VREF2 and VREF3
The load resistance R24 through which the shunt collector current IC flows and the load resistance R23 through which the shunt collector current ID flows
Can detect that the voltage value of the input signal VIN exceeds the virtual reference potential VREF2 by the inversion of the output voltage of the load resistor R23 through which the combined collector current IH flows and the shunt collector current ID.
It can be determined that the input signal VIN has exceeded the virtual reference potential V11 by reversing the output voltage of the load resistor R22N through which the current flows.

Similarly, the comparison of the output voltages of the load resistors R22N and R34 indicates that the input signal VIN has exceeded the virtual reference potential V12, and the comparison of the output voltages of the load resistors R23N and R34 indicates that the input signal VIN has the virtual reference potential. It can be sequentially determined that the potential V13 has been exceeded.

As described above, the reference potentials VREF1 and VREF2 adjacent to each other are compared with the input signal VIN, and the shunt collector currents IA, IB and IC obtained by dividing the respective collector currents are obtained.
The output voltages given by the shunt collector currents having the opposite phase relationship among the IDs are compared with each other, and the shunt collector currents IA, IC and IB, and the ID are combined at a ratio of one-half. By comparing the output voltages supplied to the differential input stages 11 and 12, the input signals VIN for the virtual reference potentials V1, V2 and V3 which divide the reference potentials VREF1 and VREF2 supplied to the differential input stages 11 and 12 into four equal parts, respectively.
Can be obtained.

Other lower comparators CD53, CD54
To CD58, the same comparison output is obtained. The lower encoder 54 has eight sets of lower comparators CD51 to CD58.
Four comparison outputs are input from D58.

Thus, the A / D conversion circuit 50 has a reference voltage generation circuit 51 having the same configuration as the conventional reference voltage generation circuit 41.
Can be used to obtain an A / D conversion output with 6-bit resolution.

(3) Effect of Embodiment According to the above configuration, the shunt collector currents IA, IC, IB, and ID having the same phase among the comparison outputs of the reference potentials VREF1 and VREF2 and the input signal VIN are reduced by half. And the output voltage generated by the combined collector currents (IA / 2 + IC / 2) and (IB / 2 + ID / 2) and the shunt collector currents IB and IC that are in anti-phase relation to the combined collector current. By comparing the generated output voltages with the respective output voltages, the actually applied reference potential VREF1 is obtained.
Reference potentials V1, V2, V3 which divide VREF2 and VREF2 into four equal parts
Can be obtained as a comparison output of the input signal VIN.

As a result, the number of elements required to constitute the lower comparator of the AD conversion circuit 50 may be six when transistors having different emitter area ratios are used for one differential input stage. When transistors having the same emitter area are used, the number is eight, and the number of transistors required in the conventional circuit is 14 (when transistors having different emitter area ratios are used, and when the transistors have the same emitter area, 32). ), And the circuit area required for the comparator can be reduced to approximately one fourth.

(4) Other Embodiments In the above embodiment, load resistors R13, R14, R13N, R12N... Are directly connected to the collectors of the respective shunt transistors Q13, Q14, Q13N, Q12N. Although the case has been described, the present invention is not limited to this, and as shown in FIG.
Q14, Q13N, Q12N ... and load resistors R13, R
, R13N, R12N,... Having the same emitter area and a base-grounded transistor Q4
3, Q44, Q43N, Q42N... May be cascaded.

In this way, the parasitic capacitance at the output terminal becomes apparently one, which can be reduced to half of the parasitic capacitance in the case of the above embodiment. Thus, the lower comparator section 20 can be operated at a higher speed.

In the above embodiment, the reference potential V
, REF1... And an input signal VIN are compared, and transistors Q10 and Q11...
.. Have been described separately. However, the present invention is not limited to this. The transistors Q10 and Q11 forming the differential input stage 11 and the collector currents connected to their collectors as shown in FIG. Q12, Q13, Q14, Q14N, Q13N,
Transistors Q72, Q73, Q74 and Q74N, Q73 having an emitter area ratio of 1: 1: 2
N and Q72N may be shared.

In this case, the number of elements required to configure the lower comparator can be further reduced by a smaller number of elements, and the circuit area required for the comparator can be reduced.

Further, in the above embodiment, two adjacent
Four reference potentials VREF1 and VREF2 (= VREF1 + ΔV)
Although the case where the comparison output of the input signal VIN with respect to the divided virtual reference potentials V1, V2, and V3 is obtained by interpolation has been described, the present invention is not limited to this, and generally N (N is a natural number)
The present invention can be widely applied to a case where a comparison output of the input signal VIN with respect to the virtual reference potential to be divided is obtained by interpolation.

In this case, two reference potentials VREF1 and VREF2
Dividing the difference voltage ΔV into N means that the difference between the intermediate potential ΔV / 2 of the difference voltage and the reference potential VREF1 or VREF2 is divided into two by N. For example, in the case of dividing into eight, this means dividing the difference voltage ΔV / 2 into four as shown in FIG.

Therefore, the following equation

(Equation 1) Shunt collector current IA and shunt collector current I based on
A composite collector current which internally divides C into (N / 2) -k: k (k = 0, 1,... N / 2) is generated, and each of these composite collector currents is compared with the shunt collector current IB. The interval between the reference potential VREF1 and the intermediate potential (VREF1 + ΔV / 2) can be divided into N by two.

Similarly, the shunt collector current IB and the shunt collector current ID are expressed as (N / 2) -k: k (k = 0, 1,... N /
By generating a combined collector current internally divided into 2) and comparing each of these combined collector currents with the shunted collector current IC, it is possible to divide the intermediate potential (VREF1 + ΔV / 2) and the reference potential VREF2 by N for two minutes. it can.

Further, in the above-described embodiment, a case where a plurality of transistors having different emitter area ratios are directly cascode-connected to a pair of transistors Q10 and Q11, Q20 and Q21. However, the present invention is not limited to this, and an emitter resistor may be added to the emitter of the transistor used for the shunt in order to reduce the variation in the current ratio.

Further, in the above-described embodiment, a plurality of cascode transistors Q12, Q13, Q14, (Q14N, Q13N, Q1
Although the case where the emitter area ratio of 2N) is set to 1: 1: 2 has been described, the present invention is not limited to this, and another ratio may be set.

Further, in the above-described embodiment, the case where the present invention is applied to a two-step parallel type A / D conversion circuit has been described. However, the present invention is not limited to this, and is widely applied to a series-parallel type comparison stage. obtain.

[0077]

As described above, according to the present invention, the first and second in-phase comparison output currents are synthesized at a predetermined ratio in the interpolation output stage constituting the lower comparison section of the analog digital conversion circuit. The combined in-phase output current is compared with the first and second inverted comparison output currents that are out of phase with the combined output current, and the first and second inverted comparison outputs are compared with the combined inverted output current at a predetermined ratio. The combined output current is compared with the first and second in-phase comparison output currents having opposite phases. As a result, the number of transistors required to form the lower comparison section is significantly reduced as compared with the conventional case, and the circuit area of the analog digital conversion circuit can be further reduced.

[Brief description of the drawings]

FIG. 1 shows an analog digital conversion circuit 50 according to the present invention.
FIG. 4 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic connection diagram for explaining the reference voltage generation circuit.

FIG. 3 is a schematic connection diagram for explaining the lower comparator.

FIG. 4 is a connection diagram for explaining the principle of interpolation by shunting of a collector current in a lower comparator.

FIG. 5 is a characteristic curve diagram showing a relationship between a collector current flowing through a differential pair to which different reference potentials are applied and an input signal.

FIG. 6 is a characteristic curve diagram showing a relationship between a combined collector current combined at a predetermined ratio and a collector current flowing with respect to a reference potential.

FIG. 7 is a characteristic curve diagram for explaining a virtual reference potential interpolation process using a combined collector current.

FIG. 8 is a connection diagram showing a configuration of a lower comparator.

FIG. 9 is a connection diagram for explaining another embodiment.

FIG. 10 is a connection diagram for explaining another embodiment.

FIG. 11 is a characteristic curve diagram for explaining N-division interpolation.

FIG. 12 is a schematic connection diagram for explaining a conventional serial-parallel A / D conversion circuit;

[Explanation of symbols]

50: AD conversion circuit, 52: Upper encoder, 5
3 ... Selection output unit, 54 ... Lower encoder, CU, C
D: comparison unit, VIN: input analog signal, VREF1, V
REF2, VREF3 ... reference potential, V1, V2, V3 ... virtual reference potential.

Claims (4)

(57) [Claims] 1. A serial-parallel type analog-to-digital conversion circuit to perform in a plurality of stages of conversion of the above analog signal into digital data, the lower comparator unit used for the conversion operation, a first reference signal inputs the input signal, first inverting comparator output current and a first differential input stage for outputting a first phase comparison output current, the second reference signal and the input signal to the first reference signal And a second differential input stage for outputting a second inverted comparison output current and a second in-phase comparison output current with respect to the second reference signal; and the first and second inverted comparison output currents And the first and second
A shunt means for the in-phase comparison output current shunt, respectively at a predetermined ratio, and generates a composite inverted output current by causing Awa and legs of the first and second inverted comparison output current diverted by the predetermined ratio, generates a synthesized phase output current by causing Awa and legs of the first and second phase comparison output current diverted by the predetermined ratio, the shunt by the predetermined ratio as the opposite phase to the synthetic inverted output current first and second phase comparison output current is, by comparing each the first and second inverted comparison output current diverted by the predetermined ratio as the opposite phase to the synthesis phase output current And an interpolation output stage for obtaining a comparison result of the input signal with a virtual reference signal existing between the first and second reference signals. Wherein the said first and said first and second differential input stage a second reference signal and the said input signal for comparing each of said first, second inverting comparator output current and the second 1,
2. The analog-to-digital converter according to claim 1, wherein the common-mode comparison output current is shared with a shunting device that shunts the second in- phase comparison output current at a predetermined ratio. Wherein said first differential input stage is made of a differential pair of first and second transistors, inverting comparison result of the comparison the first and the input signal and the first reference signal and outputs as the output current and the first phase comparison output current, the second differential input stage is made of a differential pair of third and fourth transistors, the input signal and the second reference signal and comparison result output as the second inverted comparison output current and said second phase comparison output current, said shunt means, fifth grounded base cascaded to said first differential input stage of the 6, 7th and 8th, 9th, 1st
, Twelfth, thirteenth and fourteenth grounded bases cascaded to the transistor 0 and the second differential input stage.
Fifteenth and sixteenth transistors shunt the first inverted comparison output current and the first in-phase comparison output current at a ratio of 1: 1: 2, respectively. said second phase comparison output current of 1: 1: 2 above were diverted to the ratio, the interpolated output stage, the sum of the first and second inverted comparison output current quarter at a rate of 1 synthesis inverted output current with comparing the first and second phase comparison output current collectors generated by the common connection, which is the composite inverted output current and said shunt of said sixth and eleventh transistors, The first and second in-phase comparison output currents are
The synthesis phase output obtained by summing in 1 ratio of quarter generated by commonly connecting the collector of the transistor of the ninth and fourteenth, the combined in-phase output currents and the shunt
Claims, characterized in that to obtain a comparison result of the input signal for the virtual reference signal present between said first and second reference signals by comparing the first and second inverted comparison output current which is Item 2. An analog digital conversion circuit according to item 1. 4. The interpolation output stage according to claim 1, wherein said interpolation output stage comprises:
And the first and second inverted comparison output currents divided at the predetermined ratio, the combined in-phase output current and the predetermined
The seventeenth and eighteenth , nineteenth , and nineteenth and twentieth and nineteenth and ninth transistors have the same emitter area between the output terminals through which the first and second in-phase comparison output currents respectively shunted and the shunting transistors flow. 2. The analog-to-digital converter according to claim 1, wherein the twentieth, twenty-first, and twenty- second transistors are connected in cascade.