JP3219212B2 - Analog digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIG. 13) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1, 8 to 11) Action (FIG. 8) Example (FIGS. 1 to 12) (1) Overall Configuration of Embodiment (FIGS. 1 to 10) (1-1) Configuration of A / D Converter Circuit 50 (FIGS. 1 to 3) (1-2) Shunting of Current in Lower Comparators CD51 to CD58 Interpolation Principle Used (FIGS. 4 to 8) (1-3) Configuration of Lower Comparators CD51 to CD58 (FIG. 9) (2) Operation of Embodiment (FIG. 10) (3) Effect of Embodiment (4) Others Example (FIGS. 11 and 12) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter and, more particularly, to an analog-to-digital converter suitable for use in a serial-parallel analog-to-digital converter.

[0003]

2. Description of the Related Art Conventionally, in various fields such as audio equipment and measuring instruments, an analog digital conversion circuit (hereinafter referred to as an AD conversion circuit) for digitally processing various analog signals such as audio signals to be recorded or reproduced. That)
Is generally converted to digital data by using, and various conversion methods are considered according to the application field, required accuracy, speed, and the like.

In particular, when high-speed operation and high accuracy are required, a parallel (flash) type A / D conversion circuit and a series-parallel (subranging) type A / D conversion circuit are generally used. In particular, the serial-parallel A / D converter has an advantage that the number of elements can be greatly reduced as compared with the parallel A / D converter.

[0005] This serial-parallel A / D conversion circuit uses an input signal V
IN is converted into digital data in two stages of upper bits and lower bits, and this type of serial-parallel A-
When a video signal is to be processed also in the D conversion circuit, a two-step parallel A / D conversion circuit 40 is mainly used (FIG. 13).

The A / D conversion circuit 40 has a reference voltage generation circuit 4 composed of 16 reference resistors R connected in series.
1, the reference voltages VU1 and VU corresponding to the upper two bits.
U2, VU3, and the three sets of reference voltages VU1, VU
U2, VU3 and the input signal VIN are connected to the upper comparator CU.
1, CU2 and CU3 compare. Then, by supplying the comparison output to the upper encoder 42, the most significant bit D1 is generated.

The upper encoder 42 switches the switch group SW based on the comparison output of the upper comparators CU1, CU2 and CU3, thereby subdividing the voltage band to which the upper two bits belong, and the upper and lower sides of the voltage band. A total of eight reference voltages VD1, VD2,..., VD8, which are the reference voltages for redundancy correction prepared in FIG.

The lower comparators CD1, CD2,
.., And these eight reference voltages VD1, VD in CD8
D2,..., VD8 are compared with the input signal VIN, and the comparison output is supplied to the lower encoder 43 to generate the remaining lower three bits D2, D3, D4.

[0009]

However, the resolution is 10
When the bit becomes as small as ~ 12 bits, the voltage of the least significant digit (1 LSB) required for the A / D conversion circuit 40 becomes very small at about 1 [mV], and as the number of bits increases, the lower comparators CD1, CD2,. .., The effect of the base-emitter voltage ΔVBE of the transistor constituting the differential pair of CD8 cannot be ignored.

Therefore, by comparing a plurality of comparison outputs generated in the comparator and comparing them, a comparison output between the input signal VIN and a potential located in the middle of the actually applied reference potential is obtained by interpolation. An interpolation method for reducing the number of comparators required for signal comparison by processing has been studied.

As one of such interpolation methods, a load resistance of a differential amplifier circuit constituting a comparator is formed as a resistor string of resistors having a predetermined resistance ratio, and an output voltage obtained as a difference voltage between connection taps of each resistor. Have been proposed to obtain a comparison output between an input signal and an intermediate potential that equally divides a reference potential by combining.

In this case, however, an extra differential amplifying stage for interpolation is required one by one, and a plurality of differential outputs with different resistance values are compared. As a result, it is not suitable for use in a lower comparator constituted by a serial-parallel A / D conversion circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a comparison output between an input signal and a plurality of virtual reference potentials which divide the reference potential with a significantly smaller number of elements than in the prior art. It is intended to propose an A / D conversion circuit having a comparison circuit which can perform the following.

[0014]

SUMMARY OF THE INVENTION In order to solve this problem, according to the present invention, a lower-order comparison of a serial-parallel type analog-to-digital converter 50 which divides an analog signal into digital data and executes the operation in a plurality of stages. Section, input a first reference signal VREF1 and an input signal VIN,
A first inverted comparison output current (IB / 2 + IB) and a first in-phase comparison output current (IA) for the first reference signal VREF1
/ 2 + IA), a second reference signal VREF2 and an input signal VIN, and a second inversion comparison output current (ID / 2 +) for the second reference signal VREF2.
ID) and the second common-mode comparison output current (IC / 2 + IC)
, A first inverted comparison output current (IB / 2 + IB), and a first in-phase comparison output current (IA).
/ 2 + IA) and the second inverted comparison output current (ID / 2 + IA).
ID), and shunt means Q12, Q1 for shunting the second in-phase comparison output current (IC / 2 + IC) at a predetermined ratio, respectively.
3, Q13N, Q12N and Q22, Q23, Q23
N, Q22N and the first and second inverted comparison output currents IB and ID divided at the predetermined ratio are added to generate a combined inverted output current II, or the first divided output current II divided at a predetermined ratio is generated. And the second common-mode comparison output currents IA and IC to obtain a composite common-mode output current IE
And comparing the combined inverted output current II with the first and second in-phase comparison output currents IA and IC shunted at a predetermined ratio opposite to the combined inverted output current II, or By comparing the output current IE with the first and second inversion comparison output currents IB and ID which are shunted at a predetermined ratio of opposite phase to the combined in-phase output current IE, the first reference signals VREF1 and VREF1 are compared. And an interpolation output stage for obtaining a comparison result of the input signal VIN with a virtual reference signal existing between the second reference signals VREF2.

According to the present invention, in order to solve the above-mentioned problem, the interpolation output stage is provided with the first divided output at a predetermined ratio.
And the second inverted comparison output currents IB and ID or the first and second in-phase comparison output currents IA and IC shunted at a predetermined ratio and the first inverted comparison output current IB and shunted at a predetermined ratio The second inverted comparison output current ID thus added is added at a ratio of (N / 2) -k: k (where k = 0, 1,... N / 2), and the combined inverted output current II or the combined in-phase output current IE, and compares the combined inverted output current II with the first and second in-phase comparison output currents IA and IC divided at a predetermined ratio, or the combined in-phase output current I
By comparing E with the first and second inverted comparison output currents IB and ID divided at a predetermined ratio, N existing between the first reference signal VREF1 and the second reference signal VREF2 is obtained.
A comparison result of the input signal VIN with respect to one virtual reference signal is obtained.

Further, in order to solve such a problem, in the present invention, the first differential input stage comprises a differential pair of first and second transistors Q10 and Q11, and the input signal V
The comparison result between IN and the first reference signal VREF1 is output as a first inverted comparison output current (IB / 2 + IB) and a first in-phase comparison output current (IA / 2 + IA), and the second differential input stage It comprises a differential pair of third and fourth transistors Q20 and Q21, and compares the result of comparison between the input signal VIN and the second reference signal VREF2 with a second inverted comparison output current (ID / 2 + I
D) and the second common-mode comparison output current (IC / 2 + IC), and the shunting means includes fifth, sixth, seventh, and eighth grounded bases cascaded to the first differential input stage. The transistors Q12, Q13 and Q13N, Q12N and the second
Ninth and first grounded bases cascaded to the differential input stage of
0 and eleventh and twelfth transistors Q22, Q23 and Q23N, Q22N. The first inversion comparison output current (IB / 2 + IB) and the first in-phase comparison output current (I
A / 2 + IA) in a ratio of 1: 2, and a second inversion comparison output current (ID / 2 + ID) and a second in-phase comparison output current (IC / 2 + IC) in a ratio of 1: 2. And the interpolating output stage comprises a shunted first
And the second inverted comparison output currents IB and ID are combined to generate a combined inverted output current II by connecting the collectors of the seventh and eleventh transistors Q13N and Q23N in common, and shunt the combined inverted output current II. The first and second common-mode comparison output currents IA and IC are compared with each other, or the divided first and second common-mode comparison output currents I and IC are divided.
The combined common-mode output current IE obtained by adding A and IC
And the first and second inverted comparison output currents IB generated by connecting the collectors of the ninth transistors Q12 and Q22 in common with the combined in-phase output current IE.
And ID with the first reference signal VRE.
A comparison result of the input signal VIN with respect to a virtual reference signal existing between F1 and the second reference signal VREF2 is obtained.

Furthermore, in order to solve this problem, in the present invention, the first differential input stage comprises a differential pair of first and second transistors Q10 and Q11, and the input signal V
The comparison result between IN and the first reference signal VREF1 is output as a first inverted comparison output current (IB / 2 + IB) and a first in-phase comparison output current (IA / 2 + IA), and the second differential input stage It comprises a differential pair of third and fourth transistors Q20 and Q21, and compares the result of comparison between the input signal VIN and the second reference signal VREF2 with a second inverted comparison output current (ID / 2 + I
D) and the second common-mode comparison output current (IC / 2 + IC), and the shunting means includes fifth, sixth, seventh, and eighth grounded bases cascaded to the first differential input stage. The transistors Q12, Q13 and Q13N, Q12N and the second
Ninth and first grounded bases cascaded to the differential input stage of
0 and eleventh and twelfth transistors Q22, Q23 and Q23N, Q22N. The first inversion comparison output current (IB / 2 + IB) and the first in-phase comparison output current (I
A / 2 + IA) in a ratio of 1: 2, and a second inversion comparison output current (ID / 2 + ID) and a second in-phase comparison output current (IC / 2 + IC) in a ratio of 1: 2. And the interpolating output stage comprises a shunted first
And the second inverted comparison output currents IB and ID are combined to generate a combined inverted output current II by connecting the collectors of the seventh and eleventh transistors Q13N and Q23N in common, and the divided first and second currents IB and ID are divided. And a second common-mode output current IE obtained by adding the common-mode comparison output currents IA and IC of FIG.
2 and the combined inversion comparison output current II or the combined in-phase comparison output current IE
By comparing either one of the divided first and second in-phase comparison output currents IA and IC or the divided first and second inverted comparison output currents IB and ID.
A comparison result of the input signal VIN with a virtual reference signal existing between the first reference signal VREF1 and the second reference signal VREF2 is obtained.

[0018]

The combined inverted output current II is generated by adding the first and second inverted comparison output currents IB and ID divided at a predetermined ratio at the interpolation output stage of the lower comparison section of the analog digital conversion circuit 50. Or the first and second common-mode comparison output currents IA divided at a predetermined rate.
And the IC are added to generate a combined in-phase comparison output current IE, and the combined inversion output current II and the first and second in-phase comparisons divided by a predetermined ratio of opposite phase to the combined inversion output current II The output currents IA and IC are compared, or the combined in-phase comparison output current IE and the first and second inverted comparison output currents IB and shunted at a predetermined ratio opposite to the combined in-phase comparison output current IE. Compare with ID. As a result, the number of transistors required to configure the comparison circuit can be significantly reduced as compared with the related art.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Overall Configuration of Embodiment (1-1) Configuration of A / D Converter Circuit 50 In FIG. 1, reference numeral 50 denotes a so-called two-step parallel type serial / parallel A / D converter circuit as a whole. As current interpolation type lower comparators CD51 to CD5
By using 8, the number of differential pairs constituting the first stage circuit of the lower comparator is reduced, and an A / D conversion circuit having a resolution of 6 bits without reducing the voltage required for the least significant digit (1 LSB) is constructed. It has been made to be.

Here, the AD conversion circuit 50 converts the reference voltages VRT and VRB generated by the reference voltage generation circuit 51 into four reference potential sections (VRB to VU1, VU1 to VU2,
VU2 to VU3, VU3 to VRT)
U1, VU2, and VU3 are compared with the input signal VIN in the upper comparators CU51 to CU53, and the comparison result is given to the upper encoder 52 (FIG. 2).

In the case of this embodiment, the upper encoder 52 outputs code values that can be selected as the most significant bit D1 by the redundancy correction function to the selection output unit 53 as three sets of line signals SA, SB, and SC, and switches. SW1
SW4 and lower reference potential selection signals X1 to X5 for switching SD1 to SD16 are output to the reference voltage generation circuit 51;
The reference potentials applied to the lower comparators CD51 to CD58 are switched.

At this time, the lower comparators CD51 to CD51
58 (FIG. 3) indicates the input signal V when encoding the upper bits.
Switches SW1 to SW4 are used to divide a reference potential section detected as belonging to IN and a reference potential section for dividing a section for redundancy interpolation into eight.
SW4 or the first stage differential pair of the lower comparator and the switch are used for inputting via switching blocks SD1 to SD16.

Here, the lower comparators CD51 to CD5
8 compares each reference potential with the input signal VIN using a first-stage differential pair, and uses a plurality of common-base transistors cascode-connected to this differential pair to generate a plurality of shunt collector currents having different current ratios. And the output voltages generated by the combination of the divided shunt collector currents are compared.

The lower comparators CD51 to CD5
Reference numeral 8 denotes to the lower encoder 54 four sets of comparison outputs corresponding to the comparison output of the input signal VIN with respect to the virtual reference potential for dividing the adjacent reference potential into four.

The lower encoder 54 receives these 32 (= 4) input from the respective lower comparators CD51 to CD58.
× 8) Lower 5 bits D2 to D6 based on comparison output of set
Is encoded and output.

The lower encoder 54 generates selection signals XA, XB, XC for correcting the code value of the most significant bit D1 by the redundancy correction function, outputs the selection signals to the selection output section 53, and outputs the line signals SA, SB, SC. Is output as the most significant bit D1.

Thus, the A / D conversion circuit 50 operates as a 6-bit resolution A / D conversion circuit having a small linearity error.

(1-2) Lower Comparators CD51-CD
Interpolation Principle Using Current Dividing in D58 In the case of this embodiment, a comparison output between a plurality of virtual reference potentials between two reference potentials and an input signal is determined by a comparator to which an input signal VIN and a reference potential VREF1 are input. Input signal V
A composite current obtained by adding two sets of in-phase outputs of a comparator to which IN and the reference potential VREF2 (= VREF1 + ΔV) are input at a predetermined ratio is compared with one of the two sets of negative-phase outputs. It is required by

The principle will be described with reference to two differential pairs 1 and 2 shown in FIG. Here, the differential pair 1 is a transistor Q
1 and Q2. The input signal VIN and the reference potential VREF1 are input to the base. Further, the differential pair 2 is constituted by transistors Q3 and Q4, and the input signal VIN and the reference potential VREF2 are inputted to the base.

At this time, the transistors Q1, Q2 and Q
3, if the collector currents flowing through Q4 are IA, IB, IC, and ID, respectively, as shown in FIG. 5, the current values of the collector currents IA, IB, IC, and ID are inverted around the reference potentials VREF1 and VREF2, respectively. .

Accordingly, the output signals VA and VB appearing at the connection midpoint between the transistors Q1 and Q2 and the load resistors R1 and R2 through which the collector currents IA and IB flow are compared by a comparator, whereby the input signal V for the reference potential VREF1 is obtained.
The comparison output of IN can be obtained.

The output voltages VC and VD appearing at the connection point between the transistors Q3 and Q4 and the load resistors R3 and R4, through which the collector currents IC and ID flow, are compared by a comparator, so that the input signal VIN with respect to the reference potential VREF2 is obtained.
Can be obtained.

Similarly, the collector currents IA and ID are inverted at an intermediate potential V2 (= VREF1 + .DELTA.V / 2) between the reference potential VREF1 and the reference potential VREF2 (= VREF1 + .DELTA.V). The output voltages VA and VD or the output voltages VB and VC are compared using an intermediate potential V2 (= VREF1 + ΔV / 2) as a boundary, so that the virtual reference potential V2 (= VREF1 + ΔV)
/ 2) can be obtained as a comparison output of the input signal VIN.

Using this relationship, consider obtaining a comparison output of the input signal VIN with respect to a virtual reference potential that divides the reference potential VREF1 and the reference potential VREF2 (= VREF1 + ΔV) into four.
Here, three currents of the collector currents IA, IB and IC are used.

At this time, since the collector current linearly increases and decreases between the difference voltage and the collector current in a range where the difference voltage is small, the collector currents IA and IC which are the in-phase outputs of the differential pairs 1 and 2 are equal to each other. As shown in FIG. 6, the collector currents IB, which are substantially in parallel with each other and output in opposite phases of the differential pair 1, intersect in a range that can be regarded as a substantially straight line.

Therefore, if a combined collector current IE (ie, IA / 2 + IC / 2) can be generated by adding the collector currents IA and IC at a ratio of 1/2, respectively, the combined collector current IE is equal to both collectors. Since the collector current IB and the combined collector current IE are equal to the currents IA and IC and are expressed as a straight line parallel to both collector currents IA and IC, the virtual reference potential V1 (= VREF1 + ΔV / 4) which divides the reference potentials VREF1 and VREF2 into four. ).

Accordingly, when the output voltage VB generated by the collector current IB is compared with the output voltage VE generated by the combined collector current IE, the virtual reference potential V1 (= VREF1 + ΔV)
/ 4) can be obtained as a comparison output of the input signal VIN.

Since the same relationship holds for the three currents of the collector currents IC, IB and ID, the combined collector current IF (that is, IB) is obtained by adding the collector currents IB and ID by a half. / 2 + I
D / 2) and comparing the output voltage VC generated by the collector current IC with the output voltage VF generated by the combined collector current IF, the virtual reference potential V3 (= VREF1 + 3 ·
ΔV / 4) can be obtained as a comparison output of the input signal VIN (FIG. 7).

The comparison output of the input signal VIN with respect to the virtual reference potential V3 obtained by comparing the combined collector current IF and the collector current IC is the combined collector current IE used for comparing the input signal VIN with the virtual reference potential V1. Can also be obtained by using

That is, by comparing the output voltage generated by the combined collector current IE with the output voltage generated by the collector current ID, a comparison output of the input signal VIN with respect to the virtual reference potential V3 can be obtained as shown in FIG.

Therefore, in this embodiment, the in-phase output IA, IC (or IB,
ID) at a ratio of 1/2
E (or IF) and this combined collector current IE (or I
F) Collector currents IB and ID that are in anti-phase relation to
(IA, IC) are compared with each other, and the comparison output of the input signal VIN with respect to the virtual reference potentials V1, V2, V3 which divide the reference potentials VREF1 and VREF2 into four equal parts is interpolated.

(1-3) Lower Comparators CD51 to CD-C
Configuration of D58 In FIG. 9, reference numeral 10 denotes a lower-order comparator section which uses this principle as a whole, and includes three sets of adjacent reference potentials VRE.
After shunting a collector current, which is a comparison output between F1, VREF2, and VREF3, and the input signal VIN at a current ratio of 1: 2, and adding them in combination, the reference potentials VREF1 and VREF2 and VREF2 and VREF3 are divided into four equal parts. A comparison output of the input signal VIN with respect to the reference potential is obtained.

In the case of this embodiment, the differential input stages 11, 12 and 13 constituting the first stage circuit of the lower comparator have the same configuration, and one of the transistors Q10 and Q20 constituting the differential pair. And the input signal V to Q30
IN, and the other transistors Q11, Q21, Q3
1 is supplied with reference potentials VREF1, VREF2 and VREF3 so that a collector current corresponding to the signal level of the input signal VIN with respect to each reference potential is drawn.

Here, the transistors (Q1
0, Q11), (Q20, Q21) and (Q30, Q3
In the collector of (1), a common base shunt transistor (Q12, Q13, Q1) having an emitter area ratio of 1: 2.
3N, Q12N), (Q22, Q23, Q23N, Q2
2N) and (Q32, Q33, Q33N, Q32N) are cascode-connected, respectively, so as to shunt the comparative collector current according to the emitter area ratio.

In each differential input stage, the collectors of shunt transistors (Q12, Q22) and (Q23N, Q33N) of adjacent differential input stages for shunting the collector current to one third are commonly connected. It is made as
An output voltage is obtained by combining two sets of shunt collector currents having an in-phase relationship with each other.

As a result, the transistors Q13 and Q23
Is a combined collector current IE obtained by combining the shunt collector currents IA and IC at a ratio of 1/2, respectively, to the load resistor R12 connected to the common collector of the transistors Q12 and Q22. (= IA / 2 + IC / 2) flows.

Similarly, transistors Q22N and Q3
Assuming that the shunt collector currents flowing through 2N are ID and IH, the shunt collector current ID is applied to the load resistor R23N connected to the common collector of the transistors Q23N and Q33N.
And IH at a ratio of 1/2 each, a combined collector current II (= ID / 2 + IH / 2) flows.

The reason is that each shunt transistor (Q12, Q12)
13, Q12N), (Q22, Q23, Q22N) ...
Have load resistors (R12, R13,
R12N), (R22, R23, R22N)... Are connected to the respective load resistors, and the outputs corresponding to the current values of the divided collector current and the combined collector current divided according to the ratio of the emitter area of the transistor. A voltage is obtained.

In this embodiment, the reference potentials VREF1 and VREF1
The comparison output with respect to the virtual reference potential which divides the potential between REF2 into four is obtained by comparing the output voltage of each load resistor. That is, the comparison output of the input signal VIN with respect to the reference potentials VREF1 and VREF2 is obtained by comparing the output voltages of the load resistors R12 and R12N, respectively,
3 and the output voltage of the load resistor R23N.

The two reference potentials VREF1 and VREF2 are
The comparison output of the input signal VIN with respect to the divided virtual reference potential V2 (= VREF1 + ΔV / 2) is represented by load resistances R12N and R12N.
23 can be obtained by comparing the output voltages.

The comparison output of the input signal VIN with respect to the virtual reference potential V1 (= VREF1 + ΔV / 4) which divides the reference potential VREF1 and the intermediate potential V2 into two (that is, divides between the reference potentials VREF1 and VREF2 into four) is the combined collector current This can be obtained by comparing the output voltage of the load resistor R12 through which the IE flows and the output voltage of the load resistor R12N through which the shunt collector current IB flows.

Similarly, the reference potential VREF2 and the intermediate potential V2 are set to 2
The comparison output of the input signal VIN with respect to the virtual reference potential V3 (= VREF1 + 3 ・ ΔV / 4) that is divided (that is, the reference potential VREF1 and VREF2 are divided into four) is the combined collector current I
It can be obtained by comparing the output voltage of the load resistor R12 through which E flows and the output voltage of the load resistor R22N through which the shunt collector current ID flows.

As described above, the distance between the reference potentials VREF1 and VREF2 is 4
Input signal V for virtual reference potentials V1 and V3 to be divided
The comparison output of IN can be obtained by comparing the combined collector current IE with the same phase with respect to the input signal VIN and the collector currents IB and ID with the opposite phase with respect to this.

On the other hand, the comparison output of the input signal VIN with respect to the virtual reference potentials V11 and V13, which divides the reference potentials VREF2 and VREF3 adjacent to the reference potentials VREF1 and VREF2 into four, is synthesized in the opposite phase to the input signal VIN. Collector current II
And the collector currents IC and IG which are in opposite phases to each other.

(2) Operation of Embodiment In the above configuration, the AD converter circuit 50 inputs the input signal VIN to the upper comparators CU51 to CU53, compares the input signal VIN with the reference voltages VU1 to VU3, and outputs a line corresponding to the comparison output. While supplying the signals SA to SC to the selection output unit 53,
At this time, the reference potential section to which the input signal VIN belongs and the reference potential for dividing the section for redundancy correction into eight are switched by the lower reference potential selection signals X1 to X5, and the lower comparator C
D51 to CD58.

At this time, the eight lower-order comparators CD51
To CD58, the lower comparators CD51 and CD53
And reference potentials VREF1, VREF2 to the differential pair at the first stage of CD55.
And VREF3, the input signal VIN is sequentially changed from the reference potential VREF1 to the adjacent reference potentials VREF2 and VREF3.
The interpolation operation of the four-division interpolation type comparison circuit when increasing the number will be described.

First, when the input signal VIN exceeds the reference potential VREF1 (intersection P1 in FIG. 8), the shunt collector current I
The voltage value of the output voltage of the load resistor R13 through which A flows and the load voltage of the load resistor R12N through which the shunt collector current IB flows are inverted, and at this time, the comparison output of the voltage value is newly inverted.

Further, when the voltage value of the input signal VIN gradually increases and the voltage value of the input signal VIN exceeds the virtual reference potential V1 (intersection P3 in FIG. 8), this time is combined with the load resistance R12N through which the shunt collector current IB flows. Collector current I
The output voltage of the load resistor R12 through which E (= IA / 2 + IB / 2) flows is inverted, and the comparison output of this voltage value is newly inverted.

Similarly, when the voltage value of the input signal VIN exceeds the virtual reference potentials V2 and V3 (intersection points P4 and P6 in FIG. 8), the shunt collector currents IB and IC
, The output voltages of the load resistors R12N and R23 reverse, and the shunt collector current ID and the combined collector current I
Load resistance R22N through which E (= IA / 2 + IC / 2) flows
And the output voltage of the load resistor R12 is inverted, and these comparison outputs are sequentially inverted.

As described above, the lower comparator section 10 provides the virtual reference potentials V1, V2, and V3 that divide the two in addition to the two reference potentials VREF1 and VREF2 actually given.
Can be obtained.

Subsequently, adjacent reference potentials VREF2 and VREF3
The load resistance R23 through which the shunt collector current IC flows and the load resistance R22 through which the shunt collector current ID flows
The voltage value of the input signal VIN exceeds the virtual reference potential VREF2 due to the inversion of the output voltage of N (the intersection P1 in FIG. 10).
1) can be detected and the load resistance R23N through which the combined collector current II flows and the load resistance R through which the shunt collector current IC flows
The fact that the input signal VIN has exceeded the virtual reference potential V11 due to the reversal of the output voltage at 23 (intersection P12 in FIG. 10) can be determined.

Similarly, the comparison between the output voltages of the load resistors R22N and R32 indicates that the input signal VIN has exceeded the virtual reference potential V12 (intersection P13 in FIG. 10), and the comparison between the output voltages of the load resistors R23N and R33. Thus, the fact that the input signal VIN has exceeded the virtual reference potential V13 (intersection P14 in FIG. 8) can be sequentially obtained.

As described above, of the shunt collector currents obtained by shunting each collector current flowing based on the comparison result between the reference potential adjacent to each other and the input signal VIN, the shunt collector currents having the same phase relationship are reduced by half. One of the combined collector currents IE or II of the combined collector currents
Is compared with the shunt collector currents IB, ID or IC, IG having an opposite phase relationship with respect to the combined collector current, so that the reference potentials VREF1 and VREF actually given are obtained.
2, it is possible to obtain a comparison output of the input signal VIN with respect to the virtual reference potentials V1, V2, V3 and V11, V12, V13 which respectively divide the VREF2 and VREF3 into four equal parts.

Other lower comparators CD53 and CD54
To CD58, the same comparison output is obtained. The lower encoder 54 has eight sets of lower comparators CD51 to CD58.
Four comparison outputs are input from D58.

As a result, the AD conversion circuit 50 includes a reference voltage generation circuit 51 having the same configuration as the conventional reference voltage generation circuit 41.
Can be used to obtain an A / D conversion output with 6-bit resolution.

(3) Effects of the Embodiment According to the above configuration, of the collector current flowing based on the result of comparison between the adjacent reference potentials VREF1, VREF2 or VREF2, VREF3 and the input signal VIN, the input signal VIN The combined collector current IE (= IA / 2 + I) is obtained by adding the two shunt collector currents IA, IC or ID, IH having the same-phase relationship or opposite-phase relationship at a ratio of 1/2.
C / 2) or II (= ID / 2 + IH / 2) and comparing each combined collector current with the shunt collector currents IB, ID or IC, IG which are in the opposite phase to the adjacent reference potential VREF1. , VREF2 or VREF2, VREF3, or virtual reference potential V1, V2, V3 or V1
The comparison output for 1, V12, and V13 can be obtained.

As a result, the AD conversion circuit 50 can obtain a large difference voltage between the reference potentials actually applied to the differential pair, and can reduce the influence of the base emitter voltage ΔVBE.
Also, the number of elements required to constitute one differential input stage may be four when transistors with different emitter area ratios are used, and six when transistors with the same emitter area are used. The number of transistors required in comparison (14 when transistors having different emitter area ratios are used, and 32 when the emitter areas are equal).
) Can be realized with a significantly smaller number of elements.

(4) Other Embodiments In the above-described embodiment, of the comparison output of the input signal VIN with respect to the reference potential VREF2, the collector current IC having the same phase as that of the input signal VIN is divided into half. The collector current (IC / 2) is supplied to the differential input stage 11 for obtaining a comparison output with respect to the lower reference potential VREF1, while the collector current ID having the opposite phase to the input signal VIN is halved. The current (ID / 2) is set to the higher reference potential V
Although the case of supplying the comparison output to REF3 to the differential input stage 13 has been described, the present invention is not limited to this.
As shown in FIG. 11 in which the same reference numerals are given to the corresponding parts, two sets of shunt collector currents (IC / 2 and ID / 2)
In either case, it may be combined with the shunt collector current of the lower or upper differential input stage.

In this case, since two sets of combined collector currents IE and IF are simultaneously generated as shown in FIG. 7, virtual reference potentials V1, V2, and V3 are generated using only one of the combined collector currents IE and IF. Input signal VIN for
What is necessary is just to obtain the comparison output of.

In the above embodiment, the case where the load resistors R12, R13, R12N... Are directly connected to the collectors of the respective shunt transistors Q12, Q13, 13N, Q12N. Not limited to this, the transistors Q12, Q13, 13N for the respective shunts,
Q12N ... and load resistors R12, R13, R12N ...
, Transistors having the same emitter area and having a common base may be connected in cascade.

In this way, the parasitic capacitance at the output terminal becomes apparently one, which can be reduced to half of the parasitic capacitance in the above-described embodiment. Thus, the lower comparator section 20 can be operated at a higher speed.

Further, in the above-described embodiment, transistors Q10 and Q11 forming a differential pair for comparing reference potentials VREF1... With input signal VIN and grounded base transistor Q1 which shunts a collector current as a comparison output
2, Q13, Q13N, Q12N... Have been described separately, but the present invention is not limited to this, and the input signal VIN is input in parallel to the bases of the transistors Q12 and Q13 among the common base transistors. The reference potential V is applied to the bases of the other transistors Q13N and Q12N.
REF1 may be supplied, and the emitters of these four transistors may be connected to a common constant current source so that the comparison transistor and the shunt transistor are shared.

In this case, the number of elements required to configure the lower comparator section can be realized with a further smaller number of elements, and the circuit area required for the comparator can be reduced.

Further, in the above embodiment, two adjacent
Four reference potentials VREF1 and VREF2 (= VREF1 + ΔV)
Although the case where the comparison output of the input signal VIN with respect to the divided virtual reference potentials V1, V2, and V3 is obtained by interpolation has been described, the present invention is not limited to this, and generally N (N is a natural number)
The present invention can be widely applied to a case where a comparison output of the input signal VIN with respect to the virtual reference potential to be divided is obtained by interpolation.

In this case, two reference potentials VREF1 and VREF2
Dividing the difference voltage ΔV into N means that the difference between the intermediate potential ΔV / 2 of the difference voltage and the reference potential VREF1 or VREF2 is divided into two by N. For example, in the case of dividing into eight, it means dividing the difference voltage ΔV / 2 into four as shown in FIG.

Therefore, the following equation

(Equation 1) Shunt collector current IA and shunt collector current I based on
A composite collector current which internally divides C into (N / 2) -k: k (k = 0, 1,... N / 2) is generated, and each of these composite collector currents is compared with the shunt collector current IB. The interval between the reference potential VREF1 and the intermediate potential (VREF1 + ΔV / 2) can be divided into N by two.

Similarly, the shunt collector current IA and the shunt collector current IC are expressed as (N / 2) -k: k (k = 0, 1,... N /
By generating a combined collector current internally divided into 2) and comparing each combined collector current with the shunt collector current ID, it is possible to divide the intermediate potential (VREF1 + ΔV / 2) and the reference potential VREF2 into N by two. it can.

Further, in the above-described embodiment, a case where a plurality of transistors having different emitter area ratios are cascode-connected to a pair of transistors Q10 and Q11, Q20 and Q21... As described above, the present invention is not limited to this, and an emitter resistor may be added to the emitter of the transistor used for the shunt in order to reduce the variation in the current ratio.

Further, in the above embodiment, the transistors Q12 and Q13 (Q13
(N, Q12N) is set to 1: 2, but the present invention is not limited to this, and may be set to another ratio.

Further, in the above-described embodiment, the case where the present invention is used in the comparison unit of the two-step parallel type A / D conversion circuit has been described. Applicable.

[0082]

As described above, according to the present invention, the first and second inverted comparison output currents divided at a predetermined ratio are added in the interpolation output stage of the lower comparison section of the analog digital conversion circuit. To generate a combined in-phase output current, or add the first and second in-phase comparison output currents shunted at a predetermined ratio to generate a combined in-phase comparison output current. A comparison is made between the first and second in-phase comparison output currents that are shunted at a predetermined ratio opposite to the current, or the combined in-phase comparison output current and a predetermined The first and second inverted comparison output currents divided by the ratio are compared. As a result, the number of transistors required to form the comparison circuit can be significantly reduced as compared with the related art, and thus the circuit area of the analog-to-digital conversion circuit can be reduced.

[Brief description of the drawings]

FIG. 1 shows an analog digital conversion circuit 50 according to the present invention.
FIG. 4 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a schematic connection diagram for explaining the reference voltage generation circuit.

FIG. 3 is a schematic connection diagram for explaining the lower comparator.

FIG. 4 is a connection diagram for explaining the principle of interpolation by shunting of a collector current in a lower comparator.

FIG. 5 is a characteristic curve diagram showing a relationship between a collector current flowing through a differential pair to which different reference potentials are applied and an input signal.

FIG. 6 is a characteristic curve diagram showing a relationship between a combined collector current combined at a predetermined ratio and a collector current flowing with respect to a reference potential.

FIG. 7 is a characteristic curve diagram for explaining a virtual reference potential interpolation process using a combined collector current.

FIG. 8 is a characteristic curve diagram for explaining a virtual reference potential interpolation process using a combined collector current.

FIG. 9 is a connection diagram illustrating a configuration of a lower comparator.

FIG. 10 is a characteristic curve diagram for explaining the operation.

FIG. 11 is a connection diagram for explaining another embodiment.

FIG. 12 is a characteristic curve diagram for explaining N-division interpolation.

FIG. 13 is a schematic connection diagram for describing a conventional serial-parallel A / D converter.

[Explanation of symbols]

50: AD conversion circuit, 52: Upper encoder, 5
3 ... Selection output unit, 54 ... Lower encoder, CU, C
D: comparison unit, VIN: analog signal, VREF1, VREF
2, VREF3 ... reference potential, V1, V2, V3 ... virtual reference potential.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (4)

(57) [Claims] 1. A serial-parallel type analog-to-digital conversion circuit to perform in a plurality of stages of conversion of the above analog signal into digital data, the lower comparator unit used for the conversion operation, a first reference signal inputs the input signal, first inverting comparator output current and a first differential input stage for outputting a first phase comparison output current, the second reference signal and the input signal to the first reference signal And a second differential input stage for outputting a second inversion comparison output current and a second in-phase comparison output current with respect to the second reference signal ; the first inversion comparison output current; 1 common-mode comparison output
Current and the second inverted comparison output current, the second in-phase
A shunt means for the comparison output current shunted respectively at a predetermined ratio to generate a combined inverted output current by causing Awa and legs of the first and second inverted comparison output current diverted by the predetermined ratio, or the predetermined the first and second phase comparison output current diverted at a rate to produce a synthesized phase output current by causing Awa and legs, the synthetic inverted output current and the synthesized reverse the output currents of opposite phase of the predetermined comparing the diverted <br/> first and second phase comparison output current at a rate, or diverted by the predetermined ratio of the opposite phase to the synthesis phase output current and the composite common mode output current by comparing the first and second inverted comparison output current, the first reference signal
Analog-to-digital converter according to item and characterized by comprising an interpolation output stage to obtain a comparison result of the input signal for the virtual reference signal present between said second reference signal. 2. The method according to claim 1, wherein the interpolation output stage shunts at the predetermined ratio.
It has been the first and second inverted comparison output current or the predetermined
The first and second common-mode comparison output currents divided by the ratio
(N / 2) -k: k [where k = 0,1, ...... N / 2] are summed at a rate of generating the synthetic inverted output current or the synthesis phase output current, and the combined inverted output current Above place
First and second common-mode comparison output currents shunted at a fixed rate
Comparing the door, or the combined phase output current and the predetermined split
By comparing the first and second inverted comparison output current that is diverted in case, the relative said first reference signal and the N-1 virtual reference signal present between said second reference signal 2. The analog-to-digital converter according to claim 1, wherein a comparison result of the input signals is obtained. Wherein said first differential input stage is made of a differential pair of first and second transistors, inverting comparison result of the comparison the first and the input signal and the first reference signal and outputs as the output current and the first phase comparison output current, the second differential input stage is made of a differential pair of third and fourth transistors, the input signal and the second reference signal and comparison result output as the second inverted comparison output current and said second phase comparison output current, said shunt means, fifth grounded base cascaded to said first differential input stage of the A common base cascaded to the sixth and seventh and eighth transistors and the second differential input stage
And the ninth, tenth, eleventh, and twelfth transistors. The first inversion comparison output current and the first in-phase comparison output current are respectively shunted at a ratio of 1: 2, and the second inverted comparison output current and the second phase comparison output current of 1: 2 of branched into percentage, the interpolated output stage was Awa and legs of the first and second inverted comparison output current which is the diverted above synthesis inverted output current generated by commonly connecting the collector of the transistor of the seventh and 11th, the synthetic inverted output current and the component
Comparing the first and second phase comparison output current flows,
Or the first and second phase comparison output current which is the diverted
The was allowed Awa and feet above synthesis phase output currents above 5 and 9
The collector of the transistor produced by commonly connecting, the combined in-phase output current by comparing the first and second inverted comparison output current is above diverted, the first reference signal and the second 2. The analog-to-digital converter according to claim 1, wherein a comparison result of the input signal with a virtual reference signal existing between the reference signals is obtained. Wherein said first differential input stage is made of a differential pair of first and second transistors, inverting comparison result of the comparison the first and the input signal and the first reference signal and outputs as the output current and the first phase comparison output current, the second differential input stage is made of a differential pair of third and fourth transistors, the input signal and the second reference signal and comparison result output as the second inverted comparison output current and said second phase comparison output current, said shunt means, fifth grounded base cascaded to said first differential input stage of the A common base cascaded to the sixth and seventh and eighth transistors and the second differential input stage
And the ninth, tenth, eleventh, and twelfth transistors. The first inversion comparison output current and the first in-phase comparison output current are respectively shunted at a ratio of 1: 2, and the second inverted comparison output current and the second phase comparison output current of 1: 2 of branched into percentage, the interpolated output stage was Awa and legs of the first and second inverted comparison output current which is the diverted above synthesis inverted output current so as to generate by commonly connecting the collector of the transistor of the seventh and 11th, the first and the synthetic phase output currents of the second phase comparison output current allowed Awa with feet which are the diverted The shunt current is generated by connecting the collectors of the fifth and ninth transistors in common to one of the combined inversion output current and the combined common mode output current.
It flowed first and second phase comparison output current or the amount corresponding to the
By comparing the first and second inverted comparison output currents, to obtain a comparison result of the input signal for the virtual reference signal present between said first reference signal and the second reference signal 2. The analog digital conversion circuit according to claim 1, wherein: