JPH06204876A - Analog/digital converting circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements by setting up the value of bias voltage impressed to one end of a resistor array for generating reference voltage in accordance with an input analog signal and changing the voltage range of plural reference voltage levels to be impressed to plural comparing means. CONSTITUTION:This analog/digital(A/D) converting circuit is provided with a control means 11 for comparing a threshold voltage VTH with an input analog signal VIN and setting up the bias voltage of a level shifting means VCENT, SW1 based upon the compared result S1 with the threshold voltage VTH and correcting means 12, 13 for correcting the compared results of plural comparing means C1 to C127 based upon the bias voltage set up by the means 11 and outputting a digital signal corresponding to the signal VIN. The value of bias voltage impressed to one end 126 of a resistor array R for generating reference voltage is set up in accordance with the signal VIN and the voltage range VR1 to VR127 of plural reference voltage levels impressed to the comparing means C1 to C127 are changed to another voltage range VR129 to VR255.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 6 and 7) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 2) Action (FIGS. 3 to 5) Example (FIGS. 1 to 5) (1) Principle of full-scale expansion by resistance division (FIG. 1) (2) Overall configuration of the embodiment (FIG. 2) (3) Operation and effect of the embodiment (FIGS. 3 to 5) (4) Other embodiments The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog digital conversion circuit, and is particularly suitable for application to a parallel (flash) type analog digital conversion circuit.

[0003]

2. Description of the Related Art Conventionally, in various fields such as audio equipment and measuring instruments, an analog digital conversion circuit (hereinafter referred to as an AD conversion circuit) for digitally processing various analog signals such as audio signals to be recorded or reproduced. Say)
Is converted into a digital signal using. By the way, in the case of these A-D conversion circuits, various conversion systems have been proposed in accordance with the field of use and the required accuracy and speed, and particularly in the field where high-speed operation is required, a parallel type A-D conversion circuit is used. It is used.

Here, the parallel type A-D conversion circuit inputs the input signal VIN to the comparator in parallel, finds the boundary of the potential at which the logical value of the comparison output is inverted, and converts it into binary data. For example, a parallel type A-D conversion circuit 1 having an 8-bit resolution is configured as shown in FIG.

That is, the parallel AD conversion circuit 1 has 256
The reference resistors R1 to R256 are connected in series, and the reference voltages VRT and VRB are supplied to both ends thereof to generate 256 reference voltages at the reference resistors R1 to R256. Then, a comparator COM to which each of these reference voltages is given
Input the analog input signal VIN to P (C1 to C256),
The magnitude relationship with each reference voltage is compared (FIG. 7).

Thereafter, the A / D conversion circuit 1 compares the comparison outputs of the comparator circuits C1 to C256 with AND circuits AND1 to A.
The signal is supplied to the encoder 3 via the differentiating circuit 2 constituted by ND256, and the input signal VIN is converted into 8-bit digital data.

[0007]

However, the parallel type A-
Since the D conversion circuit is an A-D conversion circuit intended for high-speed operation, the number of comparators is extremely large. For example, if an 8-bit resolution A-D conversion circuit is configured by a parallel conversion system, it is about 10,000 circuit elements were required. Therefore, the chip area has to be increased.

For this reason, as for the A-D conversion circuit having a resolution of 8 bits or more, more A-D conversion circuits using other conversion methods (for example, serial-parallel type A-D conversion circuits) than the parallel type are adopted than the parallel type. Has been done. However, considering the improvement of the processing speed, it is desired to realize a parallel type A-D conversion circuit having a small chip area.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose an analog digital conversion circuit having a much higher resolution than the conventional one without increasing the chip area.

[0010]

In order to solve such a problem, according to the present invention, an input analog signal VIN is input in parallel to a plurality of comparing means C1 to C126 and a plurality of comparing means are provided to the comparing means. Reference voltage VR1 to VR
In an analog digital conversion circuit for converting the input analog signal VIN into a digital signal based on the result of comparison with 256, a plurality of resistance means R1 to R126 are connected in series, and a plurality of reference voltages VR1 to VR127 (or VR129 to V129).
R255) for generating and outputting each to the comparing means, and a plurality of reference voltages VR1 to VR127 (which are connected to one end of the resistor string R and are generated in the resistor string R by switching and controlling the bias voltage). Or VR129 to VR255)
Level shift means VCENT, SW for switching the voltage range of
1 and the control means 11 for comparing the threshold voltage VTH with the input analog signal VIN and setting the bias voltage of the level shift means VCENT, SW1 based on the comparison result S1 with the threshold voltage VTH. Correcting means 12 and 13 for correcting the comparison results of the plurality of comparing means C1 to C127 based on the bias voltage set by 11 and outputting a digital signal corresponding to the input analog signal VIN are provided.

Further, in the present invention, the input analog signal VIN is inputted in parallel to the plurality of comparing means C1 to C126, and based on the result of comparison with the plurality of reference voltages VR1 to VR256 respectively given to the comparing means. In an analog digital conversion circuit for converting an input analog signal VIN into a digital signal, a plurality of resistance means R1 to R126 are connected in series to generate a plurality of reference voltages VR1 to VR127 (or VR129 to VR255) to a comparison means. A first resistor string R for outputting each and a plurality of resistor means r1 to r126
In series connection, and the input analog signal VIN input to one end r1 of the plurality of resistance means is sequentially attenuated by different voltage gradients with respect to the voltage gradients of the plurality of reference voltages generated by the first resistor string R. A plurality of attenuated analog signals VI1 ...
It is connected to the second resistor string r for outputting to the plurality of comparing means C1 to C126 as VI126 and one end R126 of the first resistor string R, and is generated in the first resistor string R by switching and controlling the bias voltage. Are connected to the first level shift means VCENT, SW1 for switching the voltage ranges VR1 to VR127 (or VR129 to VR255) of the plurality of reference voltages to be connected to one end r1 of the second resistor string r to control switching of the bias voltage. As a result, second level shift means RL, SW2, SW3 for switching the voltage range of the plurality of attenuated analog signals VI1 to VI126 generated in the second resistor string r.
And the threshold voltage VTH and the input analog signal VIN are compared, and the first threshold voltage VTH is compared based on the comparison result.
And second level shift means VCENT, SW1 and SW
2, the control means 11 for setting the bias voltage value of SW3 respectively, and the comparison result of the comparison means C1 to C127 is corrected based on the bias voltage value set by the control means 11 to obtain the input analog signal VIN. The correction means 12 and 13 for outputting the corresponding digital signals are provided.

[0012]

The value of the bias voltage applied to the one end R126 of the resistor string R for generating the reference voltage is set according to the input analog signal VIN, and the voltage ranges VR1 to VR127 of the plurality of reference voltages applied to the comparing means C1 to C127. To other voltage range V
Change to R129 to VR255. As a result, the comparison means C1
.About.C127 can be shared for a plurality of voltage ranges, the number of elements can be remarkably reduced as compared with the conventional one, and the circuit area of the analog digital conversion circuit can be made much smaller than the conventional one.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Principle of full-scale expansion by resistance division The input analog signal VIN is attenuated by different voltage gradients with respect to the voltage gradient of the reference potential VREF, and the attenuated attenuated analog signal and the reference potential VREF are compared. As a result, the full scale of the input analog signal VIN is expanded to the full scale of the reference potential VREF.

Here, in the case where the voltage gradient of the input analog signal VIN is set to half the voltage gradient of the reference potential and the full scale of the input analog signal VIN is doubled to the full scale of the reference potential VREF. Will be described by taking an AD conversion circuit having 8-bit resolution as an example.

In FIG. 1, the horizontal axis indicates the number of stages of the comparator, and the vertical axis indicates the reference potential VRE input to each comparator.
The potentials of F and the attenuated analog signal VINi are shown. Here, the maximum potential VREFT of the reference potential is applied to the comparators C1 and C255 located at both ends of the group of 255 comparators.
And the minimum potential VREFB, respectively, and the maximum potential VRE is applied to the intermediate comparators C2 to C254.
On the solid line connecting FT and the minimum potential VREFB, 253 reference potentials VREFi lined up at a constant voltage are given.

On the other hand, the input analog signal VIN is half of the voltage gradient of the reference potential (shown by the solid line in FIG. 1) due to each of the 256 voltage dividing resistors connected in series (dotted line in FIG. 1). (Indicated by)) and applied to each of the comparators C1 to C255. Therefore, the first comparator C1 and the 255th comparator C25
5 is the full scale of the reference potential (that is, VREFT-VRE).
FB), a potential difference of 1/2 is generated.

Therefore, if the input analog signal VIN is changed from the maximum value VREFT of the reference potential to the center value of the full scale, that is, if the upper half of the reference potential full scale is the full scale of the input analog signal, the input analog signal The position of the comparator at which the magnitude relationship between the series of attenuated analog signals determined with respect to the signal VIN and the reference potential VREFi is reversed moves from the first comparator C1 to the 255th comparator C255.

Thus, the input analog signal VIN can be converted into digital data by obtaining the position of the comparator Ci at which the magnitude relationship between the potential of the attenuated analog signal and the reference potential is reversed. At this time, the full scale of the input analog signal VIN is 2 with respect to the full scale of the reference potential VREF.
Since it is sufficient to divide it by one, the load applied to the driving stage of the input analog signal VIN becomes small, and the SN ratio can be improved.

(2) Overall configuration of the embodiment In FIG. 2, reference numeral 10 denotes a parallel type A-D conversion circuit having a resolution of 8 bits as a whole, and 8 is a basic configuration of an A-D conversion circuit having a resolution of 7 bits. It is designed to achieve bit resolution. In this example, A-D
The conversion circuit 10 divides the range of the comparison reference voltage into two, that is, an upper side voltage range AR1 and a lower side voltage range AR2.
By switching the comparison operation in the two voltage ranges AR1 and AR2 according to the voltage level of the input signal VIN, 8
It is designed to achieve bit resolution (Fig. 3).

Here, the range of the reference voltage VR generated by the reference resistor train R is level-shifted by switching the bias voltage, and the range of the attenuation signal VI generated by the voltage dividing resistor train r is level-shifted by switching the bias voltage. ing. For this reason, the reference resistor string R and the voltage dividing resistor string r are configured by the following connections, respectively.

That is, the reference resistance line R and the voltage dividing resistance line r
Are 126 reference resistors Ri (i = 1, 2, 3).
...... 126) and voltage dividing resistance ri (i = 1, 2, 3 ... 1
26) are connected in series. Here, the resistance value of the voltage dividing resistor ri is set to one half of the resistance value of the reference resistor Ri, and the currents flowing through the current sources I1 and I2 connected to each resistor string are set to the same value. There is.

As a result, the voltage dividing resistor train r is generated 127.
The voltage gradient of the attenuation signals VI (VI1 to VI126) is 127 reference voltages VR (VR1
.About.VR126) is set to be 1/2 with respect to the voltage gradient. A voltage source VCENT for switching the bias voltage is connected to the midpoint of connection between the reference resistor string R and the current source I1 via a switch SW1. The voltage source VCENT is generated in the reference resistor string R by opening / closing the switch SW1. The range of the voltage level is switched to the upper side or the lower side in comparison with the intermediate potential of the full range.

On the other hand, at the midpoint of connection between the voltage dividing resistor string r and the input terminal P0 of the input signal VIN, a switch SW2 for directly connecting the voltage dividing resistor string r and the input terminal P0 is connected and the voltage dividing resistor is connected. The resistor string r and the input terminal P0 are connected to each other by a resistor RL for level shifting.
A switch SW3 connected via the switch SW3 is connected in parallel to the switch SW2.

Here, the resistance value of the resistor RL is set to a combined resistance value of 126 reference resistors R1 to R126 connected in series, and a voltage dividing resistor is provided by a switch SW2 and a switch SW3 which are opened / closed complementarily. The range of the voltage level of the input signal VIN input to the column r is shifted by ½ of the input range.

The switch of the switch circuit SW is switched by the comparator 11 for range switching. The comparator 11 for range switching uses the input signal VIN
Of the threshold voltage VTH (= VREFT, which is an intermediate potential of the input range and is three-fourths of the full range with respect to the reference potential VREFB).
-I0.RA), switch SW1
Is closed, and when the voltage is lower than the threshold voltage VTH, the switch of the switch circuit SW1 is opened.

Here, the threshold voltage VTH is a connection midpoint potential of the voltage dividing resistors RU and RD to which the reference potential VREFT is given at one end, and the current source I connected to the other end of the voltage dividing resistor RD.
Generated by zero. Incidentally, one end of the voltage dividing resistor RU is connected to the connection midpoint of the two resistors R01 and R02 having high impedance.

The A / D conversion circuit 10 has 127 sets of comparison reference voltages V generated by the switching of the voltage levels.
R1 to VR127 (or VR129 to VR255) and 127 sets of attenuation signals V1 to V127 generated by the voltage dividing resistor train r are compared in comparators C1 to C127, respectively, and the comparison output is set by the encoder 12 in 7 bits. Convert to digital data.

Subsequently, the A / D conversion circuit 10 inputs the thus generated 7-bit digital data to the digital data synthesizing circuit 13, and according to the range of the voltage level generated in the reference resistor string R. The logic value of the highest bit is switched to logic "1" or "0" and is output as 8-bit digital data.

(3) Operation and effects of the embodiment In the above configuration, assuming that the reference potentials VREFT and VREFB provided to the AD conversion circuit 10 are 0 [V] and -2 [V], respectively. The conversion operation will be described assuming that the signal VIN fluctuates in the range of 0 [V] to -1 [V].

First, the input signal VIN changes from 0 [V] to -0.5.
If the analog signal fluctuates in the range of [V], A-
The D conversion circuit 10 detects that the input signal VIN is higher than the threshold voltage VTH by the range switching comparator 11. At this time, the range switching comparator 11
The switch signal S1 is used to close the switch of the switch circuit SW1, and a voltage source V
CENT is applied, and reference voltages V1 to V127 in the range of 0 [V] to -2 [V] are generated in the standard resistor string R.

On the other hand, the range switching comparator 11 is
By closing only the switch circuit SW2 of the pair of switch circuits SW2 and SW3, the input signal VIN is directly supplied to the voltage dividing resistor string r. As a result, 127 sets of attenuation signals VI that fluctuate in the shaded area in FIG. 4 are generated in the voltage dividing resistor array r.

The A / D converter circuit 10 compares the 127 sets of the attenuation signals VI and the reference voltages V1 to V127 by taking in 127 comparators C1 to C127 and comparing them with each other, and encodes 7-bit digital data corresponding to the comparison result. 12
Further, it is supplied to the digital data synthesizing circuit 12, and the digital data synthesizing circuit 12 synthesizes the highest bit with "1" and the output of the encoder 12, and outputs the synthesis result as 8-bit digital data.

On the other hand, the input signal VIN is -0.5 [V]
If the analog signal fluctuates in the range from 1 to -1 [V], the AD conversion circuit 10 uses the range switching comparator 1
1 detects that the input signal VIN is smaller than the threshold voltage VTH. At this time, the range switching comparator 1
1 opens the switch of the switch circuit SW1 by the switching signal S1 to shift the voltage level generated in the reference resistor string R downward by the amount of the voltage source VCENT, and to the reference resistor string R by -1.
Reference voltage V129 to V255 in the range of [V] to -2 [V]
To occur.

On the other hand, the range switching comparator 11 is
By closing the switch circuit SW3 of the pair of switch circuits SW2 and SW3, the input signal VIN is shifted downward by ½ of the input range and supplied to the voltage dividing resistor string r. As a result, 127 sets of attenuation signals VI that fluctuate in the shaded area in FIG. 5 are generated in the voltage dividing resistor array r.

The A / D conversion circuit 10 compares the 127 sets of attenuation signals VI and the reference voltages V1 to V127 with 127 comparators C1 to C127 and compares them, and encoders 7 bit digital data according to the comparison result. 12
Further, it is supplied to the digital data synthesizing circuit 12, and the digital data synthesizing circuit 12 synthesizes the most significant bit with "0" and the output of the encoder 12, and outputs the synthesized result as 8-bit digital data.

According to the above construction, the range of the reference voltage corresponding to the 8-bit resolution is divided into two ranges, and the reference voltages given to the comparators C1 to C127 are divided into the upper reference voltages V1 to V127 and the lower reference voltage. Reference voltage V129-V255
When switching from one of the voltage ranges to the other voltage range, the level of the input signal VIN is shifted at the same time as this switching to shift the voltage dividing resistor series r.
The input can be used to share the comparator between the two voltage ranges.

As a result, the number of stages of the reference resistor array R and the voltage dividing resistor array r can be halved compared to the resolution, and the circuit area of the AD conversion circuit can be further reduced. In the case of this embodiment, the input signal VIN is attenuated by one half of the voltage gradient of the reference voltage, and the attenuated signals are given to the respective comparators for comparison, whereby the input required for the input signal VIN The range can be halved as compared with the conventional one, and as a result, an amplifier circuit with a small gain can be used as an amplifier stage of the input signal VIN, and the SN ratio can be further improved.

(4) Other Embodiments In the above-described embodiment, the voltage gradient of the input signal VIN attenuated by the voltage dividing resistor is divided into two minutes with respect to the voltage gradient of the reference voltage given to each comparator. Although the case of setting to 1 has been described, the present invention is not limited to this, and the voltage gradient by the voltage dividing resistor is ½ of the voltage gradient of the reference voltage.
The present invention can be widely applied to the case of setting a larger value and the case of setting a smaller value.

In the above embodiment, the resistance ratio of the voltage dividing resistor and the reference resistor is set to 1: 2, and the constant current source I1 for drawing the same constant current i1 is connected to each resistor string. However, the present invention is not limited to this, and the resistance values of the voltage dividing resistor and the reference resistor may be the same value, and the ratio of the constant current flowing through the constant current source connected to each resistor string may be set to 1: 2. .

Further, in the above-mentioned embodiment, the case where the present invention is used in the parallel type A-D conversion circuit having the resolution of 8 bits is described, but the present invention is not limited to this.
It can be widely applied to an A-D conversion circuit having a resolution other than the bit.

Further, in the above embodiment, the parallel type A
The reference voltages VRT and VRB of the -D conversion circuit 10 are set to 0, respectively.
The case of setting [V] and −2 [V] has been described, but the present invention is not limited to this and can be widely applied to a case where another value is set as the reference voltage value.

Further, in the above embodiment, the voltage source VCENT for switching the bias voltage is the reference resistor string R and the current source I.
1 has been described with respect to the connection with the switch circuit SW1 via the switch circuit SW1, but the present invention is not limited to this, and the voltage source VCENT
May be connected between the reference resistor string R and the upper reference potential VREFT via the switch circuit SW1.

Further, in the above-mentioned embodiment, the case where the input signal VIN is sequentially attenuated through the voltage dividing resistor series r to generate a plurality of attenuation signals VI has been described, but the present invention is not limited to this, and the All the resistance values of the piezoresistors ri (i = 1 to 126) are set to 0, and the input signals VIN are input to the comparators C1 to C127.
You may input directly. In this case, the switch circuits SW2 and SW3 for level shifting the input signal VIN
You don't have to.

[0045]

As described above, according to the present invention, the value of the bias voltage applied to one end of the resistor string for generating the reference voltage is set according to the input analog signal, and the plurality of reference voltages applied to the comparing means. By changing the voltage range of
The comparing means can be shared for a plurality of voltage ranges, and an analog digital conversion circuit having a remarkably small number of elements can be easily obtained.

[Brief description of drawings]

FIG. 1 is an input / output characteristic diagram for explaining the operation principle of an analog digital conversion circuit according to the present invention.

FIG. 2 is a connection diagram showing an embodiment of an analog digital conversion circuit according to the present invention.

FIG. 3 is a characteristic curve diagram for explaining the operation.

FIG. 4 is a characteristic curve diagram for explaining a comparison operation when the potential of an input signal is higher than a threshold voltage.

FIG. 5 is a characteristic curve diagram for explaining a comparison operation when the potential of the input signal is lower than the threshold voltage.

FIG. 6 is a connection diagram showing a conventional analog digital conversion circuit.

FIG. 7 is a characteristic curve diagram for explaining the operation.

[Explanation of symbols]

10 ... Parallel A / D conversion circuit, 11 ... Range switching comparator, 12 ... Encoder, 13 ... Digital data combining circuit, SW1, SW2, SW3 ... Switch circuit.

Claims (6)

[Claims] 1. An input analog signal is input to a plurality of comparing means in parallel, and the input analog signal is converted into a digital signal based on a result of comparison with a plurality of reference voltages given to the comparing means. In the analog digital conversion circuit, a plurality of resistance means are connected in series, the resistance series that generate the plurality of reference voltages and output to the comparison means, and the bias series are connected to one end of the resistance series and switch the bias voltage. Level shift means for switching the voltage range of the plurality of reference voltages generated in the resistor string by controlling, the threshold voltage and the input analog signal are compared, and based on the comparison result with the threshold voltage. Control means for setting the bias voltage of the level shift means, and an upper limit based on the bias voltage set by the control means. An analog digital conversion circuit, comprising: a correction unit that corrects a comparison result of a plurality of comparison units and outputs a digital signal corresponding to the input analog signal. 2. An input analog signal is input in parallel to a plurality of comparing means, and the input analog signal is converted into a digital signal based on a result of comparison with a plurality of reference voltages given to the comparing means. In the analog digital conversion circuit, a plurality of resistance means are connected in series, and a first resistance string that generates the plurality of reference voltages and outputs the reference voltages to the comparison means and a plurality of resistance means are connected in series. The input analog signals input to one end of the plurality of resistance means are sequentially attenuated by different voltage gradients with respect to the voltage gradients of the plurality of reference voltages generated by the first resistance series, and a plurality of attenuated analog signals are obtained. Is connected to one end of the first resistor string and the second resistor string to be output to the plurality of comparing means, and the first resistor string is switched by controlling the bias voltage. First level shift means for switching the voltage range of the plurality of reference voltages generated in the resistance series, and the second resistance series connected to one end of the second resistance series and controlling the switching of the bias voltage. Second level shifting means for switching the voltage range of the plurality of attenuated analog signals generated in the above, and a threshold voltage and the input analog signal are compared, and the second level shift means is used based on the comparison result with the threshold voltage. The control means for setting the bias voltage values of the first and second level shift means respectively, and the comparison result of the comparing means are corrected based on the bias voltage values set by the control means, and the input analog An analog digital conversion circuit, comprising: a correction means for outputting a digital signal corresponding to the signal. 3. The analog digital conversion circuit according to claim 1, wherein the bias voltage is given by switching a plurality of voltage sources. 4. The current values of the current sources supplied to the first and second resistance series are the same, and the resistance values of the resistance means constituting the second resistance series are the same as those of the first resistance series. 3. The parallel type analog digital conversion circuit according to claim 2, wherein an arbitrary ratio is set with respect to each resistance value of the resistance means constituting the resistance means. 5. The resistance values of the resistance means forming the first and second resistance series are the same, and the first current value supplied to the first resistance series is the second resistance series. 3. The parallel type analog digital conversion circuit according to claim 2, wherein the second current value supplied to the column is set to an arbitrary ratio. 6. The parallel type analog digital conversion circuit according to claim 4 or 5, wherein the ratio is set to be larger than 1.