JPH06112267A - Tab semiconductor device - Google Patents

Tab semiconductor device

Info

Publication number
JPH06112267A
JPH06112267A JP4259517A JP25951792A JPH06112267A JP H06112267 A JPH06112267 A JP H06112267A JP 4259517 A JP4259517 A JP 4259517A JP 25951792 A JP25951792 A JP 25951792A JP H06112267 A JPH06112267 A JP H06112267A
Authority
JP
Japan
Prior art keywords
semiconductor device
tab
conductive patterns
resin
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4259517A
Other languages
Japanese (ja)
Inventor
Takao Sato
尊夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP4259517A priority Critical patent/JPH06112267A/en
Publication of JPH06112267A publication Critical patent/JPH06112267A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To provide a semiconductor device wherein the short circuit between conductive patterns due to fine foreign matter is prevented and a drop in a withstand voltage is prevented in a TAB semiconductor device wherein the number of leads is extremely large and conductive patterns are crowded. CONSTITUTION:In a TAB semiconductor device, a conductive foil is laminated on an insulating film 1 in which a through hole 1b has been made, the conductive foil is extended into the etching hole 1b, conductive patterns 2 including inner leads 2a are arranged in the position of a formed TAB through hole 1a, and electrodes for a semiconductor pellet 3 are connected electrically to the inner leads 2a. In the TAB semiconductor device, the conductive patterns 2 on the insulating film 1 near the inner leads 2a are covered with a resin 6. Since the conductive patterns in which the interval between the inner leads 2a is narrow and which are crowded are covered with the resin 6, it is possible to prevent the short circuit between the conductive patterns even when foreign matter adheres to the parts. In addition, the foreign matter can be detected easily, and the time for the cleaning operation of a bonding tool can be set properly.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、TABテープを用いた
半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a TAB tape.

【0002】[0002]

【従来の技術】TAB式半導体装置の一例を図3から説
明する。図において1は長尺の絶縁フィルムで、両側に
沿って送り用のスプロケットホール1a、1aを穿設
し、長手方向に等間隔で矩形状の透孔1bを穿設してい
る。2は絶縁フィルム1上に積層した導電箔をエッチン
グして形成した導電パターンで、透孔1b内に延在させ
てインナリード2aを形成している。この導電パターン
2はボンディング性を良好にするため金などでメッキし
ている。
2. Description of the Related Art An example of a TAB type semiconductor device will be described with reference to FIG. In the figure, reference numeral 1 designates a long insulating film, and sprocket holes 1a, 1a for feeding are formed along both sides thereof, and rectangular through holes 1b are formed at equal intervals in the longitudinal direction. Reference numeral 2 is a conductive pattern formed by etching a conductive foil laminated on the insulating film 1, and extends inside the through hole 1b to form the inner lead 2a. The conductive pattern 2 is plated with gold or the like to improve the bonding property.

【0003】このような構造のTABテープはリールに
巻き取られて運搬、保管され、製造工程でリールから繰
り出されて供給される。
The TAB tape having such a structure is wound on a reel for transportation and storage, and is unwound from the reel and supplied in the manufacturing process.

【0004】3は透孔1b位置に配置した半導体ペレッ
トで、図4に示すようにTABテープの搬送路に沿う下
方定位置の支持テーブル4上に支持され、その表面に形
成したバンプ電極(符号なし)とインナーリード2aと
を位置決めして支持テーブル4の上方に上下動自在に配
置したボンディングツール5にてバンプ電極とインナリ
ード2aの重合部分を熱圧着して接続している。
Reference numeral 3 denotes a semiconductor pellet arranged at the position of the through hole 1b, which is supported on a support table 4 at a fixed lower position along the transport path of the TAB tape as shown in FIG. Nothing) and the inner lead 2a are positioned and the bump electrode and the overlapping portion of the inner lead 2a are thermocompression-bonded to each other by the bonding tool 5 arranged above the support table 4 so as to be vertically movable.

【0005】このようにして半導体ペレット3を接続し
たTABテープは再度リールに巻取られ、エージング、
検査、表示などの工程に供給される。
The TAB tape to which the semiconductor pellets 3 are connected in this way is rewound on the reel, aged,
It is supplied to processes such as inspection and display.

【0006】この半導体装置のインナリード2aは導電
箔をエッチングして形成されているため、リードフレー
ムを用いる場合に比べ、リード巾、リード間隔を小さく
出来、高集積度の外部引出し電極の多い、例えば液晶表
示装置の駆動用集積回路装置などに適用されている。ま
た、バンプ電極とインナーリード2aの熱圧着はリード
巾、リード間隔が微小になると半導体ペレット3の厚さ
やバンプ電極の高さ、インナリード2aのばらつき、ボ
ンディングツール5と半導体ペレット3の平行度などが
ボンディング品質に大きく影響するため、リードの本数
が多くなると図4に示す一括ボンディング用のボンディ
ングツール5の代わりにキャピラリ状のボンディングツ
ール(図示せず)を用い、インナリード2a毎に1点ず
つボンディングするようにしている。
Since the inner leads 2a of this semiconductor device are formed by etching a conductive foil, the lead width and the lead interval can be reduced as compared with the case where a lead frame is used, and there are many highly integrated external extraction electrodes. For example, it is applied to an integrated circuit device for driving a liquid crystal display device. Further, the thermocompression bonding between the bump electrode and the inner lead 2a is such that the lead width, the thickness of the semiconductor pellet 3 and the height of the bump electrode when the lead spacing becomes minute, the dispersion of the inner lead 2a, the parallelism of the bonding tool 5 and the semiconductor pellet 3, etc. Therefore, when the number of leads increases, a capillary-shaped bonding tool (not shown) is used instead of the bonding tool 5 for collective bonding shown in FIG. 4, one point for each inner lead 2a. I try to bond.

【0007】[0007]

【発明が解決しようとする課題】ところで、半導体ペレ
ット3のバンプ電極とインナリード2aとを熱圧着する
際にボンディングツール5がリード2aに加圧されるた
め、導電パターン2にメッキした金属が剥離してボンデ
ィングツール5に付着し、ボンディングを繰り返すうち
にボンディングツール5からメッキ片が剥落してTAB
テープ上に落下する虞があった。そのため、導電パター
ン2の間隔が密な半導体装置では剥落片が微細であって
も導電パターン2、2間を短絡し半導体装置を不良にす
る虞があるため、異物の有無を検査することが望ましい
が、目視観察では検出が困難であり、テレビカメラを用
い拡大して観察しても、導電パターンと剥落片が同色で
あるため自動判別が困難であった。また、導電パターン
2が微細であると機械的強度が小さく、TABテープを
捻ったり局部的に過大な張力を加えると導電パターンが
断線するという問題もあった。
By the way, when the bump electrode of the semiconductor pellet 3 and the inner lead 2a are thermocompression-bonded, the bonding tool 5 is pressed against the lead 2a, so that the metal plated on the conductive pattern 2 is peeled off. And then adheres to the bonding tool 5, and the plating pieces come off from the bonding tool 5 as the bonding is repeated.
There was a risk of falling on the tape. Therefore, in a semiconductor device in which the conductive patterns 2 are closely spaced, even if the flakes are fine, there is a possibility that the conductive patterns 2 and 2 may be short-circuited and the semiconductor device may be defective. However, it is difficult to detect it by visual observation, and even when the image is magnified and observed using a television camera, automatic discrimination is difficult because the conductive pattern and the flaking piece have the same color. Further, if the conductive pattern 2 is fine, the mechanical strength is small, and if the TAB tape is twisted or a local excessive tension is applied, the conductive pattern is broken.

【0008】[0008]

【課題を解決するための手段】本発明は上記課題の解決
を目的として提案されたもので、透孔を穿設した絶縁フ
ィルム上に導電箔を積層しこの導電箔をエッチングして
透孔内に延在するインナリードを含む導電パターンを形
成したTABテープの透孔位置に配置した半導体ペレッ
ト半導体ペレットの電極とインナーリードとを電気的に
接続したTAB式半導体装置において、上記インナリー
ド近傍の絶縁フィルム上の導電パターンを樹脂にて被覆
したTAB式半導体装置を提供する。
SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-mentioned problems, in which a conductive foil is laminated on an insulating film having a through hole, and the conductive foil is etched to form the inside of the through hole. In the TAB type semiconductor device in which the electrode of the semiconductor pellet and the inner lead electrically connected to the inner lead are arranged in the through hole position of the TAB tape having the conductive pattern including the inner lead extending to the inner lead. Provided is a TAB semiconductor device in which a conductive pattern on a film is covered with a resin.

【0009】[0009]

【作用】本発明によるTAB式半導体装置は、導電パタ
ーン上を樹脂で被覆したから、異物による導電パターン
間の短絡事故を防止できる。また被覆樹脂は、導電パタ
ーンを被覆したメッキや剥落片の異物と異なる色を選択
でき、色対比の大きい色に設定することにより、異物の
観察が容易となる。
In the TAB type semiconductor device according to the present invention, since the conductive pattern is covered with resin, it is possible to prevent a short circuit between conductive patterns due to foreign matter. Further, as the coating resin, a color different from that of the foreign matter of the plating or the flaking pieces coated with the conductive pattern can be selected, and the foreign matter can be easily observed by setting a color having a large color contrast.

【0010】[0010]

【実施例】以下に本発明の実施例を図1から説明する。
図において図3と同一符号は同一物を示し説明を省略す
る。図中相違するのはインナリード2aと隣接した絶縁
フィルム1及びその上に密集して積層された導電パター
ン2上を樹脂6で被覆したことのみである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG.
In the figure, the same reference numerals as those in FIG. The only difference in the figure is that the insulating film 1 adjacent to the inner lead 2a and the conductive pattern 2 densely stacked on the insulating film 1 are covered with the resin 6.

【0011】この樹脂6は異物の色に対してコントラス
トの大きい、例えば異物が金である場合、緑色の樹脂を
用いることによって、異物による導電パターン2、2間
の短絡を防止でき、異物の発生を容易に知ることが出
来、ボンディングツール5の清浄作業の時期を適切に設
定できる。
This resin 6 has a large contrast with respect to the color of the foreign matter. For example, when the foreign matter is gold, a green resin can be used to prevent a short circuit between the conductive patterns 2 and 2 and the foreign matter is generated. Can be easily known, and the time for cleaning the bonding tool 5 can be set appropriately.

【0012】図2は本発明の他の実施例を示す。この実
施例では図1実施例の樹脂6を樹脂6a、樹脂6bの二
層に2度塗りしたもので、一層目の樹脂6aの厚さはは
導電パターン2の厚み以下に設定され、樹脂6aと樹脂
6bの厚さの和が導電パターン2の厚さより大きくなる
ように設定されている。この二重塗り部分は導電パター
ン2のインナリード2aと隣接して密集した部分に設定
し、導電パターン2の間隔が異物の径より大きい部分で
は一層でもよい。
FIG. 2 shows another embodiment of the present invention. In this embodiment, the resin 6 of FIG. 1 embodiment is applied twice to two layers of the resin 6a and the resin 6b, and the thickness of the resin 6a of the first layer is set to be equal to or less than the thickness of the conductive pattern 2. And the thickness of the resin 6b are set to be larger than the thickness of the conductive pattern 2. This double-coated portion is set in a dense portion adjacent to the inner lead 2a of the conductive pattern 2, and may be even more in a portion where the distance between the conductive patterns 2 is larger than the diameter of the foreign matter.

【0013】これにより、絶縁フィルム1の透孔1b周
りが補強され、絶縁フィルム1に撓み変形が加えられて
も透孔1b周りの変形が抑制され、インナリード2aの
捻れや間隔が不均一になるという問題が防止でき、また
この半導体装置を実装する場合、アウタリード(符号な
し)部分は薄い樹脂6aのみであるため容易に湾曲変形
でき実装性がよい。
As a result, the periphery of the through hole 1b of the insulating film 1 is reinforced, and even if the insulating film 1 is flexibly deformed, the deformation around the through hole 1b is suppressed, and the inner leads 2a are not twisted or evenly spaced. When the semiconductor device is mounted, the outer lead (no reference numeral) is made of only the thin resin 6a, so that it can be easily bent and deformed, and the mountability is good.

【0014】また、この樹脂6a、6bはそれぞれ絶縁
フィルム1の色と異なる色に設定し、その塗布パターン
と色の組み合せにより、半導体装置の機種名、極性、ロ
ット番号、製造年月日などの表示をすることが出来る。
Further, the resins 6a and 6b are set to colors different from the color of the insulating film 1, and the combination of the coating pattern and the color allows the semiconductor device model name, polarity, lot number, manufacturing date, etc. Can be displayed.

【0015】[0015]

【発明の効果】以上のように本発明によれば、インナリ
ード2aの間隔が狭小で従って密集した導電パターン2
の表面を樹脂6で被覆したから、この部分に異物が付着
しても導電パターン間の短絡や耐電圧低下を防止でき
る。
As described above, according to the present invention, the inner leads 2a are closely spaced and therefore densely packed.
Since the surface of the resin is coated with the resin 6, it is possible to prevent a short circuit between conductive patterns and a decrease in withstand voltage even if a foreign matter adheres to this portion.

【0016】また異物の発見が容易で、ボンディンクツ
ールの清浄作業の時期を適切に設定できる。
Further, it is easy to find foreign matter, and the time for cleaning the bonding tool can be set appropriately.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例を示すTAB式半導体装置の
側断面図。
FIG. 1 is a side sectional view of a TAB type semiconductor device showing an embodiment of the present invention.

【図2】 本発明の他の実施例を示す側断面図FIG. 2 is a side sectional view showing another embodiment of the present invention.

【図3】 TAB式半導体装置の一例を示す斜視図FIG. 3 is a perspective view showing an example of a TAB semiconductor device.

【図4】 図3半導体装置の製造方法を説明する側断面
FIG. 3 is a side sectional view illustrating a method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 絶縁フィルム 1a 透孔 2 導電パターン 2a インナリード 3 半導体ペレット 6、6a、6b 樹脂 1 Insulating Film 1a Through Hole 2 Conductive Pattern 2a Inner Lead 3 Semiconductor Pellets 6, 6a, 6b Resin

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】透孔を穿設した絶縁フィルム上に導電箔を
積層しこの導電箔をエッチングして透孔内に延在するイ
ンナリードを含む導電パターンを形成したTABテープ
の透孔位置に配置した半導体ペレット半導体ペレットの
電極とインナーリードとを電気的に接続したTAB式半
導体装置において、上記インナリード近傍の絶縁フィル
ム上の導電パターンを樹脂にて被覆したことを特徴とす
るTAB式半導体装置。
1. A conductive foil is laminated on an insulating film having a through hole, and the conductive foil is etched to form a conductive pattern including an inner lead extending in the through hole at a through hole position of a TAB tape. Arranged semiconductor pellets A TAB type semiconductor device in which electrodes of semiconductor pellets and inner leads are electrically connected, wherein a conductive pattern on an insulating film near the inner leads is covered with resin. .
【請求項2】導電パターンを被覆する樹脂が多層に形成
されていることを特徴とする請求項1記載のTAB式半
導体装置。
2. The TAB semiconductor device according to claim 1, wherein the resin coating the conductive pattern is formed in multiple layers.
【請求項3】導電パターンを被覆する樹脂が表示パター
ンを兼ねることを特徴とする請求項2記載のTAB式半
導体装置。
3. The TAB type semiconductor device according to claim 2, wherein the resin coating the conductive pattern also serves as a display pattern.
JP4259517A 1992-09-29 1992-09-29 Tab semiconductor device Pending JPH06112267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4259517A JPH06112267A (en) 1992-09-29 1992-09-29 Tab semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4259517A JPH06112267A (en) 1992-09-29 1992-09-29 Tab semiconductor device

Publications (1)

Publication Number Publication Date
JPH06112267A true JPH06112267A (en) 1994-04-22

Family

ID=17335204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4259517A Pending JPH06112267A (en) 1992-09-29 1992-09-29 Tab semiconductor device

Country Status (1)

Country Link
JP (1) JPH06112267A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172043A (en) * 1995-12-21 1997-06-30 Nec Kyushu Ltd Tab tape carrier and semiconductor device
JP2006053182A (en) * 2004-08-09 2006-02-23 Matsushita Electric Ind Co Ltd Component mounting system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172043A (en) * 1995-12-21 1997-06-30 Nec Kyushu Ltd Tab tape carrier and semiconductor device
JP2006053182A (en) * 2004-08-09 2006-02-23 Matsushita Electric Ind Co Ltd Component mounting system

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