JPH06111486A - Modulation circuit - Google Patents

Abstract

PURPOSE:To rapidly output an optimum margin bit with a simple circuit without testing individual margin bit in a modulation circuit in a CD system. CONSTITUTION:The optimum margin bit 44 corresponding to an input signal is outputted based on 52 kinds of selective items programed previously by a PLA 43 in a margin bit generation circuit 40 loaded on the modulation circuit. The input signals consist of a 4 bits signal showing a prohibition margin bit, a CWLL signal showing the final signal level of front 14 bits data, 3 bits data indicating the control direction of a cumulative DSV and 5 bits signal showing the DSV of the 14 bits data placed behind the margin bit. The CWLL signal and a control signal are decoded by a decoder 41, and the 5 bits signal is decoded to 5 cases and supplied to the PLA 43 by the decoder 42. Thus, the optimum margin bit 44 is generated from the PLA 43 without testing individual margin bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation circuit of a recording system for recording digital audio signals and the like. For example, a write-once type (hereinafter referred to as WO) or a rewritable type (hereinafter referred to as MO) conforming to a compact disc (CD) system. In the modulation circuit of the CD recording / reproducing apparatus described above, the present invention is applied to control of digital summation (hereinafter referred to as DSV) of channel coding.

[0002]

2. Description of the Related Art In recording a digital audio signal,
After the error detection and correction code is added to the digital signal,
It is supplied to the modulation circuit and converted (channel coding) into a code suitable for the characteristics of the recording and reproducing system.

FIG. 9A is a diagram showing an outline of a signal format of the CD system, and 8-14 conversion (hereinafter referred to as EFM) is used as a modulation system.

The EFM is an 8-bit code (hereinafter,
(Symbol) is converted to a code of 14 channel bits, a sync signal of 24 channel bits and a subcode of 14 channel bits are added, these codes are connected by margin bits of 3 channel bits, and NRZI recording is performed. It is a method.

FIG. 9B is a diagram showing a frame structure of the CD system.

As shown in the figure, a CIRC (Cross Interleaved Reed-Solomon Code) encoder inputs data to a modulation circuit during one sync frame (six sample value sections, 6 samples for each of the L and R channels, 1 sample is 16-bit data) 24. The data of symbols and the parity of 8 symbols are respectively converted into 14 channel bits and concatenated with margin bits of 3 channel bits to make 588 channel bits per frame as shown in FIG. 4.3.
NR on CD with channel bit rate of 218Mbps
ZI recorded.

Here, for each symbol input to the modulation circuit, for example, referring to a look-up table ROM,
The number of "0" s between "1" and "1" is converted into channel bit patterns of 2 or more and 10 or less, respectively.
Further, the channel bit pattern of the frame synchronization signal Sf is "10000000000100000000001".
0 ", the margin bit pattern is" 000 ",
One of “001”, “010” and “100” is selected. Furthermore, one subcoding frame is 9
The sub-code sync signal S ₀ (= “0010
0000000001 "), S ₁ (=" 0000000
0010010 ″) is added (see FIG. 9C).

FIG. 10 shows E for one example of sample values.
It is a figure which shows the channel bit pattern after FM, and DSV (digital sum variation).

One 16-bit sample is divided into high-order 8 bits and low-order 8 bits, which are input to a modulation circuit via a CIRC encoder and subjected to 8-14 conversion to be information bits. Between the information bits "1" and "1", two or more and 10
The number of "0" or less is intervening. "0" as the margin bit
One of "00", "001", "010", and "100" is selected, and this rule is always established even for the connection portion of information bits.
An EFM signal in units of 17 channel bits (however, 27 channel bits in the case of the frame synchronization signal Sf) is output from the modulation circuit at 4.3218 Mbps.

Thus, any channel bit "1"
Since 2 to 10 channel bits "0" are present between the next channel bit "1" and the next channel bit "1", the high level or low level duration (recording wavelength) of the NRZI recording waveform is always 3T or more and 11T or more. The following is obtained (see FIG. 10). That is, in this case, the shortest recording wavelength is 3T and the longest recording wavelength is 11T. However, T is the channel clock 4.
It is one cycle of 3218 MHz.
It is called the T-11T rule.

Consider digital sum variation (DSV) as an index of DC balance of the NRZI recording waveform. DSV is given as the time integral of the recording waveform. That is, the change amount of the DSV when the high level of the recording waveform continues for the unit time T is set to +1 and the change amount of the DSV when the low level continues for the unit time T is set to -1.

Time t₀The initial value of DSV at
Figure 10 shows the change in DSV with time
Shown in columns. Here, period t₁~ T₂The modulation signal at is 1
7-channel bit pattern "01000000100000
01001 ”is not uniquely determined,
Tick t₁Modulation signal level at time t₀~ T ₁
The final level of the modulation signal waveform at (hereinafter, CWLL and
Say). Therefore, the modulation signal waveform shown is the time
t₀At the low level (CWLL =
"0") at time t₀At CWLL =
The modulation signal waveform for "1" (high level) is high level
It becomes the reverse pattern in which the low level and the low level are replaced. As well
In addition, the increase / decrease of DSV also depends on CWLL, and at time t₀smell
If CWLL = "0", information bit
DS according to the pattern "01000100100010"
V change (hereinafter referred to as 14 NWD), that is, the period t
₀~ T_{0 + 14}Change in DSV at +2 as shown
Is. Contrary to the figure, time t₀At CWLL =
If it is "1", 14NWD = -2. Also, the period t_{0 + 14}
~ T_{1 + 14}The change in DSV at 17 is called 17NWD.

Margin bits inserted in the periods t _{0 +14 to} t ₁ will be described.

Four types of margin bits "000" and "0"
EFM3 out of 01 ”,“ 010 ”and“ 100 ”
According to the T-11T rule, "001" and "100" cannot be inserted, but "010" or "000" can be inserted. That is, if the number of "0s" at the end of the previous information bit pattern output before the margin bit is B and the number of "0s" at the tip of the current information bit pattern output later is A, B = 1
Since A = 1, the leading edge of the margin bit must be "0" and the trailing edge must be "0", and the insertable margin bit pattern is "0x0".

The solid line shows the DSV when "010" is inserted as a margin bit, and the dotted line shows the DSV when "000" is inserted.

As described above, when two or more margin bits of four types can be added, any one of the margin bits is selected so that the DSV becomes as small as possible based on the current information bit 14NWD. It That is, since the DSV at time t _{1 + 14} is +3 when “010” and −1 when “000”, “000” is selected as the optimum margin bit, and this is the period t.
_{0 + 14} is added to ~t _1.

As mentioned above, the margin bits are
EF at the connection point between information bit patterns
Selected to satisfy the M3T-11T rules, then DSV if multiple margin bits can be inserted.
Select the margin bit that makes x closest to zero.

FIG. 11 is a block diagram of the modulation circuit disclosed in JP-A-1-319178.

Reference numeral 101 is a CIRC encoder (not shown)
Input terminal of each symbol input from, 102 is 4.32
Input terminal for system clock Sc of 18 MHz, 103
Is a frame sync timing signal input terminal, and 104 is a subcoding frame sync timing signal input terminal.

The symbols sequentially input to the input terminal 101 are subjected to 8-14 conversion by the ROM 111 and then converted into the register 112.
And four 4-bit data A and B representing the number of “0” s at the beginning and end of 14-bit data are stored in the register 112.

At the sync timing of each frame and the sync timing of the sub-coding frame, the pseudo frame sync signal S'f and the sync signals S ₀ and S _{1 of the} sub-coding frame are 14 from the ROM 116 under the control of the system control circuit 115, respectively. It is output as bit data and stored in the register 112. here,
The 24-bit frame sync signal Sf is actually a 14-bit pseudo frame sync signal S′f (= “10000
000000100 ") is a, is converted to a frame synchronizing signal Sf of 24 bits in the output. Further, the sync signal S'f, S _0, of the tip and terminating S _1" 2 four-bit data representing the number of 0 ' A and B are stored in the register 112.

Since the 14-bit data stored in the register 112 is sequentially transferred to the registers 113 and 114,
The register 113 stores the previous 14-bit data, and the register 114 stores the previous 14-bit data. The 4-bit data A is transferred from the register 112 to the ROM 11
7 and 118, 4-bit data B is stored in register 1
12 is transferred to the register 113, the previous 4-bit data B is transferred from the register 113 to the ROM 117, 11
8 are supplied.

The ROM 117 receives the 4-bit data A and the previous 4-bit data B as address inputs, and EFM3T ...
Select the margin bit that satisfies the 11T rule from the selector 12
Output to 0. Although it does not violate the EFM3T to 11T rules, an exceptional combination that results in including the same bit pattern as the 24-bit frame sync signal Sf in the bit patterns connected by the margin bits (11
In the case of the example), the ROM 118 outputs a margin bit that is particularly limited so that such a combination does not occur. That is, the ROM 118 outputs the margin bit when the exceptional prohibition occurs to the selector 120.

The detection circuit 119 includes registers 112 and 11
By referring to the three 14-bit data stored in 3, 114 and the previous margin bit stored in the register 142, the occurrence of the above-mentioned exceptional combination is detected, and the reading of the margin bit is performed from the ROM 117 to the ROM 118. Switch. The margin bits output from the ROM 117 or the ROM 118 are stored in the ROM via the selector 120.
It is input to 122 as an address. Also, the ROM 123
14-bit data is input as an address from the register 112.

The ROM 122 outputs the DSV and the polarity of the input margin bit. The DSV is stored in the DSV register 125 and the polarity is stored in the polarity register 127. Further, the ROM 123 outputs the DSV and the polarity of the input 14-bit data, and the DSV is stored in the DSV register 124 and the polarity is stored in the polarity register 126.

There are four types of margin bits output from the ROM 117 or 118 (hereinafter referred to as the first, second, third and fourth margin bits) at the maximum, but four types are always used to unify the processing. Margin bits are output. The optimum margin bit among them is determined as follows.

1) First margin bit test: Under the control of the selector 121, the selector 120 supplies the first margin bit to the ROM 122 as an address input. The DSV and its polarity for the first margin bit output from the ROM 122 are stored in the registers 125 and 127, respectively. At the same time, the DSV and the polarity of the 14-bit data output from the ROM 123 are stored in the registers 124 and 126, respectively.

Cumulative DSV output from register 130
Is applied to the adder / subtractor circuit 128 via the logic circuit 131, and the input B plus input A is calculated for negative polarity, and the input B minus input A is calculated for positive polarity. Here, the input B is the cumulative DSV supplied from the register 129,
Input A is the DSV for the first margin bit provided by register 125. Calculation result of the adder / subtractor circuit 128, that is, cumulative DS when the first margin bit is added
V is stored in the register 132. The absolute value of the calculation result is stored in the register 135 via the absolute value circuit 134.

Next, the cumulative DSV stored in the register 132 when the first margin bit is added is supplied to the adder / subtractor circuit 128 as the input B and stored in the register 124.
The DSV for the 4-bit data is supplied as an input A to the adder / subtractor circuit 128, and the addition or subtraction between the input B and the input A is performed. Here, the arithmetic control signal for addition or subtraction is supplied from the logic circuit 131 as an exclusive OR of the polarity of the cumulative DSV stored in the register 130 and the polarity of the first margin bit stored in the register 127.

The calculation result of the adder / subtractor circuit 128 and its absolute value are stored in the registers 132 and 135, respectively.

The logic circuit 131 includes registers 126 and 12
The exclusive ORs of the three polarities stored in Nos. 7 and 130 are calculated, and the calculation result is stored in the register 138.

The margin bit number (here, the first margin bit “1”) used for the calculation of the accumulated DSV stored in the register 132 is stored in the indicator 140.

2) Second margin bit test: RO controlled by selector 121 via selector 120
The second margin bit is input to M122 as an address, and the DSV of the second margin bit output from the ROM 122 and its polarity are stored in the registers 125 and 127, respectively.

The calculation of the cumulative DSV when the second margin bit is added by the adder / subtractor circuit 128 is performed in the same manner as in the case of the first margin bit. In the case of the second margin bit and thereafter, the operation result and its absolute value are stored in the register 133 and the register 136, respectively, unlike the case of the first margin bit (instead of the registers 132 and 135).

Adder / subtractor circuit 1 having as input B the cumulative DSV stored in the register 133 when the second margin bit is added
The operation of cumulative DSV at the time of adding 14-bit data by 28 is performed in the same manner as the case of the first margin bit, and in the case of the second margin bit and thereafter, the operation result and its absolute value are stored in the register 133 and the register 136, respectively. To be done.

Next, it is determined whether the current margin bit is more appropriate than the already tested margin bit. Since the margin bit is selected so that the absolute value of the cumulative DSV approaches zero as much as possible, the absolute value of the previous cumulative DSV stored in the register 135 and the absolute value of the current cumulative DSV stored in the register 136 are calculated. Compare. That is, the adder / subtractor circuit 128, which is set to the subtraction mode by the control of the logic circuit 131, receives the first
Input the absolute value of the cumulative DSV for the margin bit B
Then, the absolute value of the cumulative DSV for the second margin bit supplied from the register 136 is used as the input A, and the input A is subtracted from the input B.

When the subtraction result is positive, that is, when the accumulated DSV of the second margin bit is closer to zero, the contents of the register 133 are stored in the register 132 and the logic circuit 1
The exclusive OR of the three polarities of the registers 126, 127, and 130 output from 31 is stored in the register 138, and the number of the margin bit used for the calculation of the accumulated DSV stored in the register 132 (here, the second The margin bit “2”) is stored in the indicator 140. When the subtraction result is negative or zero, the contents of the registers 132 and 138 and the indicator 140 as described above are not updated.

In this way, the register 132 stores the accumulated DSV when the optimum margin bit is used among the margin bits tested up to now, and the register 13 is stored.
The polarity is stored in 8 and the indicator 14
The optimum margin bit number is stored in 0.

3) Third margin bit test: The same processing as in the case of the second margin bit is performed on the third margin bit supplied via the selector 120. As a result, the register 132 stores the accumulated DSV of the optimum margin bit among the first to third margin bits tested so far, the polarity thereof is stored in the register 138, and the optimum margin is stored in the indicator 140. Bit number is stored.

4) Fourth margin bit test: The same processing as in the case of the second and third margin bits is performed on the fourth margin bit supplied via the selector 120. As a result, the register 132 accumulates the optimum margin bit D among all the margin bits.
The SV is stored, the polarity is stored in the register 138, and the optimum margin bit number is stored in the indicator 140.

As a result of the above tests 1) to 4), the optimum margin bit is found, and then the output process is performed.

The optimum margin bit number stored in the indicator 140 is given to the selector 120 via the selector 121, and the selector 120 selects the optimum margin bit from the margin bits input from the ROM 117 or 118 and registers it. It outputs to 141. In addition, the cumulative DSV stored in the register 132 when the optimum margin bit is used is stored in the cumulative DSV register 129, and the polarity stored in the register 138 is stored in the cumulative polarity register 130.
Update 30.

In this way, the selection and output of the optimum margin bit for the current 14-bit data stored in the register 112 is completed, and the ROM 111 or ROM 1 is completed.
The next 14-bit data and two 4-bit data A and B are output from 16 and stored in the register 112. At the same time, the optimum margin bit for the current 14-bit data stored in the register 141 is
2 and stored.

The optimum margin bit output from the register 142 corresponds to the current 14 bits output from the register 113.
The 17-bit data obtained by concatenating the bit data is loaded into the parallel-in / serial-out shift register 143 and set to 1 during the subsequent 17 system clock (Sc) periods.
It is output to the exclusive OR (XOR) circuit 144 as 7-channel bit serial data. Based on the frame sync timing signal supplied from the input terminal 102 via the system control circuit 115, the XOR circuit 144
After converting the 14-bit pseudo frame sync signal S'f of the serial data input from the shift register 143 into the regular 24-bit frame sync signal Sf,
Through the flip-flop circuit 145, 4,3218M
Output as an EFM signal of bps.

In the above-mentioned conventional example, in order to prevent the overflow of the cumulative DSV, the cumulative DSV is calculated every sub-coding frame (that is, every 98 sync frames).
The register 129 and the cumulative polarity register 130 are reset.

[0046]

In the conventional modulation circuit, the cumulative DSV and its polarity are actually calculated for each of the four types of margin bits as described above, and the optimum margin bit is selected from the result. . Therefore, in order to select the optimum margin bit, it is necessary to constantly perform four tests in parallel or in a time-division manner, which has a drawback that the modulation circuit becomes complicated and large-scaled. However, in the case of the reproduction-only CD system, the modulation circuit is used as a part of a large-scale CD production system (for example, a laser cutting machine), and therefore the above-mentioned drawbacks have not been a major obstacle.

On the other hand, in the CD type recording / reproducing apparatus such as the recently proposed mini disk system, the modulating circuit must be miniaturized and built in each apparatus, so the above-mentioned drawbacks become a major obstacle. Was there.

Therefore, according to the present invention, the optimum margin bit can be uniquely generated without performing a test,
Moreover, the present invention proposes a modulation circuit which has a small circuit scale and is convenient for LSI implementation.

[0049]

In order to solve the above-mentioned problems, in the present invention, an input m-bit code sequence is converted into an n (where n> m) channel bit pattern, and this n-channel bit pattern is converted. A signal related to the above margin bits, which is prohibited from being used in a modulation circuit that limits the longest and shortest recording wavelengths by combining one of a plurality of types of margin bits and suppresses the low frequency component of the recording waveform. , A signal related to the final recording waveform level of the n-channel bit pattern that precedes this margin bit, a control signal related to cumulative digital summation (hereinafter referred to as DSV), and a signal that follows this margin bit. A signal related to the DSV of the n-channel bit pattern is input, and the above-mentioned margin types And has a margin bit generating means for outputting uniquely regardless of the test the best one of the bets.

[0050]

In the modulation circuit according to the present invention, the signals input to the margin bit generation circuit 40 shown in FIG. 1 are as follows. Four types of margin bits "100" and "01"
EMF3T-11 of 0 ”,“ 001 ”, and“ 000 ”
A 4-bit prohibition signal, which is set by setting a prohibition flag “1”, is input from the prohibition margin bit discriminating circuit 20 to the margin bit that conflicts with the T rule and the margin bit that is erroneously generated by the frame sync. Also, cumulative DSV
Is a 3-bit control signal "10" indicating that the desired control direction is increase (+), balance (0) or decrease (-).
0 ”,“ 010 ”or“ 001 ”is the DSV integration circuit 6
Enter from 0. In addition, the leading 1 in the margin bit
A 1-bit signal (“0” at low level, “1” at high level) indicating the final signal level (hereinafter, referred to as CWLL) of the NRZI waveform of the 4-bit data Db, and is placed after the margin bit 14 A 5-bit signal representing the DSV of the bit data Dp in 2's complement is supplied.

The respective bits of the 4-bit prohibition signal are, for example, margin bits "001" and "0" in order from the upper bit.
EFM compatible with 10 ”,“ 100 ”and“ 000 ”
A flag "1" is set to the margin bit prohibited by the 3T to 11T rules and the bit corresponding to the margin bit in which the frame sync is erroneously generated. For example, the number B of "0s" at the end of 14-bit data Db placed before the margin bit is 4 and 1 is placed after it.
When the number A of "0s" at the tip of the 4-bit data Dp is 5, the use of the margin bit "000" is prohibited by the EFM3T to 11T rules, and the 4-bit prohibition signal "0" is used.
001 ″ is output from the prohibited margin bit determination circuit 20 to the programmable logic array (PLA) 43.

A 3-bit control signal input from the DSV integrating circuit 60 (the first bit is an instruction to increase cumulative DSV "+").
When the second bit represents the balanced instruction "0" and the third bit represents the decrement instruction "-", they are respectively set to "1") and the decoder 4 uses the CWLL signal as a gate signal.
1 to the PLA 43. Here, the decoder 41 outputs to the PLA 43 a 3-bit control signal converted so that the PLA 43 can output the optimum margin bit 44 regardless of the polarity of CWLL. That is, CWLL =
When it is "1", the input control signal is an increase command "100".
If so, it is converted to the decrease instruction “001” and the decrease instruction “001”
If so, the increase command is converted to "100", and the balance command is "0".
If it is 10 ", it is directly output to the PLA 43 without conversion.

The DSV of the 14-bit data Dp, that is, the amount of change in the cumulative DSV when the 14-bit data Dp is added after the margin bit (hereinafter referred to as 14NWD) is
It is represented by a 5-bit two's complement number, is input to the decoder 42 as a 14NWD signal, and is decoded into the following five cases.

1) When 14NWD ≧ 3, the 4-bit signal “1000” is output from the decoder 42 to the PLA 43.

2) When 14NWD = 2, the 4-bit signal "0100" is output from the decoder 42 to the PLA 43.

3) When 14NWD = 1, the 4-bit signal "0010" is output from the decoder 42 to the PLA 43.

4) When 14NWD = 0, the 4-bit signal "0001" is output from the decoder 42 to the PLA 43.

5) When 14NWD≤-1, the 4-bit signal "0000" is output from the decoder 42 to the PLA 43.

The PLA 43 has an 11-bit input signal (a 4-bit signal indicating a prohibition margin bit, a 3-bit control signal for instructing the control direction of accumulated DSV, and a 14NWD signal).
The optimum margin bit 44 is uniquely output corresponding to the combination of the 4-bit signal indicating the above five cases.

[0060]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows that the margin bits "100", "010", "001" or "00" are optimal depending on the situation.
FIG. 9 is a block diagram showing an embodiment of a margin bit generating circuit 40 according to the present invention that uniquely generates 0 ″.

FIG. 2 shows the margin bit generation circuit 40.
FIG. 3 is a block diagram showing a modulation circuit according to the present invention in which is mounted.

First, FIG. 2 will be described.

Data of 32 symbols per one sync frame is input to the input terminal 10 from a data generation circuit (not shown). Each 8-bit symbol is EF
8-1 for each 14-bit data by MROM11
4 converted.

Constructing a subcoding frame 98
The 0th and 1st sync frames of the sync frame include
As described above, 14-bit subcode sync signals S0 and S1 are added. This subcode sync signal S0,
The addition of S1 is performed by the subcode sync addition circuit 12 based on a subcode sync timing signal (not shown).

The pseudo frame sync adding circuit 13 is based on a frame sync timing signal (not shown) and has a 14-bit pseudo frame sync signal S'f (= "1xxxx.
xxxxxxxxx10 ") is added to the beginning of each sync frame. The bit pattern of the leading 1 bit and the trailing 2 bits of the pseudo frame sync signal S'f is a regular 24-bit frame sync signal Sf (=" 1000000000 ").
Since it is the same as that of 01000000000010 "), when the margin bit is selected, the same processing as other 14-bit data can be performed.

14-bit data Dp including sub-code sync signals S0 and S1 and pseudo frame sync signal S'f
Are sequentially supplied to the register 14 and latched, and the upper 12 bits thereof are supplied to the inhibition margin bit determining circuit 20. At the same time, the previous 14-bit data Db latched in the register 14 is output to the frame sync conversion circuit 15 and the inhibition margin bit determination circuit 20, and the lower 2 bits of the 14-bit data Db are stored in the register 31. Stored in. The lower 2 bits stored last time, that is, the 14-bit data Db two times before the last time
The lower 2 bits of b are supplied from the register 31 to the inhibition margin bit determination circuit 20. The current margin bit Mp supplied from the margin bit generation circuit 40 described later is stored in the register 32. 3 stored last time
The bit data, that is, the previous margin bit Mb is supplied from the register 32 to the prohibited margin bit determination circuit 20.

The prohibition margin bit discriminating circuit 20 determines the upper 12 bits of the 14-bit data Dp of this time and the previous 14 bits of the 14-bit data Dp.
Based on the lower 2 bits of the bit data Db, the previous margin bit Mb, and the 14-bit data Dbb two times before, the margin bit that conflicts with the EFM3T-11T rule and the exceptional prohibition rule is determined, and the margin bit generating circuit is used as the prohibition signal. Output to 40. This prohibition signal is 4
Each of the bits corresponds to four types of margin bits “100”, “010”, “001”, and “000”. For example, when the first and third margin bits “100” and “001” are prohibited by the EFM3T to 11T rules and the exceptional prohibition rule, the 4-bit prohibition signal is set to “1010”.

Here, the pseudo frame sync addition circuit 1
3, the registers 14, 31, 32 and the prohibition margin bit discrimination circuit 20 constitute a discrimination circuit 30.

That is, the discriminating circuit 30 receives the 14-bit data Dp supplied from the sub-code sync adding circuit 12,
The margin bit Mp supplied from the margin bit generation circuit 40 is used as an input signal, and the previous 14-bit data D
b to the frame sync conversion circuit 15, and the previous 14-bit data Db and the current 14-bit data D
4 that indicates the margin bit that should not be used for concatenation with p
The bit inhibition signal is output to the margin bit generation circuit 40.

FIG. 3 is a diagram showing an algorithm for determining a prohibited margin bit.

The prohibition margin bit discriminating circuit 20 performs a test of the bits shown by hatching in FIG. 3 among the input signals Dp, Db, Mb and Dbb, and according to the result, the previous 14-bit data Db and this time are tested. The margin bit Minh which should not be used for connection with the 14-bit data Dp is determined, and the 4-bit inhibition signal Sinh is supplied to the margin bit generation circuit 40.

In FIG. 3A, EFM3T to 11T
The algorithm for discriminating the prohibited margin bit Minh by the rule is as follows.

1) The total number of the number "0" at the front end of the 14-bit data Dp this time and the number B of "0" at the end of the previous 14-bit data Db is 8 or more (A + B ≧ 8). Case: Margin bit “000” is prohibited (Minh
= “000”).

2) The most significant bit C1 of the current 14-bit data Dp is "1" (A = 0) or the next most significant bit C2 is "1" (A = 1), or the previous 14-bit data Dp.
When the number B of “0” s at the end of b is 9 (B = 9): the margin bit “001” is prohibited (Minh = “00”).
1 ”).

3) The most significant bit C1 of the current 14-bit data Dp is "1" (A = 0), or the least significant bit C14 of the previous 14-bit data Db is "1" (B = 0).
If: Margin bit “010” is prohibited (Min
h = “010”).

4) The number of "0s" at the end of the 14-bit data Dp this time is 9 (A = 9), or the least significant bit C14 of the previous 14-bit data Db is "1" (B =
0) or the next-order bit C13 is "1" (B = 1): the margin bit "100" is prohibited (Minh =
"100").

In FIG. 3B, EFM3T to 11T
The judgment of the margin bit that does not violate the rule but is prohibited in order to prevent the frame sync signal from being erroneously generated, that is, the prohibition margin bit by the exceptional prohibition rule is as follows.

Case (1): Previous 14-bit data D
When the number B of “0s” at the end of b is 7, and the frame sync signal is generated at this timing.

Case (2): The frame sync signal is generated last time, and C1 to C6 of the 14-bit data of this time
Is 0 (A = 6).

Case (3): In the case of "B = 7 and upper 11 bits of Dp =" 10000000000000 "".

Case (4): "Lower 13 bits of Db =
In the case of "0000000000100" and A = 5 ".

Case (5): In the case of "B = 6 and upper 12 bits of Dp =" 0100000000000 "".

Case (6): "Lower 12 bits of Db =
In the case of “000000000010” and A = 6 ”.

Case (7): "Lower 11 bits of Db =
In the case of "0000000000001" and A = 7 ".

Case (8): "Previous margin bit M
b = “000” and Db = “00000000001000”
In the case of 000 "and A = 1".

Case (9): "The least significant bit C14 =" 0 "of the 14-bit data Dbb two times before and" Mb = "
“000” and Db = “0000001000000
In case of "0"".

Case (10): "Mb =" x00 ", Db =" 00000000100000 ", and A =
In case of 2 ”.

As described above, in the cases (1) to (10), the margin bit “000” is prohibited (Minh = “00”).
0 ").

Case (11): "End of Dbb =" 0
0 ”, Mb =“ 000 ”, and Db =“ 00000 ”
100000000 "", the margin bit is "00"
1 ”is prohibited (Minh =“ 001 ”).

In FIG. 2, the frame sync conversion circuit 1
Reference numeral 5 shows that after converting the pseudo frame sync signal S'f into the regular 24-bit frame sync signal Sf of the sequentially input 14-bit data on the basis of the frame sync timing (not shown), the other 14-bit data remains unchanged. It is supplied to the P / S register 16. 24-bit parallel in / serial out (P / S) register 16
Outputs serially 14-bit data (24-bit data only for the frame sync signal Sf) and 3-bit data (margin bit) alternately based on a channel bit clock of 4.3218 MHz.

The serial signal output at a speed of 4.3218 Mbps is NRZI-modulated by the NRZI circuit 17, and then, as an EFM signal, for example, a rotary transformer, a recording amplifier via a recording amplifier, or a laser diode (both not shown). It is supplied and digitally recorded on a CD. Further, the DSV integration circuit 60 to which the EFM signal is supplied integrates the DC component of the EFM signal in units of 17 channel bits, and outputs a 3-bit control signal to the margin bit generation circuit 40 based on the accumulated DSV.
For example, when the cumulative DSV has a positive polarity, "001" that commands a decrease "-" of the cumulative DSV, and "010" that commands a balanced "0" of the cumulative DSV when the cumulative DSV is zero,
Further, when the cumulative DSV has a negative polarity, "100" instructing the increase "+" of the cumulative DSV is output as the control signal.

Next, the margin bit generating circuit 40 shown in FIG. 1 will be described.

The margin bit generation circuit 40 has four types of margin bits “100”, “010”, “001”,
The optimum margin bit of "000" is output. The optimum margin bit is two 14-bit data Db.
And Dp are connected by this margin bit,
The EFM3T to 11T rules are established also at the connection points, and the margin bits are selected so as to prevent the erroneous occurrence of the frame sync signal and bring the cumulative DSV of the EFM signal as close to zero as possible.

The margin bit generation circuit 40 (FIG. 1) of the modulation circuit (FIG. 2) according to the present invention is different from the conventional example in which four kinds of margin bits are individually tested and the optimum margin bit is determined and output from the result. However, it is configured to uniquely output the optimum margin bit corresponding to the situation such as the bit pattern of two 14-bit data and the accumulated DSV, and the input signal is as follows.

First, the prohibition margin bit discriminating circuit 20.
The 4-bit inhibition signal is input from. The prohibition signal is EF
If there is a margin bit that cannot be inserted between the two 14-bit data Db and Dp because it violates the M3T to 11T rule or when the frame sync signal is erroneously generated, the bit corresponding to the margin bit is set to "1". Indicates that the use is prohibited. For example, when the first and third margin bits of the four types of margin bits “100”, “010”, “001”, and “000” are prohibited from use, the 4-bit prohibition signal becomes “1010”.

Secondly, the cumulative DS from the DSV integration circuit 60 is
A 3-bit control signal corresponding to V is input. In the 3-bit control signal, the desirable control direction of the cumulative DSV is increasing “+”, balanced “0”, and decreasing “−” in order from the upper bit.
It means that. Therefore, cumulative DSV> 0
In the case of, the control signal is set to “001” to instruct the decrease of the cumulative DSV, and when the cumulative DSV <0, the control signal is set to “100” to instruct the increase of the cumulative DSV, and when the cumulative DSV = 0, This control signal is set to "010" to instruct not to increase or decrease the cumulative DSV as much as possible.

As the third and fourth input signals, a 5-bit 14NWD signal and a 1-bit CWLL signal are input.

FIG. 4 is a diagram showing an example of NRZI waveforms of two 14-bit data Db and Dp combined by margin bits.

The amount of change in the cumulative DSV when the margin bit is added to the previous 14-bit data Db, that is, the DC component of the margin bit (hereinafter referred to as the DSV of the margin bit) is the signal of the NRZI waveform at the start of the margin bit. The case where the level (hereinafter, referred to as CWLL) is the low level (= "0") is shown as a reference. That is, FIG.
As shown in (A) to (D), the first margin bit "1"
The DSV of 00 "is +3, and the second margin bit is" 010 "
Has a DSV of +1 and the third margin bit “001” has a DSV of
V is -1, and the DSV of the fourth margin bit "000"
Is -3. When CWLL = "1" (high level), the DSV values of these margin bits have opposite signs.

Similarly, the amount of change in cumulative DSV when 14-bit data Dp is added, that is, DC of 14-bit data Dp
The component (hereinafter, referred to as 14NWD) is represented based on the case where the signal level of the NRZI waveform at the start of the 14-bit data Dp is low level. That is, the 14-bit data Dp (= “001001000001” shown in FIG.
00 ″) has a 14NWD of −2.

Change in cumulative DSV when the next 14-bit data Dp is concatenated by using 14-bit data Db with 3-bit margin bits (hereinafter referred to as 17NWD)
Is the value obtained by subtracting 14NWD from the DSV of the margin bit in the case of the first to third margin bits, and D of the margin bit in the case of the fourth margin bit “000”.
It is the sum of SV and 14NWD.

FIG. 5 is a nomograph for obtaining 17NWD from 14NWD when CWLL = "0" (low level).
FIG. 6 shows 14NWD to 17N when CWLL = "1".
It is a nomograph which calculates WD.

(A), (B), (C), (D) in FIG.
Indicates that when 14-bit data Dp is 14NWD = -2 (FIG. 4), four types of margin bits “1” to be inserted are inserted.
17NWD for "00", "010", "001", and "000" are shown, respectively.

In FIG. 5 (CWLL = 0), for example,
Consider the case where the 14NWD of the next 14-bit data Dp is 3 or more. First, if the cumulative DSV up to the present is zero or negative, the next 17NWD is set to zero or positive, and the cumulative DV
I want to increase SV and bring cumulative DSV closer to zero. 14N
In the case of WD ≧ 3, the margin bit that enables 17NWD ≧ 0 is only “000”, which is the first priority. If the first priority margin bit "000" cannot be inserted due to the EFM3T to 11T rules or the exceptional prohibition rule, the second best margin bit "100" is given second priority and the margin bit "010" is given third priority. If the margin bit “001” has the fourth priority, CWLL =
The optimum margin bit in the case of 0 and 14 NWD ≧ 3 can be uniquely determined. That is, it is not necessary to individually test the four types of margin bits as in the conventional case.

Similarly, in the case of 14 NWD ≧ 3, if the cumulative DSV up to the present is positive, the next 17 NWD is set to be negative,
I want to reduce the cumulative DSV. In this case, the priority order of the margin bits is “010”, “001”, “100”,
The optimum margin bit can be uniquely determined by setting the order of "000".

Similarly, 14NWD = 2, 14NWD =
For each of the cases of 1, 14 NWD = 0 and 14 NWD ≦ −1, the priority of four types of margin bits is logically determined.

Similarly, in the case of CWLL = "1" (high level) shown in FIG. 6, the next 14-bit data D
14NWD of p is +3 or more, +2, +1, 0 and -1
The priority of margin bits is determined for each of the following five cases. However, as is clear by comparing FIG. 5 showing the case of CWLL = “0” and FIG. 6 showing the case of CWLL = “1”, both flags are in the x-axis (14NWD).
6), the graph of FIG. 6 becomes the same as that of FIG. 5 by reversing the sign of the y-axis (axis indicating 17NWD) of FIG. That is, when CWLL = "1", the 3-bit control signal is converted to "001" (= decrease command) for "100" (= increase command of accumulated DSV) and to "100" for "001". As a result, the optimum margin bit determination algorithm when CWLL = “0” is set to CWLL.
It can be applied as it is to the case of "1".

The operation of margin bit generating circuit 40 according to the present invention shown in FIG. 1 will be described.

Reference numeral 41 is a decoder for converting a 3-bit control signal using the CBLL signal as a gate signal so that the margin bit determination algorithm in the case of CWLL = "0" can be shared even in the case of CWLL = "1". The truth table is shown in FIG.

42 is represented by a 5-bit two's complement number 14
This is a decoder for converting NWD into a 4-bit signal showing the above-mentioned five cases, and a truth table thereof is shown in FIG. 7 (B).

Reference numeral 43 is a prohibition margin bit discriminating circuit 20.
PLA pre-programmed to output the optimum margin bit 44 with the 4-bit inhibit signal supplied from the controller, the 3-bit control signal supplied from the decoder 41, and the 4-bit signal supplied from the decoder 42 as inputs. (Programmable logic array). The truth table programmed in the PLA 43 is shown in FIGS.
Here, FIGS. 8A and 8B are truth tables of 52 terms in the case of CWLL = “0”, and FIGS. 8C and 8D are C.
It is a truth table of 52 terms in the case of WLL = "1".

As described above, since the same truth table can be shared by the conversion using the decoder 41 in the case of CWLL = "0" and the case of CWLL = "1", the PLA4
What is actually programmed into 3 is a 52-term truth table.

In the figure, "1" stands for (flag),
“0” indicates failure. Further, "x" may be either established or unestablished. For example, a truth table (Fig. 8
The meanings of the four lines (terms) shown at the top of (A)) are as follows.

CWLL = 0 and control signal = “xx0”
If (at least not a decrease instruction), 14NWD ≧
In the case of 3, the priority order of the margin bits is “000”, “100”, “010”, “00” in descending order of priority.
1 ", that is, the first priority margin bit" 00 "
If "0" is not prohibited (prohibition signal = "xxxx"
0 "), this is output as the optimum margin bit. If the first priority margin bit" 000 "is prohibited and the second priority margin bit" 100 "is not prohibited (prohibition signal =" xx01 "). , The second priority margin bit “100” is output as the optimum margin bit in this case, unless both the first and second priority margin bits are prohibited and the third priority margin bit is not prohibited (prohibition). Signal = “x011”), the third priority margin bit “010” is output as the optimum margin bit in this case When all the first to third priority margin bits are prohibited (prohibition signal = “011”)
1 "), and the fourth priority margin bit" 001 "is output.

In this way, the optimum margin bit 44 logically determined by the PLA 43 is output without actually testing each margin bit.

Although the modulation circuit conforming to the CD system has been described above, the technical idea of the present invention is that the input m-bit code is converted into an n (where n> m) channel bit pattern and the n-channel bit pattern Can be applied to one of a plurality of types of margin bits to limit the longest and shortest recording wavelengths and can be applied to a general modulation circuit that suppresses the low-frequency component of the recording waveform.

[0118]

As described above, according to the modulation circuit having the margin bit generation circuit of the present invention, it is possible to perform simple operation without testing individual margin bits in parallel or in time division as in the conventional case. Since the optimum margin bit can be output at high speed and uniquely by using the logic circuit, the circuit scale can be reduced and the integrated circuit can be easily formed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a margin bit generation circuit 40 according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a modulation circuit according to the present invention to which the same margin bit generation circuit is applied.

FIG. 3 is an explanatory diagram of prohibited margin bit discrimination.

FIG. 4 is an explanatory diagram of an EFM signal waveform when two 14-bit data are connected by a margin bit.

FIG. 5: From 14NWD to 1 when CWLL is “0”
It is a nomogram which calculates | requires 7NWD.

FIG. 6 shows 14 NWD to 17 when CWLL is “1”
It is a nomograph which calculates NWD.

FIG. 7 is a diagram showing a truth table of decoders 41 and 42.

8 is a diagram showing a truth table of the programmable logic array 43. FIG.

FIG. 9 is a diagram showing a signal format of a CD system.

FIG. 10 is an explanatory diagram of sampled values and EFM signals.

FIG. 11 is a block diagram showing an example of a conventional modulation circuit.

[Explanation of symbols]

11 EFMROM 12 Sub Code Sync Addition Circuit 13 Pseudo Frame Sync Addition Circuit 14 Register 15 Frame Sync Conversion Circuit 16 Parallel In / Serial Out (P / S) Register 17 NRZI Modulation Circuit 18 EFM Signal 20 Inhibition Margin Bit Discrimination Circuit 40 Margin Bit Generation Circuits 41 and 42 Decoder 43 Programmable logic array (PLA) 44 Optimal margin bit 60 Digital summation (DSV) integrating circuit

[Procedure amendment]

[Submission date] June 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 13A is a diagram showing an outline of a signal format of the CD system, and 8-14 is a modulation system.
A conversion (hereinafter referred to as EFM) is used.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

FIG. 13B is a diagram showing a frame structure of the CD system.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

Here, for each symbol input to the modulation circuit, for example, referring to a look-up table ROM,
The number of "0" s between "1" and "1" is converted into channel bit patterns of 2 or more and 10 or less, respectively.
Further, the channel bit pattern of the frame synchronization signal Sf is "10000000000100000000001".
0 ", the margin bit pattern is" 000 ",
One of “001”, “010” and “100” is selected. Furthermore, one subcoding frame is 9
The sub-code sync signal S ₀ (= “0010
0000000001 "), S ₁ (=" 0000000
0010010 ″) is added (see FIG. 13C).

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

FIG. 14 shows an example of the sampled value E
It is a figure which shows the channel bit pattern after FM, and DSV (digital sum variation).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Thus, any channel bit "1"
Since 2 to 10 channel bits "0" are present between the next channel bit "1" and the next channel bit "1", the high level or low level duration (recording wavelength) of the NRZI recording waveform is always 3T or more and 11T or more. The following is obtained (see FIG. 14). That is, in this case, the shortest recording wavelength is 3T and the longest recording wavelength is 11T. However, T is the channel clock 4.
It is one cycle of 3218 MHz.
It is called the T-11T rule.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

The DSV when "010" is inserted as a margin bit is shown by a solid line, and the DSV when "000" is inserted is shown by a dotted line in FIG.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

FIG. 15 is a block diagram of the modulation circuit disclosed in JP-A-1-319178.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

The prohibition margin bit discriminating circuit 20 selects one of the input signals Dp, Db, Mb and Dbb shown in FIGS.
A bit test shown by hatching is performed, and the previous 14-bit data Db and the current 14-bit data are tested according to the result.
The margin bit Minh which should not be used for connection with the bit data Dp is discriminated, and the 4-bit inhibition signal Sinh is supplied to the margin bit generation circuit 40.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0073

[Correction method] Change

[Correction content]

In FIG. 3, an algorithm for discriminating the prohibited margin bit Minh according to the EFM3T to 11T rules is as follows.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0078

[Correction method] Change

[Correction content]

In FIG. 4, although the EFM3T to 11T rules are not violated, the judgment of the margin bit prohibited in order to prevent the erroneous occurrence of the frame sync signal, that is, the prohibition margin bit by the exceptional prohibition rule is as follows. is there.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0099

[Correction method] Change

[Correction content]

FIG. 5 is a diagram showing an example of an NRZI waveform of two 14-bit data Db and Dp combined by margin bits.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction content]

The amount of change in the cumulative DSV when the margin bit is added to the previous 14-bit data Db, that is, the DC component of the margin bit (hereinafter referred to as the DSV of the margin bit) is the signal of the NRZI waveform at the start of the margin bit. The case where the level (hereinafter, referred to as CWLL) is the low level (= "0") is shown as a reference. That is, FIG.
As shown in (A) to (D), the first margin bit "1"
The DSV of 00 "is +3, and the second margin bit is" 010 "
Has a DSV of +1 and the third margin bit “001” has a DSV of
V is -1, and the DSV of the fourth margin bit "000"
Is -3. When CWLL = "1" (high level), the DSV values of these margin bits have opposite signs.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0101

[Correction method] Change

[Correction content]

Similarly, the amount of change in cumulative DSV when 14-bit data Dp is added, that is, DC of 14-bit data Dp
The component (hereinafter, referred to as 14NWD) is represented based on the case where the signal level of the NRZI waveform at the start of the 14-bit data Dp is low level. That is, the 14-bit data Dp (= “001001000001” shown in FIG.
00 ″) has a 14NWD of −2.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0103

[Correction method] Change

[Correction content]

FIG. 6 is a nomograph for obtaining 17NWD from 14NWD when CWLL = "0" (low level).
FIG. 7 shows 14NWD to 17N when CWLL = "1".
It is a nomograph which calculates WD.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0104

[Correction method] Change

[Correction content]

(A), (B), (C), (D) in FIG.
Indicates that when 14-bit data Dp is 14NWD = -2 (FIG. 5), four types of margin bits “1” to be inserted are
17NWD for "00", "010", "001", and "000" are shown, respectively.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0105

[Correction method] Change

[Correction content]

In FIG. 6 (CWLL = 0), for example,
Consider the case where the 14NWD of the next 14-bit data Dp is 3 or more. First, if the cumulative DSV up to the present is zero or negative, the next 17NWD is set to zero or positive, and the cumulative DV
I want to increase SV and bring cumulative DSV closer to zero. 14N
In the case of WD ≧ 3, the margin bit that enables 17NWD ≧ 0 is only “000”, which is the first priority. If the first priority margin bit "000" cannot be inserted due to the EFM3T to 11T rules or the exceptional prohibition rule, the second best margin bit "100" is given second priority and the margin bit "010" is given third priority. If the margin bit “001” has the fourth priority, CWLL =
The optimum margin bit in the case of 0 and 14 NWD ≧ 3 can be uniquely determined. That is, it is not necessary to individually test the four types of margin bits as in the conventional case.

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0108

[Correction method] Change

[Correction content]

Similarly, in the case of CWLL = "1" (high level) shown in FIG. 7, the next 14-bit data D
14NWD of p is +3 or more, +2, +1, 0 and -1
The priority of margin bits is determined for each of the following five cases. However, as is clear by comparing FIG. 6 showing the case of CWLL = “0” and FIG. 7 showing the case of CWLL = “1”, both flags are determined to be in the x-axis (14NWD).
7), the graph of FIG. 7 becomes the same as FIG. 5 by reversing the sign of the y-axis (axis indicating 17NWD) of FIG. That is, when CWLL = "1", the 3-bit control signal is converted to "001" (= decrease command) for "100" (= increase command of accumulated DSV) and to "100" for "001". As a result, the optimum margin bit determination algorithm when CWLL = “0” is set to CWLL.
It can be applied as it is to the case of "1".

[Procedure 18]

[Document name to be amended] Statement

[Correction target item name] 0110

[Correction method] Change

[Correction content]

Reference numeral 41 is a decoder for converting a 3-bit control signal using the CBLL signal as a gate signal so that the margin bit determination algorithm in the case of CWLL = "0" can be shared even in the case of CWLL = "1". The truth table is shown in FIG.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0111

[Correction method] Change

[Correction content]

42 is represented by a 5-bit two's complement number 14
It is a decoder for converting NWD into a 4-bit signal showing the above-mentioned five cases, and a truth table thereof is shown in FIG.

[Procedure amendment 20]

[Document name to be amended] Statement

[Name of item to be corrected] 0112

[Correction method] Change

[Correction content]

Reference numeral 43 is a prohibition margin bit discriminating circuit 20.
PLA pre-programmed to output the optimum margin bit 44 with the 4-bit inhibit signal supplied from the controller, the 3-bit control signal supplied from the decoder 41, and the 4-bit signal supplied from the decoder 42 as inputs. (Programmable logic array). The truth table programmed in the PLA 43 is shown in FIGS. Here, FIGS. 9 and 10 are truth tables of 52 terms when CWLL = “0”, and FIGS. 11 and 12 are CWLL = “1”.
It is a truth table of 52 terms in the case of.

[Procedure correction 21]

[Document name to be amended] Statement

[Correction target item name] 0114

[Correction method] Change

[Correction content]

In the figure, "1" stands for (flag),
“0” indicates failure. Further, "x" may be either established or unestablished. For example, the meanings of the four rows (terms) shown at the top of the truth table (FIG. 9) are as follows. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 20, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a margin bit generation circuit 40 according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a modulation circuit according to the present invention to which the same margin bit generation circuit is applied.

FIG. 3 is an explanatory diagram of prohibited margin bit discrimination.

FIG. 4 is an explanatory diagram of prohibited margin bit discrimination.

FIG. 5 is an explanatory diagram of an EFM signal waveform when two 14-bit data are connected by a margin bit.

FIG. 6 shows 14 NWD to 1 when CWLL is “0”
It is a nomogram which calculates | requires 7NWD.

FIG. 7: From 14 NWD to 17 when CWLL is “1”
It is a nomograph which calculates NWD.

FIG. 8 is a diagram showing a truth table of decoders 41 and 42.

9 is a diagram showing a truth table of the programmable logic array 43. FIG.

10 is a diagram showing a truth table of the programmable logic array 43. FIG.

11 is a diagram showing a truth table of the programmable logic array 43. FIG.

FIG. 12 is a diagram showing a truth table of the programmable logic array 43.

FIG. 13 is a diagram showing a signal format of a CD system.

FIG. 14 is an explanatory diagram of sampled values and EFM signals.

FIG. 15 is a block diagram showing an example of a conventional modulation circuit.

[Explanation of Codes] 11 EFMROM 12 Subcode Sync Addition Circuit 13 Pseudo Frame Sync Addition Circuit 14 Register 15 Frame Sync Conversion Circuit 16 Parallel In / Serial Out (P / S) Register 17 NRZI Modulation Circuit 18 EFM Signal 20 Inhibition Margin Bit Discrimination Circuit 40 Margin bit generating circuit 41, 42 Decoder 43 Programmable logic array (PLA) 44 Optimal margin bit 60 Digital summation (DSV) integrating circuit

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 8]

[Figure 5]

[Figure 6]

[Figure 7]

[Fig. 13]

[Figure 9]

[Figure 10]

FIG. 11

[Fig. 12]

FIG. 14

FIG. 15

Claims (1)

[Claims] 1. An n-bit input m-bit code sequence
(Where n> m), the n-channel bit patterns are converted, and the n-channel bit patterns are combined by one of a plurality of types of margin bits to limit the longest and shortest recording wavelengths and to reduce the recording waveform. In the modulation circuit that suppresses the band component, the signal related to the above margin bit that is prohibited from being used,
A signal related to the final recording waveform level of the n-channel bit pattern that precedes this margin bit, a control signal related to cumulative digital summation (hereinafter referred to as DSV), and an n-channel that follows this margin bit. A modulation circuit comprising a margin bit generating means for inputting a signal relating to a DSV of a bit pattern and uniquely outputting an optimum one of the plurality of types of margin bits without a test.