JPH0611108B2 - Semiconductor circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique particularly effective when applied to a logic circuit and a memory circuit, for example, a semiconductor circuit device that outputs first and second logic states, in particular. The present invention relates to a technique effectively used for a level conversion circuit that converts a signal of a MOS level into a signal of a different amplitude such as an ECL level and outputs the signal.

[Background technology]

Conventionally, in a CMOS integrated circuit, a circuit for converting an internal MOS level signal such as 0 to -5V into an ECL level signal such as -0.9 to -1.7V and outputting the signal is shown in FIG. A circuit as shown in (1) has been proposed by Intel (Electronics / February 10, 1982 160-
163). This level conversion circuit has the advantages of low current consumption and high speed.

However, according to a study made by the present inventor, in this circuit, when the output of the CMOS inverter IV in the preceding stage is between -5V and -0.6V, the emitter
The follower EF outputs a low level (about -1.7V),
When the output of the inverter IV is between -0.6 and 0 V, the emitter follower EF has a high level (about -0.9).
V) is output. On the other hand, the output of the inverter IV at the preceding stage changes at substantially the same speed when changing from the low level to the high level and when changing from the high level to the low level.

Therefore, when the input signal of the CMOS inverter IV changes and the output of the inverter IV changes from the low level to the high level and when the output of the inverter IV changes from the high level to the low level, the propagation delay of the signal in the level conversion circuit. It turns out that the time will be different.

Therefore, the P-MOS that constitutes the CMOS inverter IV
The N / MOS channel W / L ratio is set to, for example, 5: 1 to bring the logic threshold to the higher level side, and the signal delay time between the rising edge and the falling edge of the output signal is increased. The present inventor has considered to alleviate the imbalance of However, even in this case, it has been found that the fall time of the output signal of the circuit is about 2 ns earlier than the rise time.

Therefore, if such a level conversion circuit is used in, for example, an output circuit of a CMOS memory, the memory access time is determined by the slower output signal in the output circuit, so that the speedup of the memory cannot be sufficiently achieved. It was made clear by the present inventors that there are points.

[Object of the Invention]

In a circuit that outputs the first and second logic states such as a level conversion circuit including a MOS inverter and an emitter follower, there is a need to eliminate the difference between the delay times of output signals and to shorten the delay time. It is another object of the present invention to improve the operation speed of the entire LSI such as a memory using this circuit.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, for example, a switch transistor is provided between the input signal line of the circuit and one of the power supply voltage terminals, and the switch transistor is turned on until just before the operating potential propagates, thereby outputting in advance. Can be fixed to the logic state with the longer delay time, which speeds up the change to the logic state with the longer delay time and reduces the difference in delay time between the changes to the first and second logic states. The object is to be achieved so that the object can be eliminated.

The present invention will be specifically described below with reference to the drawings.

〔Example〕

FIG. 2 shows an embodiment in which the present invention is applied to a level conversion circuit for converting a MOS level to an ECL level.

This level conversion circuit, like the circuit of FIG.
It consists of a MOS inverter IV and an emitter follower EF. The CMOS inverter IV is a P-channel type MOSFET Q ₁ and an N-channel type MOSFE connected in series between the ground potential of the circuit and the power supply voltage V _EE (−5V).
It is composed of TQ ₂ and. The output voltage of the CMOS inverter IV is supplied to the base of the NPN bipolar transistor Tr which constitutes the emitter follower EF. The collector of the transistor Tr is connected to the ground potential of the circuit, the emitter is connected to the power supply voltage such as -2V through the resistor R, and the level-converted output V _ECL is taken out from the emitter of the transistor Tr. There is.

Further, in this embodiment, although not particularly limited between the input signal line 1 of the inverter IV and the power supply voltage V _EE ,
An N-channel type switch MOSFET Q ₃ is connected. And the gate of this MOSFET Q ₃
Control pulse P output from a pulse generation circuit (not shown)
_C is supplied, and the control pulse P _C causes the MOSFE
TQ ₃ is adapted to be turned on and off.

When the level conversion circuit of the above embodiment is used as an output circuit of a CMOS memory and an ECL level signal is output, a sense output from a sense amplifier (readout circuit) of the memory is input to the input signal line 1 to the inverter IV. Is made to come in as an input signal.

In this case, from the start of address selection based on a control signal such as an address signal or a write enable signal supplied to the memory from the outside until a signal is input from the sense amplifier to the inverter IV in the level conversion circuit. Control pulse P _C that is made to be at a high level only during
Is formed and is applied to the gate of the MOSFET Q ₃ .

Then, the MOSFET Q ₃ is turned on by the control pulse P _C , and the MOSFET Q ₁ , which constitutes the inverter IV,
A voltage of V _EE level is applied to the gate of Q ₂ . Therefore, the output of the inverter IV is set to a high level (0V), and the transistor T that constitutes the emitter follower EF.
When r is turned on, the output of the emitter follower EF is set to a potential such as -0.6 V which is lower than the base potential of the transistor Tr by V _BE .

As a result, the output of the emitter follower EF, that is, the output of the level conversion circuit is sense output (operating potential) from the sense amplifier to the circuit by the control pulse P _C.
It will be fixed to high level (-0.6V) in advance until is input.

Therefore, in the above embodiment, as shown in FIG. 3, the control pulse P _C falls to the low level and the MOSFE
Input signal (sense output) V _{IN after} TQ ₃ is turned off
Is changed, the output signal V _{ECL of the} circuit changes correspondingly quickly. That is, the output V _ECL of this circuit, as described above, the control pulse P _C, are forced to a high level just before the incoming input signal V _IN, the control pulse P _C falls, Although the level is slightly lowered, it immediately follows the change of the input signal V _IN and changes.

Here, when the input signal V _IN changes from low level to high level, the output of the inverter IV changes from high to low, and the output V _ECL of the emitter follower EF also changes to low level. The change is inherently rapid, as described in the circuit of FIG. On the other hand, when the input signal V _IN changes from high level to low level, the output of the inverter IV changes from low to high, and the output V _ECL becomes high level. Then,
Before the input signal _IN enters the circuit, the transistor Tr is turned on by the control pulse P _C , and the output V _ECL is fixed at the high level. Therefore, the output level starts to drop due to the fall of the control pulse P _C. Also, the input signal V _IN changes before it completely drops. Therefore, the output V _ECL immediately changes following the change of the input signal V _IN and is brought to a predetermined high level state such as −0.6V.

In the conventional circuit as shown in FIG. 1, the input signal V
_{When IN} is changed from high level to low level, Fig. 3
As indicated by the broken line in (c), the change of the output V _{ECL to} the high level is delayed by 2 ns or more from the change to the low level.
However, in the circuit of the embodiment, the change of the output V _{ECL to} the high level has the same delay time as the change to the low level. Therefore, there is no difference between the delay time when the output V _ECL is changed to the low level and the delay time when the output V _ECL is changed to the high level, and the later delay time in the level conversion circuit is aligned with the earlier delay time. be able to.

As a result, the access time in the CMOS memory using such a level conversion circuit as an output circuit is shortened by 2 ns or more, and the read speed can be increased.

It should be noted that, in the above embodiment, the MO which constitutes the inverter IV
N between the gates of the SFETs Q ₁ and Q ₂ and the power supply voltage V _EE
Although the switch MOSFET Q ₃ of channel shaped is provided, that the use of the P-channel type MOSFET in place of MOSFET Q _3, may be turned on by applying the control pulse _{P C} and the negative-phase pulse Needless to say. In the embodiment, the inverter IV is C
Although it has a MOS structure, it is an N-channel drive M
The present invention can also be applied to a level conversion circuit composed of an inverter composed of an OSFET and a load MOSFET and an emitter follower.

Further, in the above-described embodiment, the configuration in which the output from the sense amplifier is directly supplied to the inverter IV has been described, but a level such that a plurality of stages of inverters are connected in front of the inverter IV is described. It can also be applied to a conversion circuit. In this case, the switch MOSFET Q ₃ may be connected, for example, between the gate of the MOSFET forming the final stage inverter and the power supply voltage V _EE .

[Effect]

In a circuit that outputs a first logic state (high level) and a second logic state (low level) like a level conversion circuit including a MOS inverter and an emitter follower,
A switch transistor is provided between the input signal line of the circuit and one of the power supply voltage terminals, and this switch transistor is turned on until just before the operating potential propagates, so that the output has a long delay time in advance. Since it can be fixed to one of the logic states, the change to the logic state with the larger output delay time is accelerated to match the change with the smaller delay time, which eliminates the difference in delay time and delay. The time gets shorter. Further, there is an effect that the operation speed in an LSI such as a memory using this circuit as an output circuit can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. Nor.

[Field of application]

In the above description, as an example, the signal of the MOS level is EC
The level conversion circuit for converting to an L level signal and the case where the level conversion circuit is used for the output circuit of the memory have been described.
The present invention can be applied to a circuit for converting between the OS level and the TTL level, all other circuits having a significantly different rise time and fall time, and a logic LSI other than a memory.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional level conversion circuit from a MOS level to an ECL level, FIG. 2 is a circuit diagram showing an embodiment of a level conversion circuit to which the present invention is applied, and FIG. 6 is a timing chart showing timings of input / output signals and control pulses in the circuit. IV ... Inverter, EF ... Emitter follower, T
r ...... bipolar transistor, _{Q 3} ...... switch transistor (MOSFET), V _IN ...... input signal, V _ECL
…… Output signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsumi Ogigami 1450, Kamisuihonmachi, Kodaira-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (56) Reference JP 58-59629 (JP, A) 57-119946 (JP, U)

Claims (1)

[Claims] 1. A CMOS inverter for receiving a sense output from a sense amplifier of a memory as its input, and such a C inverter.
The emitter follower receiving the output of the MOS inverter receives the CMOS level signal from the inside, and receives the ECL signal.
An output circuit for forming an output signal of a level is configured, and a delay time when the output level of the emitter follower changes from a first level to a second level caused by a change of an input of the CMOS inverter, A semiconductor circuit device having a delay time longer than that at the time when the level changes from the second level to the first level, wherein the CMOS inverter includes a P-channel MOSFET having a large W / L ratio and a small W / L ratio. N channel MO
It has a high logic threshold by being composed of an SFET and a switch MOSFET forcing the output level of the emitter follower to the second level by the switch operation.
T is coupled to the CMOS inverter, and the switch MOSFE is activated by a control pulse whose output is started by the start of selection of a memory address and ended at the timing when the sense output is output from the sense amplifier.
A semiconductor circuit device, wherein T is switch-controlled.