JPH06110695A - Min-max arithmetic circuit for fuzzy inference - Google Patents

Abstract

PURPOSE:To provide the min-max arithmetic circuit for fuzzy inference realizing the improvement of arithmetic speed and the reduction of hardware amount. CONSTITUTION:In the min-max arithmetic circuit for fuzzy inference performing the min-max arithmetic processing of the grade of the operated input label on defined plural input labels by a membership function on respective plural input channels, a mean (10) arranging the order of input label evaluation according to the order of the grade of the operated input label.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention generates an output label grade by performing min-max operation on the input label grade generated in a fuzzy inference machine used for controlling various home appliances and vehicles. It relates to a min-max arithmetic circuit for fuzzy reasoning.

[0002]

2. Description of the Related Art Fuzzy control using fuzzy inference is being applied to a wide range of existing control such as control of various home appliances and vehicles. In the multi-fuzzy inference that forms the core of this fuzzy inference, first, the degree of matching (grade) between the multiple fuzzy concepts on the input side included in the antecedent part of the fuzzy rule and the facts indicated by the actual input data. Is calculated. A label is added to the plurality of fuzzy concepts on the input side in order to identify each other. Therefore, each fuzzy concept is also referred to as an input label. Corresponding to the rule about the grade of each input label calculated
By performing min-max operation, the output label grade for cutting off the membership function of the fuzzy concept (output label) on the output side included in the consequent part of each rule is calculated. Finally, defuzzification is performed, in which the deterministic output is obtained from the centroid of the membership function of each output label truncated by the corresponding grade.

In the above fuzzy inference machine for control, in order to receive a plurality of input data such as speed, pressure and temperature,
A plurality of input channels are provided, and a plurality of input labels are defined for each input channel. Further, a plurality of output channels are provided for outputting a plurality of output data regarding opening / closing of switches and opening of valves, and a plurality of output labels are defined in each output channel. Therefore, the total number of input label grades calculated is equal to the number of input labels per input channel × one input channel, and the amount of data to be subjected to the min-max calculation in the subsequent stage becomes considerably large.

Conventionally, the control based on the fuzzy inference as described above has been mainly applied to low-speed control of home electric appliances and the like, but it is required to be relatively complicated and high-speed such as vehicle running control and suspension control. In order to apply it to the technical field, it is necessary to dramatically reduce the conventional processing time, typically by about 3 digits. This reduction in calculation time is performed by the grade calculation for the input label, the calculation of the output label grade by the min-max calculation for this calculated grade group, and the membership of the output label truncated by the calculated grade. It is necessary to realize each stage of defuzzification by calculating the center of gravity of the function while maintaining harmony.

[0005]

Conventionally, the min-max operation for the grades of input labels is realized by a large number of magnitude comparisons with respect to the grades of a large number of input labels. A typical example of a system that realizes this size comparison by software processing is disclosed in Japanese Patent Application No. 4-10133, etc.
There is a problem that it is difficult to improve the calculation speed because it is necessary to repeat a large number of magnitude comparisons. A typical example of a system for realizing the above size comparison by a hardware circuit is Japanese Patent Application No. 2-1.
No. 59628, etc., it is necessary to execute a plurality of comparison operations with respect to the same input label, and it is difficult to increase the speed. In addition, the scale of this hardware circuit becomes large and the manufacturing cost is reduced. There is a problem that it becomes difficult.

Further, in a typical fuzzy inference,
Most of the input label grades subject to min-max operation are zero. For example, for each input channel, if we define each of the eight input label membership functions so that only the nearest neighbors intersect, then each input channel will output two input labels with a non-zero grade. To be done. That is, 70 to 80% of the grades of the input label subject to the min-max calculation are zero grades (hereinafter referred to as "zero grades"). The zero grade, which accounts for most of this, has a peculiarity different from other input label grades (hereinafter referred to as "non-zero grades") in that it does not substantially affect the min-max operation result. ing. However, in the conventional min-max operation, zero grade is processed in the same way as non-zero grade, so
A large amount of useless processing is included, which makes it more difficult to improve the calculation speed and reduce the hardware amount. Therefore, an object of the present invention is to provide a min-max arithmetic circuit for fuzzy inference that realizes an improvement in arithmetic speed and a reduction in hardware amount.

[0007]

SUMMARY OF THE INVENTION A fuzzy inference min-max operation circuit according to the present invention which solves the above-mentioned problems of the prior art is an input operation for a plurality of input labels defined for each of a plurality of input channels. Label grades that exceed a specified threshold (for example, those that are not zero) are rearranged according to the order of grade, along with the corresponding input channels and input label identifiers that are supplied simultaneously, and then rearranged. Output the subsequent input label grades in order from the smallest and with the corresponding identifier on the grade bus and label bus,
For a predetermined value or less (for example, zero), a rearrangement circuit for excluding the rearrangement and output according to a zero instruction signal indicating that is provided.

The min-max arithmetic circuit further defines a rule-corresponding bit string that indicates whether or not each input label of each input channel corresponds to all fuzzy rules used for this fuzzy inference with valid / invalid bits. A rule memory that holds and outputs at an address accessed by an identifier supplied at the time of rearrangement and output by the grade rearrangement circuit of the input label, and the maximum number of rules that can be included in each output label of each output channel, The same number is installed, and is validated only when the grade of the input label in the rearrangement corresponding to the valid bit appearing in the rule corresponding bit string read from the rule memory at the time of rearranging the input grade is equal to or more than a predetermined value. At the same time, the identifiers of the rearranged input labels and the rules read from the rule memory when the grades are output. The min operation unit that detects the first significant bit that appears in the corresponding bit string and generates a significant signal, and the same number of output labels of each output channel are installed and output from each corresponding min operation unit. A logical circuit having a max operation unit for outputting a logical sum of the signals for holding the grade of the input label being output from the rearrangement circuit, and the grade of the input label being output from the rearrangement circuit. And a grade holding circuit for holding the input label according to the holding command output from the logic circuit.

[0009]

According to the min-max operation circuit of fuzzy inference according to the present invention, first, a plurality of input labels defined for each of a plurality of input channels are operated, and corresponding to the grades of the input labels supplied in the operation order. Of the input label are rearranged by the rearrangement circuit in the order of the grade of the input label. When rearranging the identifier of this input label and its grade, the zero grade which occupies most of the grades of the input label of the min-max operation target is discarded. The rearranged input label grades are output in ascending order, along with the corresponding identifiers.

At the time of rearrangement and output by the rearrangement circuit, a rule-corresponding bit string indicating whether or not the input label corresponds to all the rules is read from the rule memory accessed by receiving the identifier at the address terminal, It is supplied to the logic circuit for min-max operation, which is installed in the same number as each output label of each output channel. The min operation part of each logic circuit is installed corresponding to each bit of the rule corresponding bit string read from the rule memory at the time of output of the rearranged input label grade, that is, corresponding to each rule. The significant bit which appears first as the corresponding bit, that is, which corresponds to the minimum grade output from the rearrangement circuit, is detected to generate a significant signal.

The max operation unit installed corresponding to each output label of each output channel uses the logical sum of significant signals output from each corresponding min operation unit as a holding command to hold the input label grade holding circuit. Output to. The grade holding circuit of the input label is installed corresponding to each max operation unit, for example. Therefore, hold the last significant signal output from each max operation unit, that is, the maximum one (max grade) of the minimum grades (min grades) included in multiple rules in each output label. The command is output to the grade holding circuit.

Since the zero grade is discarded during the rearrangement of the input label grades, the above-mentioned function of each min operation unit is provided with the rule read from the rule memory at the time of rearrangement by the input label grade rearrangement circuit. It is enabled only when the grade of the input label in the rearrangement corresponding to the valid bit appearing in the corresponding bit string is not all zero, and in other cases, that is, the valid bit appearing in the rule corresponding bit string read at the time of rearranging If the grade of the corresponding input label is zero for one or more of them, or if no valid bit appears in the read rule-corresponding bit string, it is invalidated.

[0013]

FIG. 1 is a block diagram showing the construction of a min-max arithmetic circuit for fuzzy inference according to an embodiment of the present invention. 10 is a rearrangement circuit of an input label grade and a corresponding identifier (hereinafter, "Input Label Grade Rearrangement Circuit"
20) is a rule ROM, 30 is a grade holding register group of input labels, 40 is a logic circuit group, 51 is a grade bus, 52 is an identifier bus, and 53 is a valid flag signal line. For convenience of illustration, the rear-stage portion including the rule ROM 20, the input label grade holding register group 30, and the logic circuit group 40 is shown for only one output channel. That is, in the latter part, the number equal to the total number of output channels, for example, the total number of output channels is 10
If so, only 10 sets of the same number will be installed.

On the grade bus 51, input label grades are arranged in the order of arrangement of a plurality of input channels in a grade arithmetic circuit in the preceding stage (not shown) and in the order of arrangement of a plurality of input labels defined for each input channel. The calculation is executed, and the grade of each input label of each input channel appears in the execution order of this calculation.
Assuming a typical system where the total number of input channels is 8 and the total number of input labels in each input channel is 9, a total of 72 input label grades appear on the grade bus 51. In the following, for convenience of explanation, the total number of input channels is 8, and the total number of input labels defined for each input channel is 9.

The input channel / input label identifier corresponding to the grade of the input label appearing on the grade bus 51 is the label bus 5 at the same time as the grade of this input label.
Appears on 2. The identifier of each input channel / input label may be represented by a combination of the serial number of the input channel and the serial number of the input label included in this input channel, such as the third input label of the second input channel, or , May be represented by serial numbers for the 72 input labels that are arranged in the arrangement order of the input channels and the arrangement order of the input labels defined for each channel. In the following, the identifiers of the input channels / input labels that indicate which input label of which input channel the corresponding input label grade corresponds to are simply referred to as identifiers.

In a typical fuzzy inference, most of the grades of the input label appearing on the grade bus 51 are zero. For example, for each input channel, if we define each of the eight input label membership functions so that only the nearest neighbors intersect, then each input channel will output two non-zero input label grades. It That is, a total of 7 for 9 input channels in total
Of the two input label grades, only 18 are not zero, and the remaining 54 are zero grades (hereinafter referred to as "zero grades"). In this min-max arithmetic circuit, the processing time and the circuit scale are reduced by executing exceptional processing for zero grade, which accounts for most of the input label grade. As a part of this, from the grade calculation circuit of the input label at the preceding stage (not shown), a valid flag indicating that the calculation result is not zero grade is output to the valid flag signal line 53 if the grade is zero grade. It

The input label grade that includes a large number of zero grades that appear on the grade bus 51 is first determined in the input label grade rearrangement circuit 10 according to the order of zero grade discard and non-zero grade size. And rearrangement is performed. The rearrangement circuit 10 is basically composed of two series of data register groups arranged in a column, the data register group of one series holds the input label grade, and the data register group of the other series is held. Holds the identifier of the corresponding input label.

The discarding of the zero grade and the rearrangement of the grades of the input label according to the order of the size of the non-zero grade are performed on the grade bus 51 only when the valid flag appears on the valid flag signal line 53. This is realized by holding the appearing grade in one of the data register groups of each system together with the corresponding identifier while selecting the holding destination according to the magnitude relationship. Such an input label grade rearrangement circuit 10 can be realized based on an appropriate method. For example, the graded rearrangement circuit 10 disclosed in the “data sorting circuit” filed by the present applicant before and after this application can be implemented. If used, it is particularly suitable in terms of shortening the processing time.

When the rearrangement by the input label grade rearrangement circuit 10 is completed, an initial value of zero is set for all of the register groups 30 holding the input label grade, and then a continuous supply from the address counter 54 is performed. In accordance with the address, the grades of the rearranged input labels are output from the input label grade rearrangement circuit 10 to the grade bus 51 in ascending order. At the same time, the corresponding identifier is output from the input label grade rearrangement circuit 10 onto the identifier bus 52. The identifier output on the identifier bus 20 becomes an address supplied to the address input terminal of the rule ROM 20, and from the rule ROM 20, each input label of each input channel held at this address and this fuzzy inference are set. A bit string (hereinafter, referred to as “rule-corresponding bit string”) indicating presence / absence of correspondence with all the fuzzy rules that are present by valid / invalid bits is output to the logic circuit 40.

As shown in FIG. 2, the data held in the rule ROM 20 includes data indicating which input channel each rule (fuzzy rule) including an arbitrary output label of an arbitrary output channel in the consequent part. Whether or not the input label is included as an antecedent part is displayed as a valid bit when it is included, and as an invalid bit when it is not included, and is displayed by a bit string arranged in a predetermined order over all input labels of all input channels. .

For example, If In.Ch 0 = L 0 & In.Ch1 = L 1 & In.Ch7 = L 7
 then Out.Ch 0 = L0 Output channel 0 (Out.Ch  0) output
Label 0 (L Defined as rule (1) for 0)
Be present. In this case, as shown in FIG.
All input labels included in
Force channel 0 (In.Ch  Input label of 0) 0 (L 0)
And input channel 1 (In.Ch 1) Input label 1 (L
 1) and input channel 7 (In.Ch Input label 7 of 7)
(L A valid bit (“1”) is set in 7) (see FIG. 2).
(Circle inside), all other input channels, all inputs
An invalid bit (“0”) is set in the label.

Further, the output label 0 of the output channel 0
Another rule about If In.Ch 1 = L 0 then Out.Ch 0 = L It is assumed that rule (2) of 0 is defined. this
If this is the input label included in rule (2),
Input channel 1 (In.Ch  Input label of 1) 0 (L
A valid bit (“1”) is set only in 0), and
All input labels of all other input channels are invalid.
("0") is set.

As shown in FIG. 2, by arranging the above data in a predetermined order over each rule included in each output label of each output channel, a matrix form showing whether or not there is a correspondence relationship between the output label and the input label is formed. A rule data group is constructed. This matrix of data enables / disables the correspondence between each input label of each input channel and all fuzzy rules set for this fuzzy inference.
The rule R accessed by the identifier of the corresponding input label as the rule-corresponding bit string indicated by the invalid bit
It is held at the address of OM20.

In the example shown in FIG. 2, the output label 0 has a width of 5 bits so that a maximum of 5 rules can be defined. However, the actually defined rules are rule (1) and ( Only 2 of 2). This is this min-
This is to allow the user to appropriately add up to three rules for the output label 0 according to the operation status of the fuzzy inference machine including the max operation circuit. For this purpose, the rule memory is a rewritable ROM.
And RAM are used. The number of rules assigned to each output label is based on the empirical rule of the present inventor, and is designed so that both end portions and the central portion are increased in accordance with the arrangement order of the output labels.

In the example of FIG. 2, output labels 0 and 8 at both ends have a maximum of 5 rules, an output label 3 at the center has a maximum of 6 rules, and an intermediate output label 1 has a maximum of 6 rules.
Up to four rules can be assigned to each of the addresses 2 and 2, so that each address holds a rule-corresponding bit string having a total of 42 bits. When the circuit scale has a margin, the number of rules assigned to each output label may be constant for all output labels. Also, in order to improve the utilization efficiency of the rule memory, by adding an appropriate circuit, the number of rules that can be assigned to each output label can be adjusted every time the user of this min-max operation circuit creates a rule. It can also be settable.

The logic circuit 40 that receives the rule-corresponding bit string output from the rule ROM 20 is composed of nine partial logic circuits 41, 42, corresponding to each of the nine output labels.
... 49. Each partial logic circuit creates the logical sum of the unit logic circuits 410, 420, ..., 490, and the same number of rules as the maximum number of rules that can be defined for the corresponding output label, and creates a logical sum in the corresponding data register. Output OR gates 411, 421 ...
... It is composed of 491.

The unit logic circuit 410 uses the rule ROM 2 when re-outputting the grade of the input label from the rearrangement circuit 10.
Only when the first "1" appears in the rule corresponding bit output from 0, "1" is output to the input terminal of the OR gate 411. That is, even if the second and third "1" appear in the rule corresponding bit, "1" is not output to the input terminal of the OR gate 411. The configuration of such a unit logic circuit will be described in detail later.

Now, after the contents of the grade registers 31 to 39 are initialized to zero, the grade rearrangement circuit 10
When the output of the grade of the rearranged input label is started from, the identifier corresponding to the grade of the input label output on the grade bus 51 is output from the grade rearrangement circuit 10 on the label bus 52. The identifier output on the label bus 52 is supplied to the address input terminal of the rule ROM 20 and is stored in the rule ROM 20.
The rule-corresponding bit string of bits is output in the order of the grade of the input label being output regardless of the arrangement order of FIG. 2, and each rule-corresponding bit is a total of 4 of the logic circuits 41 to 49.
It is supplied to the two unit logic circuits 410 to 490.

When the first "1" appears in one rule-corresponding bit string sequentially read from the rule ROM 20, "1" is output to the OR gate 411, and accordingly, the OR gate 411 transfers to the corresponding grade register 31. "1" is output to instruct to hold the data. The grade register 31 that has received this holding command is
Keep the grade that is emerging above. That is, the unit logic circuit 410 causes the data register 31 to hold the grade of the first accessed input label among the one or more input labels included in the antecedent part of each rule regarding the output label 0 of the output channel 0. Perform a function.

Here, considering that the grades of the input labels appearing on the grade bus 51 appear in ascending order, the input labels held in the register 31 based on the rule corresponding bit which becomes "1" first. Is the minimum of the grades of the one or more input labels included in the antecedent part of each rule of the output label 0. That is, each of the unit logic circuits 410 fulfills a part of the function for realizing the min operation for each input grade included in each rule as the antecedent part.

Regarding the output label 0, the grade of the input label is held in the register 31 every time "1" is output from each unit logic circuit 410 installed for each rule. At this time, the grade of the input label already held is replaced by the grade of the input label newly held. Therefore, at the end of the re-output of the grade from the input label grade rearrangement circuit 10, the input label grade held in the data register 31 outputs “1” at the end of each unit logic circuit 410. It is nothing but the grade of the input label included in the rule corresponding to the thing. Here, considering again that the larger the grade that appears on the grade bus 51 appears later, the grade of the input label held in the data register 31 by the rule corresponding bit that finally becomes “1” corresponds to It is nothing but the maximum value (max) of the minimum values (min) of the grade of the input label obtained for each rule included in the output label of.

That is, each of the unit logic circuits 410 performs a part of the function of min operation for each input grade included as an antecedent part in each rule by itself, and is installed in parallel with each other and each output terminal is an OR gate. 41
Min-max due to the overall configuration in which 1 is logically added
It will fulfill a part of the function of calculation. The rest of the min-max operation function is owed to the function of the input label grade rearrangement circuit 10 in which the smaller the grade on the grade bus 51, the more the output of the input label grade is output. This min-max operation function is performed by the partial logic circuit 42 installed corresponding to the other output label of this output channel.
The same applies to all of the other partial logic circuits, which are installed corresponding to the output labels for all other output channels (not shown).

In this way, the grade rearrangement circuit 10
When a total of 16 non-zero grades are output from, the grade of each input label of each input channel
The grade of each output label of each output channel calculated based on the min-max operation is held in the grade register.
The grade of each output label of each output channel held in this grade register is transferred to the defuzzification circuit in the subsequent stage via the grade bus 51, and is subjected to the defuzzification processing by the center of gravity method or the like to be deterministic. It is output to each output channel as output data.

Now, each unit logic circuit corresponds to the unit logic circuit 4
As shown in FIG. 3 as a representative of 10, a rear stage portion including a D flip-flop 411a and a 2-input AND gate 411b, and a front stage portion including JK flip-flops 411c and 411g, a switch 411d, and logic gates 411e and 411f. It consists of The main operation of this unit logic circuit is to share a part of the function of the min-max operation during the re-outputting of the rearranged input label grade, as described above. First, the D flip-flop 41
The latter part composed of 1a and the two-input AND gate 411b realizes a differentiation function of outputting "1" only for a half clock period when the output of the OR gate 411f in the former part changes from "0" to "1". . On the other hand, the JK flip-flop 411g in the preceding stage portion
And the OR gate 411f are for prohibiting the function of the latter part of the nonuse rule. In the latter part, the JK flip-flop 411
The part consisting of c and the OR gate 411f is the rearrangement circuit 1
When an invalid input label that does not correspond to the rule appears during the rearrangement of the input label grade by 0, the valid input label specified by the rule is zero grade, or during the min-max calculation process. When the first valid bit designated in the antecedent part of each rule appears, that is, when the minimum grade of the rule appears, the function of the latter stage is stopped thereafter.

Whether the input label grade re-arrangement circuit 10 is executing rearrangement or one of the input gates of the arranged input labels is being re-outputted to one of the input terminals of the NOR gate 411e in the preceding stage. In the former case, a signal "0" is input, and in the latter case, a signal "1" is input. To the other input terminal of the NOR gate 411e, "1" is input from the valid flag signal line 53 in FIG. 1 if the grade of the input label to be rearranged is zero, and "0" is input if it is not zero.

First, before the rearrangement of the input label grade rearrangement circuit 10 is started, an initial value "1" is set in the JK flip-flop 411g based on a preset signal, and the JK flip-flop 41 is also set.
The initial value "0" is set in 1c. After this, when the rearrangement circuit 10 starts rearrangement of the input label grades, the rule ROM 20 is accessed while receiving the identifier of the input label appearing on the label bus 52 at the address terminal. During the rearrangement of the grades of the input labels, "0" is continuously input to one input terminal of the NOR gate 411e as described above.

When "0" that indicates that the grade of the input label on the grade bus 51 is not zero appears at the other input terminal of the NOR gate 411e, the output of the NOR gate 411e becomes "1", and the switch 411d is switched to the position shown in the figure. It is switched to the state shown by the dotted line. In this state, input terminal IN
When the rule-corresponding bit "1" appears, the state of the JK flip-flop 411g is inverted from the initial value "1" to "0". On the other hand, when "1" indicating that the grade of the input label is zero appears at the other input terminal of the NOR gate 411e when the rule bit of "1" appears at the input terminal IN, the output of the NOR gate 411e becomes It becomes "0", the switch 411d is switched to the state shown by the solid line in the figure, and the state of the JK flip-flop 411c is inverted from the initial value "0" to "1". Therefore, the output of the OR gate 411f at the time when the rearrangement of grades is completed is “0” when a non-zero grade input label is specified for all the rule corresponding bits “1”, and in other cases. That is, if the zero-grade input label is specified even once for the rule corresponding bit "1", or if the rule corresponding bit "1" does not appear at all, the initial value "1" is maintained. .

After that, when the rearrangement circuit 10 starts the re-output of the rearranged input label grade and the corresponding identifier for the min-max operation, the switch 411d is switched to the state shown by the solid line in the figure. The rule corresponding bit read from the rule ROM 20 is supplied to the J input terminal of the JK flip-flop 411c through the switch 411d. If the states of the JK flip-flops 411c and 411g are both "0" at the start of this re-output, "0" is supplied to the inverting input terminal of the 2-input AND gate 411b, so that the rule corresponding bit is first set to "0". When it becomes "1", "1" is output from the output terminal OUT for a half clock period, and the grade of the input label appearing on the grade bus 51 is the grade register 31.
Held in.

On the other hand, the JK flip-flop 41
If 1c or 411g is held at "1" at the start of the output of the rearranged input label grade,
Since the "1" signal is continuously supplied to the inverting input terminal of the 2-input AND gate 411b, "1" is not output from the output terminal OUT even if the rule corresponding bit becomes "1".
That is, the operation at the time of re-output of the unit logic circuit 410 is prohibited. As described above, in the pre-stage portion in the unit logic circuit 410 of FIG. 3, when the grade of any of the input labels included in the antecedent part of the corresponding rule is zero, or the rule puts the input label in the antecedent part. When the unused rule does not include even one, the unit logic circuit performs a function for determining an effective rule that prohibits the unit logic circuit from participating in the min operation. The necessity of such a function is based on the following three reasons.

The first reason is that in the rearrangement circuit 10 in the previous stage in this embodiment, the zero grade discard having the correspondence with the rule is performed in parallel with the rearrangement of the input label of the non-zero grade. This is because, according to the original principle of min-max calculation, zero grades that have a correspondence with such rules cannot be simply discarded or ignored. That is, according to the original min-max operation, a zero grade that has a correspondence with a rule is also subject to the min operation like other non-zero grades, and a rule that includes the input label of this zero grade in the antecedent part. For, a zero min result must be obtained.

Therefore, if such a zero grade is simply discarded for simplification of the rearrangement circuit 10, the smallest non-zero grade other than this becomes the min operation result for the rule, resulting in an error. . Therefore, in order to prevent such an error, when discarding a zero grade that has a correspondence with a rule, it is necessary to instruct the min operation for the rule containing this zero grade in the subsequent min-max operation. One bit of information is stored.
This is because the contents of each grade register are initialized to zero, so that the inhibition of the min operation by the 1-bit information produces the same result as holding the zero grade.

The second reason is that "the fuzzy inference grade arithmetic circuit" which the present applicant separately performs before and after this patent application.
When using the grade operation circuit disclosed in the patent application entitled, the reordering circuit 10 rearranges the input label grades, it is invalid during the operation of the input label grade defined by the Π-type membership function. Data may be output, and in such cases min-max
It is necessary to prohibit the operation, and for this reason, the min operation is prohibited by 1-bit information.

The third reason is that the rule included in a certain output label and not used at all is min-
This is because it must be distinguished as a rule that is not subject to max operation. This is necessary when adding a weighting function to the rule. The JK flip-flop 411g in FIG. 3 is added as a discriminator of this effective rule.

Now, at the end of the min-max operation at the time of re-output, a maximum of nine grades of non-zero output labels are held in the nine grade registers of each output channel.
This maximum of 9 output label grades per output channel is read into the subsequent defuzzification circuit and used to truncate the membership function of the corresponding output label. In order to reduce the calculation time for this defuzzification, the output label is different from the input label in that the corresponding membership function is replaced by a line segment of unit height set at the position of its center of gravity. Singleton data is used, and the singleton data is truncated by the grade of each output label, so that the singleton data has a height equal to the grade of the output label.

According to a patent application called "a defuzzification method for fuzzy reasoning" filed separately by the applicant, all truncated singleton data are used in order to further reduce the defuzzification operation time. There is disclosed an approximation method in which only two pieces of singleton data are selected in descending order of height and the center of gravity is calculated using these, instead of performing the center of gravity calculation. In order to perform such an approximation method, it is necessary to select only two grades from the maximum of nine output label grades held in the nine grade registers 31 to 39 in descending order. If this selection is made in the defuzzification circuit in the subsequent stage, a large number of comparison operations are required and the processing time is prolonged, or if it is intended to shorten the processing time, a complicated arrangement in which many comparison circuits are arranged in parallel is required. Requires hardware.

Such a problem is solved by selectively holding only the largest and the next largest grades of the output label of the calculation result in parallel with the above-mentioned min-max calculation. FIG. 4 shows the configuration of a selective holding circuit according to another embodiment of the present invention, which enables such selective holding of the output label grade.

The selective holding circuit shown in FIG. 4 is obtained by replacing the nine grade registers 31 to 39 shown in FIG. 1 with the elements shown in the figure. To clarify the correspondence with FIG.
The nine OR gates 41 to 49 common to FIG. 1 and the grade bus 51 are shown overlapping with FIG. This selective holding circuit is provided in a cascaded grade register 111.
~ 113, label registers 121 also connected in cascade
To 123, a match determination circuit 114 for determining the match of the grades held in the registers, a match determination circuit 124 for determining the match of the labels held in the registers, and the like.

The outputs of the OR gates 411 to 491 are directly input to the label register 121, and also input to the D-type flip-flop 132 via the OR gate 131. Therefore, when the output of any of the OR gates 411 to 491 becomes "1", the D-type flip-flop 132 is set to "1", the grade appearing on the grade bus 111 is held in the grade register 111, and
The output of the OR gates 411 to 491 is the label register 12
Held at 1. However, the label mentioned here is different from the identification code of the input label for accessing the rule ROM 20 of FIG. 1, and displays nine input labels in each output channel by the bit position where "1" is set. It is a thing. The grade held in the grade register 111 is stored in the grade register 11 in the comparison circuit 114.
2 and the label held in the label register 121 is compared with the content of the label register 122.

A. When the contents of the label registers 121 and 122 do not match and the contents of the grade registers 111 and 112 do not match, the contents of the grade register 112 are the same as the grade register 11
3 and the contents of the grade register 111 are transferred to the grade register 112. At the same time,
The logical product of the contents of the label register 122 and the inverted contents of the label register 121 is transferred to the label register 123 through the switch 127 and the AND gate 128, and the OR register 126 is set in the label register 122.
The contents of the label register 121 are transferred through.

B. When the contents of the label registers 121 and 122 do not match, but the contents of the grade registers 111 and 112 match, the logical product of the contents of the label register 123 and the inverted contents of the label register 121 is the switch 127 and the AND gate 128. After being transferred to the label register 123 through the label register 123, the logical sum of the contents of the label register 121 and the contents of the label register 122 is transferred to the label register 122 through the OR gate 126.

C. When the contents of the label registers 121 and 122 match but the contents of the grade register 111 and the grade register 112 do not match
2 is transferred.

D. If the contents of the label registers 121 and 122 match and the contents of the grade registers 111 and 112 also match, no operation is performed.

In the above A, the maximum value of the grades appearing on the grade bus 51 so far is the grade register 1
In this case, the maximum grade up to now is transferred from the grade register 112 to the grade register 113 as the grade having the second largest value, and the content of the grade register 111 is set as the new maximum grade. It is transferred to the grade register 112. In this way, the grade register 112 holds the maximum value of the grade that has appeared on the grade bus 51 so far, and the grade register 113 has the second largest value of the grade that has appeared on the grade bus 51 so far. Is retained. The label registers 122 and 123 hold the labels corresponding to the maximum grade and the second largest grade. By transferring the label held in the label register 122 to the label register 123 while taking the logical product with the inverted content of the label register 121, the same label as the label newly held in the label register 122 is held in the label register 123. Is prohibited.

At the time when the last grade has appeared on the grade bus 51, the grade registers 112 and 11
Each of 3 holds the maximum grade and the second largest grade of each output channel, and the label registers 122 and 123 hold the corresponding output labels.
The content held in each register is read and processed by the defuzzification circuit in the subsequent stage to create definite output data.

As described above, the configuration in which the zero grade is excluded from the targets of the rearrangement and the re-output is exemplified. However, a predetermined threshold value larger than zero is set, and the grades below this threshold are the targets of the rearrangement and the re-output. It can be configured to be outside.

Further, in order to realize a high-speed processing of the entire fuzzy inference, the rearrangement circuit and the grade arithmetic circuit in the preceding stage are connected in cascade, and the grade arithmetic operation and the rearrangement of the already-calculated grade are pipelined. The configuration to be executed is illustrated. However, when such high speed is not required, a buffer memory may be installed between the rearrangement circuit and the grade calculation circuit, and the rearrangement may be started after all the grade calculations are completed. it can.

[0057]

The min-max of fuzzy inference according to the present invention
Prior to the min-max operation, the operation circuit first performs a pre-processing of rearranging the non-zero grade identifier or the instruction information of the input label in the rule antecedent part in descending order of magnitude while discarding most of the zero grade. Because of the configuration, the amount of data to be subjected to the min-max calculation thereafter is significantly compressed, and the processing time is significantly shortened.

Further, since the min-max arithmetic circuit of the present invention is configured to output the grades rearranged by the above-mentioned pre-processing in ascending order, it is known in advance that the grade of the preceding stage circuit is smaller. It is not necessary to repeat the magnitude comparison between grades, and both min and max operations can be completed by setting / resetting a flag of only 1 bit, and the processing time and the amount of hardware can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a min-max operation circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a data configuration in a rule ROM 20 of FIG.

3 is a circuit diagram illustrating a configuration of a unit logic circuit 410 of FIG.

FIG. 4 is a block diagram showing another example of the configuration of the grade holding register in FIG.

[Explanation of symbols]

 10 grade rearrangement circuit 20 rule ROM 30 grade holding register group 40 logic circuit 51 grade bus 52 label bus

Claims (9)

[Claims] 1. A min-max for a grade of an input label calculated for a plurality of input labels defined by a membership function for each of a plurality of input channels.
In a fuzzy inference min-max operation circuit for performing an operation, the min-max of the fuzzy inference is characterized by including means for changing the evaluation order of the input labels according to the order of the grades of the operated input labels. Arithmetic circuit. 2. The identifier of a corresponding input channel number / input label number (hereinafter, simply referred to as “identifier”) together with the grade of the calculated input label is defined by the grade of the input label. The fuzzy inference is characterized in that after the rearrangement is performed in advance in order, the identifiers are taken out in ascending order of grade, and the evaluation of the rules is executed by determining the correspondence between this identifier and the antecedent part of the fuzzy inference rule. of
min-max operation circuit. 3. The grade according to claim 2, wherein the grade of the calculated input label that exceeds a predetermined threshold is subject to the rearrangement, and the grade that is less than the threshold is subjected to exception processing. A min-max operation circuit for fuzzy inference. 4. Among grades of input labels calculated for a plurality of input labels defined for each of a plurality of input channels, those having a predetermined threshold value or more,
After rearranging according to the order of magnitude with the corresponding input channel / input label identifier (hereinafter referred to as “identifier”), the grade of the input label after rearrangement is output in ascending order and with the corresponding identifier, and the threshold For input label grades of less than, according to the instruction signal indicating that, the rearrangement circuit that excludes the rearrangement and output according to the instruction signal, each input label of each input channel, and all the fuzzy rules used for this fuzzy inference. Enable / disable the correspondence of
As a rule-corresponding bit string indicated by an invalid bit, a rule memory that holds and outputs at an address designated by an identifier supplied at the time of rearrangement and output by the rearrangement circuit, and a rule that can be included in each output label of each output channel The same number as the maximum number is set, and only when the grade of the input label in the rearrangement corresponding to the valid bit appearing in the rule corresponding bit string output from the rule memory at the time of rearrangement by the rearrangement circuit is equal to or more than the threshold value. At the same time as being enabled, when the grade of the rearranged input label from the rearrangement circuit is output, the effective bit that first appears in the rule corresponding bit string output from the rule memory is detected and a significant signal is detected. The same number of generated min operation parts and output labels of each output channel are installed, and output from each corresponding min operation part. And a logic circuit having a max operation unit for outputting a logical sum of significant signals as a command to hold the grade of the input label being output from the grade rearrangement circuit of the input label, and the grade rearrangement circuit of the input label A min-max operation circuit for fuzzy inference, which holds an input label grade holding circuit for holding the grade of the input label being output from the device according to the holding command output from the logic circuit. 5. The grade of the input label calculated according to a plurality of input labels defined for each of the plurality of input channels is supplied to the rearrangement circuit in a calculation order by a grade calculation circuit at a preceding stage. As a result, the rearrangement circuit and the grade operation circuit in the preceding stage operate in a pipeline manner in cooperation with each other, and a min-max operation circuit for fuzzy inference. 6. The fuzzy inference min-max operation circuit according to claim 5, wherein the grade holding circuit of the input label is installed corresponding to each of the max operation units of the logic circuit. 7. The grade holding circuit for the input labels according to claim 6, wherein the grade holding circuits for the input labels are installed in a predetermined number of columns less than the total number of output labels defined for each of the output channels, and grade holding circuits for each input label are provided. A min-max arithmetic circuit for fuzzy inference, wherein each of the registers holds the predetermined number of output label grades in order from the largest of the output label grades of each output channel. 8. The min-max arithmetic circuit for fuzzy inference according to claim 7, wherein the predetermined number is 2. 9. The fuzzy inference min-max arithmetic circuit according to claim 4, wherein the predetermined threshold value is a minimum finite value that can be processed by the arithmetic circuit.