JPH07175659A - Min/max arithmetic circuit for fuzzy inference - Google Patents

Abstract

PURPOSE:To accelerate arithmetic speed and to reduce a hardware amount by spatially rearranging input labels contained in the antecedent parts of respective rules in the order of their grades. CONSTITUTION:Concerning the grades of input labels successively appearing on a grade bus 51, an input label rearranging circuit 10 performs the abandonment of a zero grade and the rearrangement corresponding to the order of grades. Next, the rearranged input labels are outputted to the grade bus 51 according to addresses from an address counter 54 successively from the small grade. At the same time, label codes are outputted to a label code bus 52 and supplied to a rule ROM 20, and a rule corresponding bit group is outputted from the rule ROM 20. According to a control signal from a timing control circuit 61, a corresponding bit group selecting circuit 62 selects either the rule corresponding bit group successively read from the rule ROM 20 or a weight corresponding bit group from a weight corresponding bit group generating circuit 61 and distributes it to respective minimum grade detecting circuits 41-49.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs a min-max operation on a grade of an input label generated in a fuzzy inference machine used for controlling various home appliances and vehicles to generate an output label grade. It relates to a min-max arithmetic circuit for fuzzy reasoning.

[0002]

2. Description of the Related Art Fuzzy control using fuzzy inference is being applied to a wide range of existing control such as control of various home appliances and vehicles. In the multi-fuzzy inference that forms the core of this fuzzy inference, first, the degree of relevance (grade) between the multiple fuzzy concepts on the input side included in the antecedent part of the fuzzy rule and the facts indicated by the actual input data. Is calculated. A label is added to the plurality of fuzzy concepts on the input side in order to identify each other. Therefore, each fuzzy concept is also referred to as an input label. Corresponding to the rule about the grade of each input label calculated
By performing the min-max operation, the grade of the output label for cutting off the membership function of the fuzzy concept (output label) on the output side included in the consequent part of each rule is calculated. Finally, defuzzification is performed, in which the deterministic output is obtained from the centroid of the membership function of each output label truncated by the corresponding grade.

The contents of the above-mentioned min-max calculation will be described with a specific example. First, it is assumed that the following seven rules are defined. Rule (1) if A and B then X Rule (2) if B and C then X Rule (3) if E and F then X Rule (4) if G and M and N then X Rule (5) if C and D Then Y rule (6) if H and I then Z rule (7) if J and K and L then Z where A to L included in the antecedent part of each rule are input labels and X to included in the consequent part Z is an output label. Also, the calculated input labels A to L grades Ag to Lg
Are Ag = 0, Bg = 0.06, Cg = 0.7, Dg = 0.55,
Eg = 0.65, Fg = 0, Gg = 0.45, Hg = 0.9, Ig = 0, Jg
= 0, Kg = 0, Lg = 0.62, Mg = 0. 2, Ng = 0.

First, for each rule, a min operation is performed to select the smallest grade of the input label included in the antecedent part of the rule. For example, in rule (1), the antecedent part includes the input labels A and B, but the grades Ag and Bg are 0 and 0.6, respectively.
6, the smaller grade Ag is selected.
Similarly, for rule (2), input label B grade
Bg is selected, the rule (3), the grade Fg of the input label F, is selected, and the rule (4), the grade Ng is selected.

Next, for a plurality of rules having a common output label, a max operation is performed to select the largest of the minimum grades of the min operation results. That is, for each of the four rules (1), (2), (3), and (4) with the same output label, the minimum grade Ag obtained by min operation,
Largest of Bg, Fg and Ng, ie grade
Bg is selected. Similar max operation is output label Y and Z
For output label Y, grade D
g is the operation result, and the output label Z is the grade
The calculation result is Ig = Jg = Kg = 0.

In the above fuzzy inference machine for control, in order to receive a plurality of input data such as speed, pressure and temperature,
A plurality of input channels are provided, and a plurality of input labels are defined for each input channel. Further, a plurality of output channels are provided for outputting a plurality of output data regarding opening / closing of switches and opening of valves, and a plurality of output labels are defined in each output channel. Therefore, the total number of input label grades calculated is equal to the number of input labels per input channel × one input channel, and the amount of data to be subjected to the min-max calculation in the subsequent stage becomes considerably large.

Conventionally, the control based on the fuzzy inference as described above has been mainly applied to low-speed control of home electric appliances and the like, but it is required to be relatively complicated and high-speed such as vehicle running control and suspension control. In order to apply it to the technical field, it is necessary to dramatically reduce the conventional processing time, typically by about 3 digits. This reduction in calculation time is performed by the grade calculation for the input label, the calculation of the output label grade by the min-max calculation for this calculated grade group, and the membership of the output label truncated by the calculated grade. It is necessary to realize each stage of defuzzification by calculating the center of gravity of the function while maintaining harmony.

[0008]

Conventionally, the min-max operation for the grade of the input label is realized by comparing the grades of the input label included in the antecedent part of each rule. A typical example of a system that realizes this size comparison by software processing is disclosed in Japanese Patent Application No. 4-10133, etc. However, in such software processing, it is necessary to repeat many size comparisons. There is a problem that it is difficult to improve the calculation speed. A typical example of a system for realizing the above size comparison by a hardware circuit is disclosed in Japanese Patent Application No. 2-159628, etc., but it is necessary to execute a large number of comparison operations for input labels included in each rule. However, there is a problem in that it is difficult to increase the speed, and it becomes difficult to reduce the manufacturing cost because the scale of this hardware circuit becomes large.

In a typical fuzzy inference,
Most of the input label grades subject to min-max operation are zero. For example, for each input channel, if we define each of the eight input label membership functions so that only the nearest neighbors intersect, then each input channel will output two input labels with a non-zero grade. To be done. That is, 70 to 80% of the grades of the input label of the min-max calculation target are zero grades.
The zero grade (hereinafter referred to as “zero grade”) that occupies most of this is that the grade of other input labels (hereinafter referred to as “non-zero grade”) does not substantially affect the min-max operation result. Has a specificity different from that of However, in the conventional min-max operation, zero grade is processed in the same way as non-zero grade, so
A large amount of useless processing is included, which makes it more difficult to improve the calculation speed and reduce the hardware amount.

Further, in a control system using fuzzy inference, a user may want to remove a rule or weaken the influence of the rule based on the usage result. The subsequent modification of such a rule can be realized by multiplying the min operation result of the rule by a weighting coefficient of zero or less than 1. However, there is a problem that the circuit becomes complicated when trying to realize the multiplication of the weighting factors.

Therefore, an object of the present invention is to improve the speed of computation and reduce the amount of hardware by using fuzzy inference mi.
It is to provide an n-max operation circuit, and in particular, it is a fuzzy inference mi that can easily realize weighting for each rule.
It is to provide an n-max operation circuit.

[0012]

A min-max arithmetic circuit for fuzzy inference according to the present invention, which solves the above-mentioned problems of the prior art, comprises a judging means for preliminarily judging the magnitude relation of grades of input labels concerning fuzzy inference. And a calculation unit that executes the min-max calculation according to the order of magnitude determined by the determination unit. More specifically, whether to enable / disable whether each rule includes each input label in each antecedent part according to a predetermined array defined for each input label included in each antecedent part of each fuzzy inference rule A coding rule to be displayed in bits is defined for each rule, and a rule-corresponding bit group that indicates whether or not each coding rule thus defined includes a specific input label by a valid / invalid bit group is input to each rule. Defined for the label. By holding the rule-corresponding bit group defined for each input label at the address specified by the identification code of the input label (hereinafter referred to as "label code"), each coding rule can be distributed over multiple addresses and A rule memory is provided which holds the bits while arranging them in a predetermined order in the arrangement direction of each bit of each rule corresponding bit group.

Furthermore, min- of fuzzy inference according to the present invention
The max operation circuit rearranges the input label grades calculated for each input label together with the corresponding label code in the order of magnitude, and then outputs the rearranged input label grades in ascending or descending order. An input label rearranging means for outputting a corresponding rule-corresponding bit group by supplying a label code as a read address of the rule memory is provided.

Further, the min-max operation circuit of the present invention holds a weighting factor output means for outputting the weighting factor assigned to each rule of fuzzy inference in ascending or descending order, and the weighting factor assigned to each rule. And a weight-corresponding bit group generating means for generating a weight-corresponding bit group that indicates whether or not the held weight coefficient is equal to the weight coefficient output from the weight coefficient output means, by a valid / invalid bit for each rule. , Comparing the grade of the input label output from the rearrangement means and the weight coefficient generated from the weight coefficient output means, selecting one of the rule-corresponding bit group and the weight-corresponding bit group according to the comparison result, and A weighting section comprising selection means for selecting one of the input label grade output from the array means and the weight coefficient output from the weight coefficient output circuit There.

Further, the min-max operation circuit of the present invention is installed corresponding to each output label of fuzzy inference, and
Of the grade or weighting factor of the input label selected by the selecting means included in this output label based on the effective bit that appears first or last in the rule corresponding bit group or the weight corresponding bit group selected by the selecting means The information about the smallest one is found for each rule, and the maximum grade or weighting factor is min-for this output label based on the information about the smallest value found for each rule.
A min-max detection means for detecting the max calculation result is provided.

[0016]

According to the present invention, the input labels included in the antecedent parts of all rules are rearranged by the input label rearrangement circuit in the order of the grade. As an example, assuming that the seven rules described above in relation to the description of the prior art are defined and the grade of each input label A to N included in each rule has the value as described above, By rearranging the input labels included in the case section in the order of the grade, the result shown in FIG. 10 is obtained.

As described above, by spatially rearranging the input labels included in the antecedent part of each rule in the order of magnitude of the grade, the input label having the minimum grade is the input arranged on the rightmost side. For multiple rules that are labels (enclosed by a circle) and have a common output label, the input label with the largest maximum value among the minimum grades of the min operation results is the one that is arranged on the leftmost side (double It is easily found to be). In this way, by spatially rearranging the input labels included in the antecedent part of each rule in order of magnitude of the grade, it is possible to easily know the result of the min-max operation from the order of arrangement.

The rearrangement result of FIG. 10 is suitable for human discrimination, but is not suitable for automatic discrimination. Therefore,
According to the present invention, from the viewpoint of facilitating automatic discrimination with a minimum amount of data, first, encoding of each rule defined in the system prior to rearrangement of the input label is performed. Is done. The coding of each rule defines in advance the array order of all input labels defined in all input channels in the system, and determines whether or not each input label is included in each rule. Is a valid bit (for example, “1”), and when not included, it is realized by arranging the information indicated by an invalid bit (for example, “0”) in the same order as the arrangement order defined for the input label. .

In the example of FIG. 10, if the arrangement order in alphabetical order is defined for each input label from A to N, the rule (1) is that only the input labels A and B are set as the antecedent part. The encoding rule that encoded this to include
(1) is, as shown in FIG.
0000 ". Similarly, rule (5) has input label C
Since only the antecedent and D are included in the antecedent part, the encoding rule (5) that encodes this is, as shown in FIG.
It becomes 0000000 ".

Next, the above encoding rules are set in a predetermined order,
Preferably, by arranging those having a common output label so as to be adjacent to each other, a two-dimensional array of valid / invalid bits as illustrated in FIG. 13 is obtained. This valid /
The two-dimensional array of invalid bits is obtained by vertically tracing from the bottom of FIG. 13, that is, when all the coding rules are scanned for an arbitrary input label, each input label is arranged in a predetermined order. Whether or not it is included in the antecedent part of the rule is a bit array that is indicated by a valid bit (“1”) if included and a valid bit (“0”) if not included.

Such an array of valid / invalid bits for one column will be referred to below as a "rule corresponding bit group of each input label".
Called. For example, in the case of FIG. 13, the rule-corresponding bit group of the input label A is “1000000”, and the rule-corresponding bit group of the input label N is “0001000”. Such a rule-corresponding bit group of each input label is held in advance in a memory such as a ROM accessed by the identification code (a to n) of each input label. Such a memory will be referred to as "rule memory" below, or "rule RO" when this memory is constituted by a ROM.
"M" etc., and the identification code (a to n) of the input label that specifies the read address of this rule memory.
Is called a "label code". As described above, according to the present invention, the rule RO is encoded, and the encoding rule is used as the rule RO having the address specified by the label code.
It is held in M as a rule corresponding bit group.

Further, when the rule-corresponding bit group of each input label shown in FIG. 13 is spatially rearranged in the order of the grade of each input label, the result shown in FIG. 14 is obtained. When rearranging from FIG. 13 to FIG. 14,
It is premised that even if the arrangement order of the input labels included in each antecedent part of a certain rule or its encoding rule is changed or exchanged, the content of the rule or its encoding rule is not changed at all. This is ifA and
This is because the rule of B then X is not changed even if it is transformed into if B and A then X by changing the order of the input labels of the antecedent part.

As described above, the rule-corresponding bit group of each input label is spatially rearranged in order of the grade of the input label, so that the arrangement shown in FIG. 14 can be obtained automatically and easily. That is, the effective bit (“1”) located on the rightmost side of each of the coding rules included in FIG. 14 is detected, and then the detection of each of one or a plurality of coding rules including an arbitrary output label in common has been completed. Of the most significant bit on the rightmost side of, the input label corresponding to the most significant bit on the leftmost side is detected, and finally, the grade of the detected input label is selected. , This is the min-max operation result for the output label.

As described above, it is possible to perform the min-max operation based on the spatially arranged rule-corresponding bit group. Regarding the configuration of such a spatial min-max operation, the applicant Already filed another patent application (Japanese Patent Application No. 4-3
32402). Min-max of the present invention
The arithmetic circuit performs a time-series min-max operation that utilizes the order of appearance of the rule corresponding bits. Regardless of whether the method is spatial or time-series, the processing time is greatly shortened by the arrangement in which the input labels are once rearranged in the order of grades.

That is, according to the conventional min-max operation circuit, the grades of the input labels included in the antecedent part are compared for each rule.
Assuming that there are 10 rules including B and B in the antecedent part, the magnitude comparison of each grade is repeated for 10 rules, that is, 10 times. On the other hand, in the min-max operation circuit of the present invention, even if there are any number of rules including the input labels A and B in the antecedent part, the comparison of each grade is required only once. , The calculation time is greatly reduced.

The input label rearrangement circuit required for the time-series min-max calculation reorders the grades of the input labels calculated for each input label together with the corresponding label codes in the order of magnitude and then The corresponding rule-corresponding bit group is sequentially output by supplying the corresponding label code as the read address of the rule memory according to the order of the grade of the rearranged input label. Focusing on each bit position of the rule-corresponding bit group sequentially output from the rule memory, each coding rule held in the rule memory appears in time series while being deformed by the replacement of the input label.

Therefore, in the min-max arithmetic circuit of the present invention,
A minimum grade detecting portion for detecting the minimum grade included in each encoding rule is provided at each bit position of the rule corresponding bit group sequentially output from the rule memory.
Each minimum grade detection part is the grade of the input label output from the input label rearrangement circuit and the order of rearrangement, and first in each encoding rule output from the rule memory,
Alternatively, the detection result regarding the minimum grade is obtained based on the last valid bit. In other words, if you access the rule memory in ascending order of input label grade,
The grade output from the rearrangement circuit together with the first valid bit of each coding rule can be detected as the minimum grade. On the contrary, if the rule memory is accessed in order of the grade of the input label, the grade output from the rearrangement circuit together with the valid bit appearing at the end of each encoding rule can be detected as the minimum grade.

Further, in the min-max arithmetic circuit of the present invention, the maximum grade detecting portion is installed corresponding to each output label. Each maximum grade detection part is based on the detection result about the minimum grade obtained by each minimum grade detection part installed corresponding to each rule that includes each output label as a consequent part. To get

Next, the case of weighting each rule will be described. As an example, rule (2) and rule
Each of (5) is weighted with W (0 <W <1). Since the rule (2) is if B and C then X, in order to weight this rule (2) with W, the weighting factor W is added to the min values of the grades B and C included in the antecedent part of this rule. Multiply by. If the multiplication of the weighting factors is approximated by the min operation, the rule (2) is weighted with W by selecting the smallest one from the grades B and C included in the antecedent part and the weighting factor W. Can be replaced with the min operation. Similarly, weighting W to the rule (5) is performed by selecting the smallest one from the grades C and D and the weighting factor W included in the antecedent part of this rule.
It can be replaced by n operations.

Assuming that the weighting coefficient W is 0.4, this weighting operation adds a weight-corresponding bit group corresponding to the rule-corresponding bit group of the input label of size 0.4 to FIG. 14, as shown in FIG. do it. In this weight-corresponding bit group, the valid bit “1” is set only for the weighted rules (2) and (4), and the invalid bit “1” is set for all other rules that are not weighted. 0 "
Is set. In rule (2), the minimum value B of the grade in the antecedent is 0.06, which is smaller than the weighting coefficient 0.4, so that the weighting effect does not appear. On the other hand, in rule (4), the minimum value D (0.55) of the grade in the antecedent part is replaced with the weighting coefficient 0.4, and the weighting effect appears. In this way, the weighting factor assigned to each rule is treated in the same manner as the grade of the input label included in the antecedent part of the corresponding rule, and the weighting factor can be easily set by introducing the concept of the weight-corresponding bit group. However, this can be easily changed according to the situation such as the system performance.

The above-mentioned min-max operation including the rearrangement of the rule-corresponding bit group of each input label may be realized by software or hardware. In addition, whether it is realized by software or a hardware circuit, various concrete methods can be considered. Hereinafter, typical ones of these concrete realizing methods will be described by way of examples.

[0032]

FIG. 1 is a block diagram showing the construction of a min-max operation circuit for fuzzy inference according to an embodiment of the present invention. 10 is a grade of an input label and a label code are reproduced in order of magnitude of the grade. Input label rearrangement circuit to be arranged, 20 is a rule ROM, 31 to 39 are grade holding register groups, 41 to 49 are min-max detection circuit groups, 51 is a grade bus, 52 is a label code bus, and 53 is a valid flag signal line. , 54 are address generation circuits. Also, 61
Is a weight corresponding bit group generation circuit, 62 is a corresponding bit group selection circuit, 63 is a weight coefficient output circuit, 64 is a comparison circuit, and 65
Is a timing control circuit, and 66 and 67 are gate circuits. For convenience of illustration, the rule ROM 20, the grade holding register groups 31 to 39, and the min-max detection circuit groups 41 to 4
The latter part consisting of 9 is shown for only one output channel. That is, the latter part is installed in a number equal to the total number of output channels, for example, if the total number of output channels is 10, only 10 sets of the same number are installed.

On the grade bus 51, the input labels of the input labels are arranged in the order of arrangement of a plurality of input channels in a grade arithmetic circuit in the preceding stage (not shown) and in the order of arrangement of a plurality of input labels defined for each input channel. The grade calculation is executed, and the grade of each input label of each input channel appears in the execution order of this calculation. Assuming a typical system in which the total number of input channels is 8 and the total number of input labels in each input channel is 9, a total of 72 input label grades appear on the grade bus 51.

The label code of the input channel / input label corresponding to the grade of the input label appearing on the grade bus 51 appears on the label code bus 52 at the same time as the grade of the input label. The label code of each input channel / input label may be represented by a combination of the serial number of the input channel and the serial number of the input label included in this input channel, such as the third input label of the second input channel. Alternatively, it may be expressed by serial numbers assigned to all the input labels arranged in the arrangement order of the input channels and the arrangement order of the input labels defined for each channel.

In a typical fuzzy inference, most of the input label grades appearing on the grade bus 51 are zero. For example, for each input channel, if we define each of the nine input label membership functions so that only the nearest neighbors intersect, then two nonzero input label grades are output from each input channel. It That is, a total of 7 for 8 input channels in total
Only 16 of the two input label grades are not zero, and the remaining 56 are zero grades (hereinafter referred to as "zero grades"). For such an input label grade arithmetic circuit, refer to Japanese Patent Application No. 4-283935 entitled "Fuzzy Inference Grade Arithmetic Circuit" related to the applicant's prior application, if necessary.

In the min-max operation circuit of this embodiment, exceptional processing is executed for the zero grade which occupies most of the grades of the input label, so that the processing time and the circuit scale can be shortened. There is. As part of that, from the grade calculation circuit of the input label in the previous stage (not shown),
If the calculation result is not zero grade, a valid flag indicating that is output to the valid flag signal line 53 if it is zero grade.

The input label grade including a large number of zero grades successively appearing on the grade bus 51 is first discarded in the input label re-arrangement circuit 10 and re-sorted according to the order of the size of the non-zero grade. Array and are executed. The input label rearrangement circuit 10 is basically composed of two systems of data register groups arranged in a column, one of the system data register groups holds the input label grade, and the other system data register group. Corresponding label codes are held in the group.

The discarding of the zero grade and the rearrangement of the grades of the input label according to the order of the size of the non-zero grade are performed on the grade bus 51 only when the valid flag appears on the valid flag signal line 53. This is realized by holding the appearing grade in one of the data register groups of each system together with the corresponding identifier while selecting the holding destination according to the magnitude relationship. Such an input label rearrangement circuit 1
0 can be realized based on an appropriate method, but it is preferable that it is disclosed in a "data sorting circuit" as disclosed in Japanese Patent Application No. 4-293697 filed by the present applicant. Is particularly preferable in that the processing time can be shortened. Details of this input label rearrangement circuit will be described later.

When the rearrangement of the grade and label code by the input label rearrangement circuit 10 is completed, the initial value zero is set for all of the grade register group 30,
According to the continuous addresses supplied from the address counter 54, the grades of the rearranged input labels are output from the input label rearrangement circuit 10 to the grade bus 51 in ascending order (ascending order). At the same time, the corresponding label code is input from the input label rearrangement circuit 10 to the label code bus 5
2 is output. The label code output on the label code bus 52 is supplied to the address input terminal of the rule ROM 20, so that the rule ROM 20 outputs the rule corresponding bit group held at this address, and the corresponding bit group selecting unit. After 62, the data is distributed to the min-max detection circuits 41 to 49 in the subsequent stage.

The rear-stage portion to which the rule-corresponding bit group output from the rule ROM 20 is distributed is the nine min-max operation detection circuits 41, 42, ... Which are installed corresponding to the respective nine output labels. ..49. Each min-max detection circuit is a max detection circuit consisting of the same number of min detection circuits as the maximum number of rules that can be defined for the corresponding output label, and an OR gate that creates and outputs the logical sum of the outputs of these min detection circuits. It consists of and. As shown in FIG. 2 as a representative of the min-max detection circuit 41, if the output labels to be operated by the min-max detection circuit 41 include four rules, then four
It is composed of min detection circuits 411, 412, 413, 414 and an OR gate 415 for creating and outputting a logical sum of these outputs.

Referring to FIG. 2, the min detection circuits 411 to 414 installed corresponding to the four rules (1) to (4) included in the first output label are the input label rearrangement circuit 10. Rule R when outputting the grade of the input label from
Of the rule-corresponding bits selected by the corresponding bit group selection circuit 62 after being sequentially read from the OM 20, or the weight-corresponding bit group generated by the weight-corresponding bit group generation circuit 61 and then selected by the corresponding bit group selection circuit 62. The effective bit “1” that first appears in the corresponding encoding rule that appears in the corresponding rule bit position of
It is configured to output "1" to one input terminal. That is, even if the second and third effective bits "1" appear in the corresponding coding rule, "1" is not output from the corresponding min detection circuit 410. The configuration of such a min detection circuit 410 will be described later in detail with reference to FIG.

The corresponding bit group selection circuit 62 weights the rule corresponding bit group and the weighted corresponding bit group generating circuit 61 which are sequentially read from the rule ROM 20 when the input label reordering circuit 10 outputs the grade of the input label. One of the corresponding bit groups is selected according to the timing control signal output from the timing control circuit 65, and the selected rule corresponding bit group or weighted corresponding bit group is selected via the signal line group 68 to the minimum grade detection circuit 41.
Distribute to each of ~ 49. For convenience of explanation, first, all the weighting factors set for each rule are “1”.
The case will be described. In this case, the corresponding bit group selection unit 62 always selects the rule corresponding bit group output from the rule ROM 20 and distributes it to the minimum grade detection circuits 41 to 49 by the functions of the weight calculation units 63, 64 and 65 described later. , The gate 66 is always open while the gate 67 is always closed.

When the rearrangement of the input labels by the input label rearrangement circuit 10 is completed, the grade registers 31 to 39.
The content of is initialized to zero. After that, the input label rearrangement circuit 10 sequentially outputs the rearranged input labels and label codes in ascending order of grade. The label code output from the input label rearrangement circuit 10 onto the bus 52 is supplied to the address input terminal of the rule ROM 20, and the rule-corresponding bit group held in the rule ROM 20 is output in the order of the grade of the input label. Each bit that constitutes each rule-corresponding bit group, that is, the rule bit that constitutes each encoding rule is the min shown in FIG.
The detection circuits 411 to 414 are supplied.

Each of the min detection circuits 411 to 414 detects the valid bit "1" that first appears in the corresponding coding rule read sequentially from the rule ROM 20, and outputs "1" to the OR gate 415. Along with this OR gate 41
“5” is output from 5 to the corresponding grade register 31 instructing to hold the data. The grade register 31 which has received this holding command holds the grade of the input label appearing on the bus 69 via the grade bus 51 and the gate 66. That is, the minimum grade detection circuits 411 to 41
The function 4 causes the data register 31 to hold the grade of one or a plurality of input labels included in the antecedent part of the corresponding rule, which is first output from the input label rearrangement circuit 10.

Considering that the grades of the input labels appear on the grade bus 51 in ascending order, the input held in the register 31 based on the first valid bit appearing in the corresponding encoding rule. The label grade is none other than the minimum contained in the antecedent part of the corresponding encoding rule. That is, the min detection circuits 411 to 41
Each of 4 fulfills a part of the function for realizing the min operation for each input grade included in the antecedent part of the corresponding rule.

Further, the grade register 31 installed corresponding to the first output label is installed corresponding to each rule having this output label in common.
Every time "1" is output from the min detection circuits 411 to 414, the grade of the input label appearing on the grade bus 51 is held. At this time, the grade of the input label already held is replaced by the grade of the input label newly held. Therefore, when the output of the input label grade from the input label rearrangement circuit 10 is completed, the input label grade held in the grade register 31 is “1” at the end of the min detection circuits 411 to 414. It is nothing but the minimum input label grade contained in the rule corresponding to the output. Here, considering that the larger the grade of the input label output on the grade bus 51, the later it appears, the input held in the data register 31 by the valid bit that appears last in each encoding rule. The label grade is the minimum value (min) of the input label grades detected for each encoding rule included in the corresponding output label.
Is the maximum value (max).

That is, each of the min detection circuits 411 to 414 independently performs a part of the function of the min operation for each input grade included in each rule as the antecedent part, and is also installed in parallel with each other for each output terminal. Is logically added by the OR gate 415,
It fulfills a part of the min-max operation. This mi
The remaining part of the n-max operation function is owed to the function of the input label grade rearrangement circuit 10 that the smaller the one on the grade bus 51, the more the output of the input label grade is output. This min-max math function is installed in the min-max corresponding to other output label of this output channel.
The same applies to the detection circuits 42 to 49 and all other min-max detection circuits installed corresponding to the output labels for all other output channels (not shown).

In this way, the grade rearrangement circuit 10
When a total of 16 non-zero grades are output from, the grade of each input label of each input channel
The grade of each output label of each output channel calculated based on the min-max operation is held in the grade register.
The grade of each output label of each output channel held in this grade register is transferred to the defuzzification circuit in the subsequent stage via the grade bus 51, and undergoes a defuzzification process by the center of gravity method or the like to be deterministic. It is output to each output channel as output data.

Now, the min-max detection circuit 41 shown in FIG.
1 to 414 are represented by the min-max detection circuit 411 in FIG.
As shown in FIG. 5, it is composed of a rear stage portion including a D flip-flop 411a and a 2-input AND gate 411b, and a front stage portion including JK flip-flops 411c and 411g, a switch 411d, and logic gates 411e and 411f. The main operation of this minimum grade detection circuit is to share a part of the function of the min-max operation during the output of the rearranged input label grades, as described above. First, the output of the OR gate 411f at the front stage is changed from "0" to "1" by the rear stage portion including the D flip-flop 411a and the 2-input AND gate 411b.
The differential function that outputs "1" only for a half clock period when the signal changes to is realized.

On the other hand, the part consisting of the JK flip-flop 411g and the OR gate 411f in the former part is for prohibiting the function of the latter part in the nonuse rule. Further, in the part consisting of the JK flip-flop 411c and the OR gate 411f in the preceding stage part, an invalid input label not included in the corresponding rule appears during the rearrangement of the input label grade by the input label rearrangement circuit 10, or If the rule has a valid input label of zero grade, or min-max
After the first valid bit specified in the antecedent part of each rule appears in the calculation process, that is, after the minimum grade of the rule appears, the function of the latter stage is stopped.

Whether or not the input label rearrangement circuit 10 is executing the rearrangement or the output of the grade of the arranged input label is executed at the one input terminal of the NOR gate 411e in the former stage. In this case, the signal "0" is input, and in the latter case, the signal "1" is input. To the other input terminal of the NOR gate 411e, "1" is input from the valid flag signal line 53 of FIG. 1 if the grade of the input label to be rearranged is zero, and "0" is input if it is not zero.

First, the input label rearrangement circuit 10 described above is used.
Prior to the start of the rearrangement by, the initial value “1” is set in the JK flip-flop 411g based on the preset signal, and the initial value “0” is set in the JK flip-flop 411c. After that, when the rearrangement is started by the input label rearrangement circuit 10, the rule ROM 2
0 is accessed while receiving the label code appearing on the label bus 52 at the address terminal. During the rearrangement of the input labels, "0" is continuously input to one input terminal of the NOR gate 411e as described above.

When "0" which indicates that the grade of the input label on the grade bus 51 is not zero appears at the other input terminal of the NOR gate 411e, the output of the NOR gate 411e becomes "1", and the switch 411d is switched in the figure. It is switched to the state shown by the dotted line. In this state, input terminal IN
When a valid bit "1" in the encoding rule appears in J, J
The state of the K flip-flop 411g is inverted from the initial value “1” to “0”. On the other hand, when "1" indicating that the grade of the input label is zero appears at the other input terminal of the NOR gate 411e when the valid bit "1" appears at the input terminal IN, the output of the NOR gate 411e becomes " 0 ", the switch 411d is switched to the state shown by the solid line in the figure, and the state of the JK flip-flop 411c is inverted from the initial value" 0 "to" 1 ". Therefore, the output of the OR gate 411f at the time when the rearrangement of the input label is completed is "" when the grade of the corresponding input label is not zero grade for all effective bits "1" in the encoding rule. 0, and in other cases, that is, when even one zero-grade input label is specified for the valid bit "1" in the coding rule, or when the valid bit "1" is in the coding rule. If no one appears, the initial value is kept at "1".

After this, when the output of the label code corresponding to the grade of the rearranged input label is started from the input label rearrangement circuit 10, the switch 411d is switched to the state shown by the solid line in the figure, and the rule ROM 20 The valid / invalid bit of the coding rule read from the
It is supplied to the input terminal. At the start of this output, J
If the states of the K flip-flops 411c and 411g are both "0", "0" is supplied to the inverting input terminal of the 2-input AND gate 411b, so that the valid / invalid bit of the coding rule is first "1". Output terminal OU
"1" is output from T for half a clock period,
The grade of the input label appearing on the grade bus 51 is held in the grade register 31.

On the other hand, the JK flip-flop 41
If 1c or 411g is held at "1" at the start of the output of the rearranged input label grade,
Since the "1" signal is continuously supplied to the inverting input terminal of the 2-input AND gate 411b, "1" is not output from the output terminal OUT even if the rule corresponding bit becomes "1".
That is, the operation of the min-max detection circuit 410 at the time of outputting the grade of the input label is prohibited. As described above, the preceding stage part in the min-max detection circuit 411 shown in FIG. 3 has a case where the grade of any input label included in the antecedent part of the corresponding coding rule is zero, or this coding rule is If it is a non-use rule that does not include any input label in the antecedent part, it is a valid rule judgment that prohibits this min-max detection circuit from participating in min operation when re-outputting the grade of input label. Perform the function for. The necessity of such a function is based on the following two reasons.

The first reason is that, in the input label rearrangement circuit 10 in the preceding stage in this embodiment, the zero grade discard of the input label included in the corresponding rule is performed in parallel with the rearrangement of the nonzero grade input label. Done, but the original min-ma
This is because the zero grade included in such a rule cannot be simply discarded or ignored according to the x operation principle. That is, according to the original min-max operation, the zero grade of the input label included in the rule is also subject to the min operation like other non-zero grades, and the rule that includes this zero grade input label in the antecedent part. For, a zero min result must be obtained.

Therefore, if such a zero grade is simply discarded for simplification of the input label rearrangement circuit 10, the smallest non-zero grade other than this becomes the min operation result for that rule, resulting in an error. Occurs.
Therefore, in order to prevent such an error, if the zero grade included in the corresponding rule is discarded, the following min-
For rules that include this zero grade in max operation
1-bit information for instructing to prohibit min operation is saved. This is because the contents of each grade register are initialized to zero, so that the inhibition of the min operation by the 1-bit information produces the same result as holding the zero grade.

The second reason is that Japanese Patent Application No. Hei 4 (1999) entitled "Grade Operation Circuit for Fuzzy Reasoning" related to the applicant's earlier application.
In the case of using the grade arithmetic circuit disclosed in US Pat. No. 2,883,935, when the input label rearrangement circuit 10 rearranges the input label, invalid data is generated during the calculation of the grade of the input label defined by the Π type membership function. May be output. In such a case, min-max
It is necessary to prohibit the operation, and for this reason, the min operation is prohibited by 1-bit information.

Now, at the end of the min-max operation at the time of re-output, the corresponding grade register of each output channel, for example, 9 grade registers per one output channel holds the grade of the non-zero output label. To be done.
This maximum of 9 output label grades per output channel is read into the subsequent defuzzification circuit and used to truncate the membership function of the corresponding output label. In order to reduce the calculation time for this defuzzification, the output label is different from the input label in that the corresponding membership function is replaced by a line segment of unit height set at the position of its center of gravity. Singleton data is used, and the singleton data is truncated by the grade of each output label, so that the singleton data has a height equal to the grade of the output label.

For convenience of explanation, the case where all the weighting factors set for each rule are 1.0, that is, the case where the weighting function does not operate at all has been described above. The case where the weighting function operates will be described below. In the embodiment of FIG. 1, the weighting factors that can be set for each rule are 1/8, 2/8, 3/8, ... 7/8, 8/8, and 8 in 8 steps. It is quantized to the kind value. The quantized weighting factors are output in ascending order as 8 types of binary signals of 3 bit width in the weighting factor generating circuit 63 including a counter, that is, 1/8, 2/8, 3/8 ...・ 8/8
That is, they are sequentially generated by increasing by 1/8 and are supplied to the weight corresponding bit group generation circuit 61 and the comparison circuit 64.

As shown in FIG. 4, the weight-corresponding bit group generation circuit 61 has the same number of registers R1 to Rn as the total number n of rules holding the weighting coefficient assigned to each rule, the data held in these registers and the weights. The total number of rules n that compares the weighting coefficient output from the coefficient generation circuit 63 and appears on the signal line 72 and outputs a valid signal “1” if they match and an invalid signal “0” if they do not match n And the same number of comparison circuits COMP1 to COMPn. The weighting factor generation circuit 63 can sequentially generate weighting factors from 1/8 to 8/8 in 1/8 steps, but it is of course possible to add 0/8 as this weighting factor. Here, it is assumed that the reading from the label rearrangement circuit 10 is performed in ascending order of the grade and that the weighting factor 1/8 is being output on the signal line 72.

Referring to FIG. 1, the upper 3 bits of the grade output from the input label rearrangement circuit 10 to the grade bus 51 are supplied to one input terminal of the comparison circuit 64, and the other of the comparison circuit 64 is supplied. It is compared with the minimum weighting factor of 1/8 supplied to the input terminal of. The comparator circuit 64 keeps the output to the timing control circuit 65 low when the grade appearing on the grade bus 51 is smaller than this minimum weighting factor 1/8. In this state, the timing control circuit 65 keeps the signal output on the signal line 73 low. If the signal on signal line 73 is low, gate 6
6 connects grade bus 51 to bus 69 and gate 67
Disconnects the signal line 72 from the bus 69.

If the signal on the signal line 73 is in the low state, the corresponding bit group selection circuit 62 selects the rule corresponding bit group output from the rule memory 20 and selects it via the bus 68 for min-max. It is distributed to the detection circuits 41 to 49.
Further, when the output of the comparison circuit 64 is in the low state, the timing control circuit 65 outputs a stepping pulse of a predetermined cycle on the signal line 75 and advances the generated address of the address generating circuit 54. As described above, when the grade output on the grade bus 51 is smaller than the weighting coefficient, the first operation for performing the min-max calculation on the input grade is performed.

On the other hand, when the grade appearing on the grade bus 51 reaches the minimum weighting factor of 1/8 or more, the output of the comparison circuit 64 changes from the low state to the high state and the timing control circuit 65 causes the signal line 73 to pass. The signal output above is changed to the high state. When the signal on signal line 73 goes high, gate 66 disconnects grade bus 51 from bus 69 and gate 67 connects signal line 72 to the upper 3 bits of bus 69 and keeps the lower 5 bits to zero. When the signal on the signal line 73 changes to the high state, the weight-corresponding bit group selection circuit 62 selects the weight-corresponding bit group generated by the weight-corresponding bit group generation circuit 61, and this is selected via the bus 68 for min. -max is distributed to the detection circuits 41 to 49. As a result, regarding the rule corresponding to the effective bit included in the weight corresponding bit group, the weight coefficient appearing on the bus 69 is held in the corresponding one of the holding registers 31 to 39. That is, with respect to the corresponding rule, the min-max operation equivalent to the grade of the input label included in the antecedent part is executed for the weighting coefficient.

The timing control circuit 65 includes a comparison circuit 64.
When the output of the address generation circuit 5 changes to the high state, the output of the stepping pulse on the signal line 75 is postponed so that the address generation circuit 5
4 and the signal line 7
4 is output to the weighting coefficient generating circuit 63 via 74, so that the weighting coefficient is stepped up from 1/8 to a value of 2/8, which is one step larger. In this way, when the grade appearing on the grade bus 51 is smaller than the appearing weighting factor on the signal line 72, the min.
The second operation for performing the -max operation is performed.

The comparison circuit 64 operates the signal line 72 by stepping.
The new weighting coefficient that appears above is compared with the grade that is appearing on the grade bus 51. If the latter is smaller than the former, the first operation is executed, and in other cases, the second operation is executed. Repeat. As a result, the min-max operation equivalent to the grade of the input label included in the antecedent part of the rule is performed on the weighting coefficient assigned to the rule.

According to Japanese Patent Application No. 4-293698, entitled "Defuzzification Method for Fuzzy Reasoning", which was filed by the applicant of the present application, it was truncated to further reduce the defuzzification operation time. An approximation method is disclosed in which only two singleton data in descending order of height are selected and the centroid calculation is performed using these, instead of performing the centroid calculation using all the singleton data. In order to perform such an approximation method, it is necessary to select only two grades of the maximum nine output labels held in the nine grade registers 31 to 39 in descending order. If this selection is made in the defuzzification circuit in the subsequent stage, a large number of comparison operations are required and the processing time is prolonged, or if it is intended to reduce the processing time, a large number of comparison circuits are arranged in parallel. Requires hardware.

Such a problem is solved by selectively holding only the largest and the next largest grades of the output label of the calculation result in parallel with the above-mentioned min-max calculation. FIG. 5 shows the configuration of a selective holding circuit according to another embodiment of the present invention, which enables such selective holding of the output label grade.

The selective holding circuit shown in FIG. 5 is obtained by replacing the nine grade registers 31 to 39 shown in FIG. 1 with the elements shown in the figure. To clarify the correspondence with FIG.
Nine min-max detection circuits 41 to 4 common to those shown in FIG.
9 and bus 69 are shown duplicated in FIG. This selective holding circuit includes grade registers 111 to 113 connected in cascade, label registers 121 to 123 similarly connected in cascade, a match determination circuit 114 for determining a match of grades held in each register, and a register held in each register. A match determination circuit 124 for determining whether the labels match is provided.

The outputs of the OR gates 411 to 491 are directly input to the label register 121, and the logical sum of these is input to the D-type flip-flop 132 via the OR gate 131. Therefore, OR gates 411-49
When any one of the outputs of 1 becomes "1", the D-type flip-flop 132 is set to "1", the grade appearing on the grade bus 51 is held in the grade register 111, and the outputs of the OR gates 411 to 491 are output. It is held in the label register 121. However, the label referred to here is different from the identification code of the input label for accessing the rule ROM 20 of FIG.
Each input label is displayed by the bit position where "1" is set. The grade held in the grade register 111 is compared with the contents of the grade register 112 in the comparison circuit 114, and the label register 121
The label held at is compared with the contents of the label register 122.

A. When the contents of the label registers 121 and 122 do not match and the contents of the grade registers 111 and 112 do not match, the contents of the grade register 112 are
3 and the contents of the grade register 111 are transferred to the grade register 112. At the same time,
The logical product of the contents of the label register 122 and the inverted contents of the label register 121 is transferred to the label register 123 through the switch 127 and the AND gate 128, and the label register 122 has an OR gate 126.
The contents of the label register 121 are transferred through.

B. When the contents of the label registers 121 and 122 do not match but the contents of the grade registers 111 and 112 match, the logical product of the contents of the label register 123 and the inverted contents of the label register 121 is the switch 127 and the AND gate 128. After being transferred to the label register 123 through the label register 123, the logical sum of the contents of the label register 121 and the contents of the label register 122 is transferred to the label register 122 through the OR gate 126.

C. When the contents of the label registers 121 and 122 match but the contents of the grade register 111 and the grade register 112 do not match
2 is transferred.

D. If the contents of the label registers 121 and 122 match and the contents of the grade registers 111 and 112 also match, no operation is performed.

In the above A, the maximum value of the grades appearing on the grade bus 51 so far is the grade register 1
In this case, the maximum grade up to now is transferred from the grade register 112 to the grade register 113 as the grade having the second largest value, and the contents of the grade register 111 is set as the new maximum grade value. It is transferred to the grade register 112. Thus, the grade register 112 holds the maximum value of the grade that has appeared on the grade bus 51 so far, and the grade register 113 has the second largest value of the grade that has appeared on the grade bus 51 so far. Is retained. The label registers 122 and 123 hold the labels corresponding to the maximum grade and the second largest grade. By transferring the label held in the label register 122 to the label register 123 while taking the logical product with the inverted content of the label register 121, the same label as the label newly held in the label register 122 is held in the label register 123. Is prohibited.

At the time when the last grade has appeared on the grade bus 51, the grade registers 112 and 11
Each of 3 holds the maximum grade and the second largest grade of each output channel, and the label registers 122 and 123 hold the corresponding output labels.
The content held in each register is read and processed by the defuzzification circuit in the subsequent stage to create definite output data.

FIG. 6 is a block diagram showing a part of the configuration of a min-max arithmetic circuit for fuzzy inference according to another embodiment of the present invention. FIG. 6 shows the min-max detection circuit 4 shown in FIG.
1 and a portion corresponding to the holding register 31. That is, the min-max operation circuit of this embodiment is similar to
n-max detection circuit 41 and holding register 31, min-max detection circuit 42 and holding register 32, ... The parts corresponding to the min-max detection circuit 41 and the holding register 31 are shown as a representative, and the other parts are all the same as the configuration of FIG.

In this embodiment, the input label rearrangement circuit 10
When the rearrangement of the input labels by is completed, the rearranged grades are in reverse order from the previous one in descending order of bus 5
5 is output. In addition, the weighting factors are output in descending order of converse to the case of FIG. Four minimum grade detection circuits 511, 512, 513, 514 installed corresponding to each encoding rule read from the rule ROM 20.
Holds the grade or weight coefficient of the input label appearing on the bus 69 in synchronization with the valid bit appearing in the rule corresponding bit group or the weight corresponding bit group selected by the corresponding bit group selection circuit 62. Is composed of a register that last appears in the corresponding bit group, that is, holds the minimum grade or the minimum weighting coefficient. Further, the maximum grade detection circuit 520 performs the max calculation function by selecting and holding the maximum of the minimum grades or the minimum weighting factors held in the four minimum grade detection circuits 511 to 514.

The minimum grade detection circuits 511 to 5
The 2-input AND gate and flip-flop added to 14 are additional circuits for exception processing for zero grade. That is, when a valid zero grade appears during the rearrangement by the input label rearrangement circuit 10, the output of the corresponding 2-input AND gate becomes high and the flip-flop of the subsequent stage is set. Each minimum grade detection circuit in which this flip-flop is set is prohibited from holding the grade or weight coefficient in the register portion at the time of output from the input label rearrangement circuit 10. Furthermore, the minimum grade detection circuit 511 in which this flip-flop is set
The detected values of ˜514 are excluded from the detection targets by the maximum grade detection circuit 521.

FIG. 7 shows the input label rearrangement circuit 10 of FIG.
5 is a block diagram showing an example of the configuration of FIG. 5, 51 is a grade bus in which the grade of the input label output from the grade arithmetic circuit in the preceding stage (not shown) appears, 52 is a label code bus, and 53 is a write enable (WE) flag. It is a signal line that appears as a signal. However, in this example, the valid / invalid flag is the reverse of the case described with reference to FIGS. 1 and 3, and is “0” in the zero grade and “1” in the non-zero grade. 211,21
2, 213, 221, 222, 223, ... are data register groups with selectors each having a built-in selector and connected in cascade.
... are selection control circuit groups arranged in a column corresponding to the data register groups with selectors for controlling the selection operation of the 2-input selectors in the data registers with selectors.

Data register groups 211 and 211 with selectors
12, 213 ... Each is a grade register G
R and 2 placed in front of this grade register GR
And an input grade selector GS. One input terminal A of this grade selector GS is grade bus 5
1, the other input terminal B is connected to the output terminal of the grade register GR in the data register with selector in the previous stage, and the output terminal is the grade register GR in the subsequent stage.
Is connected to the input terminal of. Each of the data register groups 221, 222, 223, ... With a selector includes a label code register LR and a 2-input label code selector LS arranged in the preceding stage of this label record register LR. One input terminal A of this label code selector LS is connected to the label code bus 52, and the other input terminal B is connected to the output terminal of the label code register LS in the data register with selector in the preceding stage, and outputs The terminal is connected to the input terminal of the label code register LS in the subsequent stage.

Grade selector GS and label selector L
When S is high, the selection command SA is conductive between the input terminal A and the output terminal. When the selection command SB is high, it is conductive between the input terminal B and the output terminal.
When both are low, neither input terminal A nor B is conducted to the output terminal. A combination in which both selection commands SA and SB are high is prohibited. The selection control circuits 231, 232, 233 ... Arranged in tandem have the grade and grade bus 5 held in the corresponding grade register.
1. A comparison circuit CMP for performing a size comparison with a new grade appearing on the top, a D-type flip-flop FF for holding a size comparison result by this comparison circuit, and a logic circuit composed of two AND gates A1 and A2. I have it. The comparison circuit CMP is configured to hold the holding data Di of the grade register of its own stage.
And the grade DDn appearing on the grade bus are compared, and when DDn ≦ Di, the output is raised to a high level.

First, before the grade of the input label starts appearing on the grade bus 51, the grade register GR of the selector-equipped data registers 211, 212, 213 ... Is preset through the preset signal line RST. It Preset grade register G
In R, the upper limit value of the grade appearing on the grade bus 51, for example, if the grade is 8-bit width unsigned data, the upper limit value [FF] _H is held. In the following, for convenience of explanation, the grade of the input label is 8-bit width data, and the upper limit value set as an initial value is [FF] _H.

After this preset is completed, the grade of the input label calculated by the grade arithmetic circuit in the preceding stage (not shown) is output on the grade bus 51, and the label code corresponding to this grade is output on the label code bus 52. It Further, only when the value of the grade output to the grade bus 51 is valid data which is not zero, a write enable signal (WE) for instructing the holding of the grade is provided on the valid flag signal line 53 from the preceding grade arithmetic circuit. Is output.

When the first non-zero grade DD1 appears on the grade bus 51 in synchronization with the rising edge of the clock signal (not shown), the selection control circuits 231 and 231 of each stage.
In the comparison circuit CMP in 232, 233, ..., The magnitude comparison between the grade DD1 appearing on the grade bus 51 and the grade Di held in the grade register GR is performed. Since the grade DD1 appearing on the grade bus 51 is less than or equal to the maximum grade value [FF] _H ,
The outputs of the comparison circuits CMP in the selection control circuits in each stage are all high, and this high signal is held in the D-type flip-flop FF in the selection control circuits in each stage in synchronization with the falling edge of the clock signal. The judgment result of the own stage is DD1 ≦ D
A high signal for notifying the selection control circuit of the subsequent stage that it is i is output on the signal line S2.

In the selection control circuit of each stage, the signal line S2 from the selection control circuit of the preceding stage is supplied to the logic circuit composed of AND gates A1 and A2 as the signal line S1 in its own stage. However, only the selection control circuit 231 in the first stage does not have the selection control circuit in the previous stage, and the low signal is continuously supplied to the signal line S1. Therefore, the selection control circuit 2 of the first stage
At 31, the outputs of the AND gates A1 and A2 become high (H) and low (L), respectively, under the above-mentioned magnitude comparison result DD1 ≦ Di, and the corresponding grade selector GS outputs this (H, L). A combination selection signal is supplied.
Corresponding grade selector GS which received this selection command signal
Is appearing on the grade bus 51 by connecting one of the input terminals A connected to the grade bus 51 and the input terminal of the corresponding grade register GR in synchronization with a falling edge of a clock signal (not shown). The first grade DD1 is transferred to and held in the corresponding grade register GR.

On the other hand, in the selection control circuits 232, 233, 234, ... Of the second and subsequent stages, the signal lines S1 connected to the selection control circuits 231, 232, 233 ,.
Since a high signal based on the magnitude comparison result DD1 ≦ Di in the preceding stage appears above, the outputs of the AND gates A1 and A2 are low and high, respectively. Corresponding grade selector GS which receives the selection command signal by the combination of (L, H) brings input terminal B and the input terminal of corresponding grade register GR into conduction in synchronization with the falling edge of the clock signal. Therefore, in the data registers with selectors 212, 213, 214 ...
The maximum grade value [FF] _H held as an initial value in the grade register GR in 3 ... Is shifted and held in the corresponding grade register GR.

As a result, the grade DD1 first appearing on the grade bus 51 is held in the grade register GR in the data register 211 with selector in the first stage, and the data registers 212, 2 with selectors in the subsequent stages.
.. hold the initial value [FF] _H shifted from the grade register GR of the data register 211, 212, 213 ... With selector in the preceding stage. Next, when the second non-zero grade DD2 appears on the grade bus 51, two different data transfer operations are performed depending on the magnitude relationship between this and the first appearing grade DD1. First, the operation in the case of DD2 ≦ DD1 will be described.

The selection control circuit 231 in the first stage compares the newly appeared grade DD2 with the grade DD1 held in the grade register GR.
In this case, since DD2 ≦ DD1, the same selection operation as that at the appearance of the first grade DD1 is performed, and the new grade DD is synchronized with the falling edge of the clock signal.
2 is held in the grade register GR in the data register 211 with a selector at the first stage.

On the other hand, for the data registers 212, 213, 214 ... With selectors in the second and subsequent stages, the combination of the signals of the AND gates A1, A2 in the corresponding selection control circuits 232, 233, 234. Since both are (L, H) as in the previous time, DD1 being held in the grade register GR in the data registers 211, 212, 213 ... With selector in the previous stage and the upper limit value [FF] of the grade
_H is shifted and held. This grade register GR
The shift operation in between is also performed in synchronization with the falling edge of the clock signal at the same time as the grade holding operation from the grade bus 1.

As a result, the grade register GR in the data register 211 with the selector at the first stage holds the grade DD2 which appears second on the grade bus 51,
The grade register GR in the data register 212 with selector in the second stage holds the grade DD1 shifted from the data register 211 with selector in the previous stage, and the data register 213 with selector in the third and subsequent stages.
An initial value [FF] _H shifted from the selector-equipped data registers 212, 213 ... Is held in the grade register GR in 214.

Next, the operation when the grade DD2 appearing second on the grade bus 51 is larger than the grade DD1 appearing first (DD2> DD1) will be described. In this case, the output of the comparison circuit CMP in the selection control circuit 231 at the first stage becomes low, and the AND gates A1, A2
The combination of outputs is (L, L). First stage data register with selector 211 that receives the selection command of this combination
The grade selector GS in
With respect to the above, the conduction to the input terminal of the corresponding grade register GR is not performed. For this reason, the grade register GR in the data register 211 with the selector at the first stage continues to hold the grade DD1 previously held.

On the other hand, the second-stage selection control circuit 23
The output of the comparator circuit CMP in 2 becomes high because the corresponding grade register GR holds the initial value [FF] _H that was previously shifted from the previous grade register GR. In addition, the previous stage selection control circuit 2 appearing on the signal line S2
Since the magnitude comparison result of 31 becomes low, AND gate A
The combination of the outputs of 1 and A2 is (H, L). The grade selector GS in the corresponding data register with selector 212 which receives the selection command of this combination brings the input terminal A and the input terminal of the corresponding grade register GR into conduction.
As a result, the second-stage selector-equipped data register 212
The grade register GR therein holds the grade DD2 (> DD1) appearing on the grade bus 1.

Selection control circuits 233 and 234 in the third and subsequent stages
.., the combination of the outputs of the AND gates A1 and A2 is (L, H) because the comparison result of the comparison in its own stage and the comparison result of the selection control circuits 232, 233 in the previous stage are high. As a result, the corresponding data register with selector 213, 214, ... Holds the initial value [FF] _H shifted from the data register 212, 213 ,.

Thus, the grade DD that first appeared
1 is first held in the grade register GR in the data register 211 with a selector in the first stage, and if the grade DD2 that appears second is less than or equal to the grade DD1, this is held in the grade register in the first stage and is also held in this. The upgraded grade DD1 is shifted and held in the second-stage grade register GR. Conversely, grade DD2
Is larger than the grade DD1, this is held in the grade register GR in the second stage, and the first grade DD1 is continuously held in the grade register GR in the first stage.

To summarize the above data transfer operation, A. The selection control circuit of each stage except the selection control circuit of the first stage is
A1. If the grade appearing on the grade bus 51 is less than or equal to each of the grades held in the previous stage and the grade register of the current stage, the grade held in the grade register of the previous stage is the grade register of the current stage. Transfer to. A2. If the grade appearing on the grade bus 51 is larger than the grade held in the previous grade register but smaller than or equal to the grade held in the own grade register, this appearing grade is Transfer to the grade register. A3. When the grade appearing on the grade bus 51 is larger than the grade being held in the grade register of the current stage, the current value is continuously retained without transferring to the grade register of the current stage.

B. If the grade appearing on the B1. Grade bus 51 is less than or equal to the grade held in the grade register of its own stage,
Transfer the appeared grade to the own grade register. B2. When the grade appearing on the grade bus 51 is larger than the grade being held in the grade register of the own stage, the transfer to the grade register of the own stage is not performed.

Referring to FIG. 5, data registers with selectors 221 and 212 arranged corresponding to the data registers with selectors 211, 212, 213, ...
22, 223 ... Are corresponding selection control circuits 231 and 231, respectively.
In accordance with a selection command from 32, 233, ..., Data registers 211, 212, 213 with selectors at respective stages
・ Perform the same operation as. Therefore, the label code bus 52 corresponds to the grade output on the grade bus 51.
The label code appearing above is held in the label code register LR of each stage corresponding to the grade held in GR in the grade register of each stage.

As a membership function that defines the input label of each input data channel of fuzzy inference, if a shape is set such that only two adjacent membership functions have intersections, a maximum of two input channels can be created for one input channel. A non-zero grade of is calculated. Therefore, by setting the number of stages of the data register with selector to a value twice the number of input data channels, all the non-zero grades appearing on the grade bus can be sorted in ascending order.

The grades of the input labels sorted in the order of size are transferred from the corresponding grade register GR through the gate circuit GG to the grade bus 51 by the read enable signal RE supplied to each stage according to the arrangement order of each stage. Is output. In synchronization with the output of the grade of the input label, the corresponding label code is transferred from the label code register LR to the gate circuit LG by the read enable signal RE.
And is output on the label code bus 52.

FIG. 8 shows the min-m of another embodiment of the present invention.
It is a block diagram which shows the structure of an ax arithmetic circuit. In the figure, the constituents designated by the same reference numerals as those in FIG. 1 are the same constituents as those already described in relation to the min-max operation circuit shown in FIG. Overlapping description of the same components as those in FIG. 1 will be omitted. In the min-max operation circuit shown in FIG. 8, the input label rearrangement circuit 10 in FIG. 1 is replaced by the input label and weight coefficient rearrangement circuit 10a, so that the min-m shown in FIG.
The ax arithmetic circuit has been improved. That is, in the improved min-max operation circuit of FIG. 8, first, the weight coefficient output circuit 63, the comparison circuit 64, and the gate circuits 66 and 67 in FIG. 1 are all removed. Furthermore, the improved min-max of Fig. 8
In the arithmetic circuit, the weight bit generation circuit 61 in FIG. 1 is replaced with a weight corresponding bit group holding memory 61a having a simpler structure, and the timing control circuit 65 in FIG. 1 is replaced with a timing control circuit 65a having a simpler structure. Has been replaced.

In the improved min-max operation circuit shown in FIG. 8, instead of generating the weighting factors which increase sequentially when executing the min-max operation including access to the rule ROM 20, the input label of the rearrangement circuit 10a When rearranging the grades, the weighting factors are mixed in the grades of the input label and rearranged in the order of the size in advance.
When the min-max operation including access to the re-arranged weight coefficient is mixed with the rearranged input label grade, the weight coefficient is output on the grade bus 51. In this way, since the weighting factor and the input label grade are treated as equal and mixed with each other, the weighting factor is also an identifier for distinguishing between the weighting factors (hereinafter, “weighting factor code”) as in the case of the input label grade. ") Is added. Further, a 1-bit identifier for discriminating whether the data output on the grade bus 51 after rearrangement is a weighting coefficient or an input label grade is the most significant bit (MSB) of each label.
Is added to.

The corresponding bit group selection circuit 62 uses the rule RO
When the min-max operation including the access to M20 is executed, the MSBs of the label code and the weighting coefficient code which are mixedly output on the label code bus 52 are received from the rearrangement circuit 10a. The corresponding bit group selection circuit 62 receives the received MS.
If B is included in the label code (for example, “0”), the output of the rule ROM 20 is output on the bus 68. Further, the corresponding bit group selection circuit 62 receives the received M
SB that is included in the weighting factor code (for example, "1")
If so, the weight corresponding bit group output from the weight corresponding bit group holding memory 61a is output onto the bus 68. The weight-corresponding bit group holding memory 61a is a ROM or RA.
It is composed of M etc., holds a corresponding weight-corresponding bit group at the address accessed by the label added to the weighting coefficient, and re-executes the min-max operation including the access to the rule ROM 20. When the address terminal receives the label of the weighting coefficient output from the array circuit 10a to the label code bus 52, the corresponding weight corresponding bit group is output to the corresponding bit group selecting circuit 62.

As in the case of FIG. 1, there are 16 non-zero grades included in the grades of the input labels to be rearranged by the rearrangement circuit 10a for the input labels and the weighting factors, and the weights weighted by each rule. It is assumed that the coefficient has 9 kinds of values that increase from 0/8 to 8/8 in 1/8 steps. Furthermore, it is assumed that the rearrangement circuit 10a has a configuration as shown in FIG. In this case, in the configuration of FIG. 7, in addition to 16 stages for holding 16 non-zero grades as grade registers connected in cascade, 9 stages for holding 9 kinds of newly added weighting factors. Minutes are added. However, because the grade of the input label and the weighting coefficient are treated the same, each grade register holds both the grade of the input label and the weighting coefficient according to the order of magnitude, or transfers them to the subsequent stage. To do
Also, the label register of each stage installed corresponding to the grade register of each stage, regardless of whether it is a label code or a weight coefficient code, holds the grade and weight coefficient of the corresponding input label and Each label code or weighting factor code is held or transferred to the subsequent stage in synchronization with the transfer operation to.

FIG. 9 exemplifies the initial values held in the grade register of each stage and the corresponding label register prior to the start of the rearrangement of the input label grade and weight coefficient. The 9 grade registers in the previous stage have 9 grades of 8 bits each increasing from 0/8 to 8/8 in 1/8 steps.
Kind weighting factors [00] _H , [20] _H , [40] _H ...
・ [FF] _H is held, and it is equal to the upper limit of the grade of the input label in all of the 16 grade registers in the latter stage.
The initial value [FF] _{H of the} bit width is held. In addition, in the nine label registers in the preceding stage, which are installed corresponding to the grade registers in the preceding stage that hold the weighting factors, the identifiers made up of the weighting factors themselves assigned to identify the weighting factors, and these 9-bit width weight coefficient codes [100] _H , [120] composed of MSB (“1”) added to identify the weight coefficient of
] _H , [140] _H ... [1FF] _H are retained. Further, an arbitrary value of 9-bit width, for example, [000] _H is held as an initial value in the 16 label registers in the subsequent stage. In the example of FIG. 9, the label code assigned to the grade of the input label to be rearranged is the MSB (“0”) used for discriminating the 8-bit width portion for discriminating input labels from each other and the weighting coefficient. ) Is added to form a 9-bit configuration.

After that, when the grade of the input label to be rearranged appears on the grade bus 51 and the corresponding label code begins to appear on the label code bus 52, FIG.
A re-arrangement operation similar to that already described in connection with is initiated. In this rearrangement operation, the grade of the input label newly held in the grade register and the held weight coefficient are treated equally without being distinguished from each other. In such a rearrangement operation, only the grade of the input label is newly held in the grade register, and the held weighting coefficient is only transferred to the register in the subsequent stage. That is, each time a grade of a new input label is held in any of the eight grade registers in the previous stage except the first stage, a weighting coefficient having a larger value than this is transferred to the grade register in the subsequent stage. , The weighting factors are distributed to each of the 25 grade registers according to the size and are held together with the grade of the input label.

When the rearrangement of the input label grades and weighting factors is completed in this way, the rearrangement circuit 10a to the grade bus 51 are arranged in the ascending order of input label grades and weighting factors, as in the case of FIG. Is output to. In sync with the output of this input label grade and weighting factor,
The corresponding label code or weighting factor code is the label code
It is output on the bus 52. The rule ROM 20 receives a 9-bit wide label code having an MSB of "0" at its address terminal and outputs a rule corresponding bit group. Similarly, R
The weight corresponding bit group holding memory 61a composed of the OM and the RAM receives the weight coefficient code of 9-bit width with MSB being "1" at its address terminal and outputs the weight corresponding bit group. The corresponding bit group selection circuit 62 receives only the MSB of the data of 9-bit width appearing on the label code bus 52, and if it is "0", it selects the rule corresponding bit group output from the rule ROM 20 and outputs it to the bus 68. If the above MSB is "1", the weight corresponding bit group output from the weight corresponding bit group holding memory 61a is output onto the bus 68.

Also in the improved min-max arithmetic circuit of FIG. 8, the min-max arithmetic unit composed of the min-max detection circuits 41 to 49 and the grade holding registers 31 to 39 is changed to the same one as shown in FIG. As a result, the configuration can be changed so that the grades and weighting factors of the rearranged input labels are output on the grade bus 51 in descending order.

As described above, in order to reduce the amount of hardware and the processing speed, the exception processing is performed for the zero grade. However, when there is a margin in the amount of hardware and the processing speed, such a configuration may be excluded.

Further, it is possible to set a predetermined threshold value larger than zero and to target grades below the threshold value as exception processing targets.

Further, an example of using eight kinds of weighting factors of 1/8 to 8/8 has been described. However, eight types of weighting factors, 0/8 to 7/8, or an appropriate number of appropriate steps can be used.

Further, the min-max detection circuits 41 to 49 shown in FIG.
The configuration in which the latter part including the holding registers 31 to 39 is installed corresponding to each output channel is illustrated. However, if the increase in computation time is acceptable, a single min-max detection circuit and a holding register are installed for multiple output channels, and this is shared by staggering the time for each output channel. It is also possible to reduce the amount of hardware in a part.

Further, in order to realize high-speed processing of the entire fuzzy inference, the rearrangement circuit and the grade arithmetic circuit in the preceding stage are connected in cascade, and the grade arithmetic operation and the rearrangement of the already-calculated grade are pipelined. The configuration to be executed is illustrated. However, when such high speed is not required, a buffer memory may be installed between the rearrangement circuit and the grade calculation circuit, and the rearrangement may be started after all the grade calculations are completed. it can.

In the min-max operation circuit shown in FIG. 8, the output signal line group of the rule ROM 20 and the output signal line group of the weight corresponding bit group holding memory 61a are connected by wire or, and the label code or the weight coefficient code is connected. M
The corresponding bit group selection circuit 62 can be omitted by changing the output signal group of the memory that does not output according to SB to the high impedance state. Figure 1
The corresponding bit group selection circuit 62 can be omitted by adopting the same configuration for the min-max operation circuit.

In the min-max operation circuit shown in FIG. 8, the rule memory 20 for holding the rule-corresponding bit group relating to the deterministic rule is constituted by the ROM, and the weight-corresponding bit-group holding memory 61a is provided later. The case where the RAM is used to allow rewriting is illustrated. However, if the rule-corresponding bit group and the weighting coefficient-corresponding bit group are held in the address area separated by the MSB of the label code and the weighting coefficient code on a single RAM, the ROM and the corresponding bit-group selecting circuit 62 are arranged. It can be omitted.

[0116]

As described in detail above, the fuzzy inference min-max operation circuit according to the present invention collectively collects the input labels included in the antecedent parts of all rules in order of magnitude of grade. Since the arrangement is rearranged, there is an advantage that the waste of repeating the magnitude comparison of the same grade for each rule is omitted and the processing time is significantly shortened.

In addition, min- of fuzzy inference according to the present invention
The max operation circuit sets the weighting factor given to each rule to the grade of the input label included in the antecedent part of that rule.
Since the configuration approximates by n calculation and introduces the concept of the bit group corresponding to the weight, there is an advantage that the weight coefficient can be easily set and the once set weight coefficient can be easily changed according to the operation status of the control system. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a min-max operation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the configuration of the min-max detection circuit 41 of FIG.

FIG. 3 is a circuit diagram showing an example of the configuration of the min detection circuit of FIG.

FIG. 4 is a block diagram showing an example of a configuration of a weight corresponding bit group invention circuit 61 of FIG.

FIG. 5 is a circuit diagram showing a partial configuration of another embodiment of the present invention.

FIG. 6 is a circuit diagram showing a part of the configuration of still another embodiment of the present invention.

7 is a block diagram showing an example of a preferred configuration of an input label rearrangement circuit 10 of FIG. 1. FIG.

FIG. 8 is a block diagram showing a configuration of a min-max operation circuit according to still another embodiment of the present invention.

9 is a rearrangement circuit 1 for input labels and weighting factors in FIG.
8A is a conceptual diagram showing an example of initial values set in a grade register and a label register of each stage when 0a is realized by the circuit shown in FIG. 7.

FIG. 10 is a conceptual diagram for explaining the concept of the present invention in which the input labels included in the antecedent part of each rule are replaced in the order of the grade.

[Fig. 11] Fig. 11 is a conceptual diagram for explaining the concept of an encoding rule in the present invention.

[Fig. 12] Fig. 12 is a conceptual diagram for explaining the concept of an encoding rule in the present invention.

FIG. 13 is a conceptual diagram for explaining the concept of a rule corresponding bit group held in the rule memory in the present invention.

[Fig. 14] Fig. 14 is a conceptual diagram for explaining the concept of a rule-corresponding bit group rearranged in order of magnitude of input label grade and a coding rule modified by exchanging input labels.

FIG. 15 is a conceptual diagram for explaining the concept of a weight corresponding bit group of the present invention.

[Explanation of symbols]

 10 Grade rearrangement circuit 10a Grade and weight coefficient rearrangement circuit 20 Rule ROM (rule memory) 31 to 39 Grade holding register 41 to 49 min-max detection circuit 51 Grade bus 52 Label code bus 61 Weight corresponding bit group generation circuit 61a Weight corresponding bit group holding memory 62 Corresponding bit group selection circuit 63 Weight coefficient output circuit 64 Comparison circuit

Claims (16)

[Claims] 1. Validating whether each rule includes each input label in each antecedent part according to a predetermined array defined for each input label included in each antecedent part of each rule of fuzzy inference. A coding rule for displaying with invalid bits is defined for each rule, and it is determined by the valid / invalid bit group whether or not each input label is included in each coding rule defined in this way and arranged according to a predetermined array. The rule-corresponding bit group shown is defined, and each rule-corresponding bit group thus defined is held at an address designated by an identification code of the corresponding input label (hereinafter, referred to as "label code") The rule memory that holds the conversion rules across multiple addresses, and the grade of the input label calculated for each input label After rearranging in accordance with the order of magnitude with the label code, the grade of the input label after the rearrangement is output in ascending or descending order and the corresponding label code is supplied as the read address of the rule memory, thereby the rule corresponding bit group. Input label rearranging means for outputting the corresponding ones, weighting coefficient output means for outputting the weighting coefficients assigned to each rule of fuzzy inference in ascending or descending order, and the weights assigned to each rule of the fuzzy inference Weight-corresponding bit group generating means for holding a coefficient and generating a weight-corresponding bit group for each rule indicating whether or not the weight coefficient being held is equal to the weight coefficient output from the weight coefficient output means And the input label grade output from the input label rearranging means and the weighting factor. Comparing the magnitude with the weighting coefficient output from the force means, and comparing the rule-corresponding bit group output from the rule memory and the weight-corresponding bit group generated by the weight-corresponding bit group generating means in accordance with the comparison result. Selection means for selecting one of the grade of the input label output from the input label rearranging means and the weight coefficient output from the weight coefficient output means, and one of the output labels of the fuzzy inference. The grade or weight of the input label, which is installed correspondingly and is selected by the selecting means based on the valid bit that appears first or last in the rule corresponding bit group or the weight corresponding bit group selected by the selecting means. Find the information about the smallest of the coefficients for each rule contained in this output label, and Based on information about the values to detect the largest of these minimum values as min-max calculation results for each output label min-max
Fuzzy reasoning mi which is characterized by having a detection means.
n-max operation circuit. 2. The fuzzy inference according to claim 1, further comprising means for detecting a predetermined number of min-max operation results detected by each of the min-max detection means in descending order. min-max operation circuit. 3. The min-max arithmetic circuit for fuzzy inference according to claim 2, wherein the predetermined number is 2. 4. The input label rearranging means according to claim 1, further comprising means for outputting rearranged input labels in ascending order, and the weighting coefficient output means outputs the weighting coefficients in ascending order. The min-max detection means is selected by the selection means included in the output label based on the effective bit that first appears in the rule corresponding bit group or the weight corresponding bit group selected by the selecting means. Of fuzzy inference, characterized in that it has means for detecting, for each rule, information about the minimum of the input label grades or weighting factors.
n-max operation circuit. 5. The input label rearranging means according to claim 1, further comprising means for outputting the rearranged input labels in descending order, and the weighting coefficient output means outputs the weighting coefficients in descending order. The min-max detection means is selected by the selection means included in the output label based on the last valid bit in the rule-corresponding bit group or the weight-corresponding bit group selected by the selecting means. Of fuzzy inference, characterized in that it has means for detecting, for each rule, information about the minimum of the input label grades or weighting factors.
n-max operation circuit. 6. The input label rearranging means according to claim 1, wherein the grade of each input label of the rearrangement target that is equal to or higher than a predetermined threshold is a target of the rearrangement and output, and the threshold is set. For input grades of less than, the corresponding rearrangement bit group is output by excluding the rearrangement and output according to the instruction signal indicating that and supplying the corresponding label code as the read address of the rule memory. Exception processing means, the min-max detection means, during the rearrangement corresponding to the effective bit appearing in each coding rule output from the rule memory at the time of rearrangement of the input label by the input label rearrangement means The minimum value at the time of output of the input label by the input label rearranging means only when the grade of the input label of the min-max calculation circuit fuzzy inferring characterized by comprising exception handling means for enabling the function output. 7. The min-max operation circuit for fuzzy inference according to claim 6, wherein the predetermined threshold value is a minimum finite value that can be processed by the min-max operation operation circuit. 8. The input label rearranging means according to claim 1, wherein the calculated input label grades are supplied to the input label rearranging means in the order of calculation by the grade calculating means in the preceding stage. A fuzzy inference min-max arithmetic circuit characterized in that the grade arithmetic means in the preceding stage operates in a pipeline manner. 9. The input label rearrangement circuit according to claim 1, wherein the input label rearrangement circuit comprises a plurality of grade registers arranged in a column and holding a predetermined initial value by initialization, and input labels installed corresponding to these grade registers. The first operation of forming a data transfer path from the grade bus in which the grade appears to the corresponding grade register, the second operation of forming a data transfer path from the grade register of the adjacent stage to the corresponding grade register, and any one of the above. Grade transfer path forming means that is controlled to execute any one of the non-operations that do not form the data transfer path, label code registers arranged in a column corresponding to the grade registers, and these label codes.・ Label code that is installed corresponding to the register and the label code appears A first operation for forming a data transfer path to a corresponding register code register, a second operation for forming a data transfer path from a label code register of an adjacent stage to a corresponding label code register, and any of the above data transfer paths A label code transfer path forming means that is controlled to execute any one of non-operations that are not formed, and a grade code transfer path forming means and a label code transfer path forming means, respectively, for instructing each operation. A plurality of transfer control circuits installed corresponding to each other, each transfer control circuit determining a size relationship between a grade being held in a corresponding grade register and a grade appearing on the grade bus. Circuit, the result of the size judgment of its own stage by this size judgment circuit, and the size of the adjacent stage which is similarly performed by the size judgment circuit in the transfer control circuit of the adjacent stage. A logic circuit for issuing a selection command for the operation to the corresponding grade transfer path forming means and label code transfer path forming means based on a combination with the determination result, and the logic circuit comprises: a. If the size judgment result of the self-stage is the first result and the size judgment result of the adjacent stage is the second result opposite to this, the corresponding transfer path forming means is instructed to perform the first operation. Output a signal to perform b. If the magnitude judgment result of the self-stage is the first result and the magnitude judgment result of the adjacent stage is the same first result, the second operation is performed on the corresponding transfer path forming means. Outputs a commanding signal, c. If the size determination result of the self-stage is the second result, the signal for instructing the non-operation is output to the corresponding transfer path forming unit regardless of the size determination result of the adjacent stage. A min-max arithmetic circuit for fuzzy inference. 10. It is enabled / disabled whether each rule includes each input label in each antecedent part according to a predetermined array defined for each input label included in each antecedent part of each rule of fuzzy inference. A coding rule for displaying with invalid bits is defined for each rule, and it is determined by the valid / invalid bit group whether or not each input label is included in each coding rule defined in this way and arranged according to a predetermined array. The rule-corresponding bit group shown is defined, and each rule-corresponding bit group thus defined is held at an address designated by an identification code of the corresponding input label (hereinafter, referred to as "label code") A rule memory that holds the generalization rules over a plurality of addresses, and whether or not a weighting factor is assigned to each rule corresponds to each rule. Bit-corresponding bit group expressed in the same format as the bit group, and a weight-corresponding bit group holding memory that holds the address corresponding to the weight coefficient code for identifying the weight coefficient, and is calculated for each input label. After rearranging the input label grade and the weighting factor assigned to each rule according to the order of magnitude with the corresponding label code or weighting factor code, the rearranged input label grade and weighting factor are sorted in ascending order. Alternatively, the corresponding label code or weight coefficient code is output as a read address of the rule memory or the weight corresponding bit group holding memory to output the corresponding one of the rule corresponding bit group or the weight corresponding bit group. Input label and weight coefficient rearrangement means, and each output label of the fuzzy inference And output from the rearrangement means of the input label and the weighting coefficient based on the effective bit that appears first or last in the rule corresponding bit group or the weight corresponding bit group read from each memory. Information about the minimum of the grades or weighting factors of the input labels that are included in this output label for each rule, and the maximum of these minimum values is detected based on the information about the minimum value that is detected for each rule. A min-max operation circuit for fuzzy inference, comprising min-max detection means for detecting an object as a min-max operation result for each output label. 11. The fuzzy inference according to claim 10, further comprising means for detecting a predetermined number of min-max operation results detected by each of the min-max detection means in descending order. min-max operation circuit. 12. The fuzzy inference min-max operation circuit according to claim 11, wherein the predetermined number is 2. 13. The input label and weighting factor rearrangement unit according to claim 10, wherein the rearrangement and output target is a target of rearrangement and output for grades of each input label to be rearranged that are equal to or more than a predetermined threshold value. Then, with respect to the grade of the input label less than the threshold value, the corresponding rule corresponding bit is excluded by the rearrangement and output according to the instruction signal indicating that and the corresponding label code is supplied as the read address of the rule memory. An exception processing unit for outputting a group, wherein the min-max detection unit is arranged in each of the coding rules output from the rule memory when rearranging the input label and the weight coefficient by the rearrangement unit of the input label and the weight coefficient. By the input label rearrangement means only when the grade of the input label in the rearrangement corresponding to the effective bit appearing in min-max calculation circuit fuzzy inferring characterized by comprising exception handling means for enabling said minimum value detecting function at the output of the input label. 14. The fuzzy inference min-max operation circuit according to claim 13, wherein the predetermined threshold value is a minimum finite value that can be processed by the min-max operation operation circuit. 15. The input label rearranging means according to claim 10, wherein the calculated input label grades are supplied to the input label rearranging means in a calculation order by a grade calculating means in a preceding stage. A min-max arithmetic circuit for fuzzy inference, characterized in that the grade arithmetic unit in the previous stage operates in a pipelined manner. 16. The input label and weight coefficient rearranging means according to claim 10, wherein a plurality of grade registers are arranged in a column and hold the weight coefficients or a predetermined initial value, and these grade registers correspond to these grade registers. First operation of forming a data transfer path from a grade bus in which a grade of an input label appears to a corresponding grade register, second operation of forming a data transfer path from a grade register at an adjacent stage to a corresponding grade register And a grade and weight coefficient transfer path forming means that is controlled to execute any one of the operation and the non-operation that does not form any of the data transfer paths, and the grade registers are arranged in columns corresponding to the grade registers. The code that holds the grades or weighting factors of the input labels currently held in the The first operation of forming a data transfer path from a label register and a label code bus installed corresponding to these code registers, in which the label code appears, to the corresponding code register, Code transfer path forming means controlled to execute one of a second operation of forming a data transfer path to a corresponding code register and a non-operation of forming no data transfer path; A plurality of transfer control circuits installed corresponding to each of the grade and weight coefficient transfer path forming means and the code transfer path forming means for instructing each of the operations. A magnitude determination circuit for determining the magnitude relationship between the grade or weighting coefficient held in the grade register and the grade appearing on the grade bus,
The corresponding grade and weight coefficient transfer path is based on a combination of the result of the size judgment of this stage by the size judgment circuit and the result of the size judgment of the adjacent stage which is similarly performed by the size judgment circuit in the transfer control circuit of the adjacent stage. And a logic circuit for issuing the operation selection command to the forming means and the code transfer path forming means, the logic circuit comprising: a. If the size judgment result of the self-stage is the first result and the size judgment result of the adjacent stage is the second result opposite to this, the corresponding transfer path forming means is instructed to perform the first operation. Output a signal to perform b. If the size determination result of the self-stage is the first result and the size determination result of the adjacent stage is the same first result, the second operation is performed on the corresponding transfer path forming means. Outputs a commanding signal, c. If the size determination result of the self-stage is the second result, the signal for instructing the non-operation is output to the corresponding transfer path forming unit regardless of the size determination result of the adjacent stage. A min-max arithmetic circuit for fuzzy inference.