JP2633161B2 - Min-max arithmetic circuit for fuzzy inference - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates an output label grade by performing a min-max operation on an input label grade generated in a fuzzy inference machine used for controlling various home appliances and vehicles. And a min-max operation circuit for fuzzy inference.

[0002]

2. Description of the Related Art Fuzzy control using fuzzy inference is being applied to a wide variety of existing controls such as control of various home appliances and vehicles. In the multi-fuzzy inference which is the core of the fuzzy inference, first, the degree of conformity (grade) between a plurality of fuzzy concepts on the input side included in the antecedent part of the fuzzy rule (rule) and the fact indicated by actual input data. Is calculated. Labels are added to the plurality of fuzzy concepts on the input side to identify each other, and thus each fuzzy concept is also referred to as an input label. Supported the rules for the grade of each input label calculated.
By performing the min-max operation, the grade of the output label for truncating the membership function of the output fuzzy concept (output label) included in the consequent part of each rule is calculated. Finally, defuzzification is performed to obtain a deterministic output from the centroid of the membership function of each output label truncated by the corresponding grade.

[0003] The contents of the above min-max operation will be described with a specific example. First, it is assumed that the following seven rules are defined. Rule (1) if A and B then X Rule (2) if B and C then X Rule (3) if E and F then X Rule (4) if G and M and N then X Rule (5) if C and D then Y rule (6) if H and I then Z rule (7) if J and K and L then Z where A to L included in the antecedent of each rule are input labels and X to X included in the consequent Z is an output label. In addition, the grades Ag to Lg of the calculated input labels A to L
Are Ag = 0, Bg = 0.06, Cg = 0.7, Dg = 0.55, Eg = 0.6, respectively.
5, Fg = 0, Gg = 0.45, Hg = 0.9, Ig = 0, Jg = 0, K
It is assumed that g = 0, Lg = 0.62, Mg = 0.2, and Ng = 0.

First, for each rule, a min operation is performed to select the smallest one of the grades of the input labels included in the antecedent part. For example, for rule (1), the input labels A and B are included in the antecedent, but the grades Ag and Bg are 0 and 0.6, respectively.
Since 6, the smaller grade Ag is selected.
Similarly, for rule (2), grade of input label B
Bg is selected, the grade Fg of the input label F is selected for the rule (3), and the grade Ng is selected for the rule (4).

Next, for a plurality of rules having a common output label, a max operation for selecting the largest one of the minimum grades of the min operation result is performed. That is, for each of the four rules (1), (2), (3), and (4) with a common output label, the minimum grade Ag obtained by the min operation
, Bg, Fg, and Ng, that is, the grade Bg is selected. A similar max operation yields the output label Y
And Z are also performed. For the output label Y, the grade Dg is the calculation result, and for the output label Z, the grade Ig = Jg = Kg = 0 is the calculation result.

In the fuzzy inference machine for control, in order to receive a plurality of input data such as speed, pressure, and temperature,
A plurality of input channels are provided, and a plurality of input labels are defined for each input channel. In addition, a plurality of output channels are provided for outputting a plurality of output data relating to opening / closing of a switch, opening of a valve, and the like, and a plurality of output labels are defined for each output channel. Accordingly, the total number of input label grades to be calculated is the number of input labels per input channel × 1 input channel, and the amount of data to be subjected to min-max calculation in the subsequent stage is considerably large.

Conventionally, the above-described control based on fuzzy inference has been mainly applied to low-speed control of home electric appliances and the like. However, such control is required to be relatively complicated and high-speed, such as vehicle drive control and suspension control. In order to apply to the technical field, it is necessary to drastically reduce the conventional processing time, typically by about three digits. The reduction of the calculation time is achieved by the grade calculation for the input label, the calculation of the output label grade by the min-max calculation for the calculated grade group, and the membership of the output label truncated by the calculated grade. It is necessary to realize each stage of defuzzification by calculating the center of gravity of the function while maintaining harmony.

[0008]

Conventionally, the min-max operation for the grade of an input label is realized by comparing the magnitude of the grade of an input label included in each antecedent for each rule. A typical example of a system for realizing the magnitude comparison by software processing is disclosed in Japanese Patent Application No. Hei 4-10133. However, such software processing requires a large number of magnitude comparisons to be repeated. There is a problem that it is difficult to improve the calculation speed. A typical example of a system for realizing the above-mentioned magnitude comparison by a hardware circuit is disclosed in Japanese Patent Application No. 2-159628 or the like. However, it is necessary to perform many comparison operations on input labels included in each rule. However, there is a problem that it is difficult to increase the speed, and it is difficult to reduce the manufacturing cost because the scale of the hardware circuit becomes large.

In a typical fuzzy inference,
Most of the input label grades subject to min-max operation are zero. For example, for each input channel, if each of the eight input label membership functions is defined such that only the nearest neighbors intersect, then each input channel will output two input labels with a non-zero grade. Is done. That is, 70 to 80% of the grades of the input label to be subjected to min-max calculation are grades of zero.
The majority of the zero grades (hereinafter referred to as “zero grades”) do not substantially affect the result of the min-max operation, and therefore, the grades of other input labels (hereinafter “non-zero grades”). Has a different specificity. However, in the conventional min-max operation, zero grade is processed in the same way as non-zero grade,
A large amount of useless processing is included, making it more difficult to improve the operation speed and reduce the amount of hardware.

Accordingly, it is an object of the present invention to provide a fuzzy inference system which achieves an increase in the operation speed and a reduction in the amount of hardware.
An object of the present invention is to provide an n-max operation circuit.

[0011]

A fuzzy inference min-max operation circuit according to the present invention for solving the above-mentioned problems of the prior art comprises: a judgment means for preliminarily judging a magnitude relation between grades of input labels related to fuzzy inference; Calculating means for executing a min-max calculation in accordance with the order of magnitude determined by the determining means. More specifically, validity / invalidity of whether each rule includes each input label in each antecedent part according to a predetermined arrangement defined for each input label included in the antecedent part of each rule of fuzzy inference is set. An encoding rule to be displayed in bits is defined for each rule, and a valid / invalid bit group of each input label (hereinafter, referred to as “rule corresponding bit group”) included in each of the encoding rules defined in this manner is input. Label identification code (hereinafter referred to as
A rule memory that holds each encoding rule over a plurality of addresses and in a predetermined order in the arrangement direction of each bit of each rule-corresponding bit group by retaining the encoding rule at an address designated by “label code”). Have.

Further, the fuzzy inference according to the present invention has a min-
The max operation circuit rearranges the grades of the input labels calculated for each input label together with the corresponding label codes in the descending order, and then rearranges the grades of the input labels or the rearrangement order of the input labels in descending order. Alternatively, there is provided an input label rearranging means for outputting a corresponding rule code as a read address of a rule memory and outputting a corresponding rule corresponding bit group by outputting the corresponding label code as a read address of the rule memory.

Furthermore, the fuzzy inference according to the present invention has a min-
A max operation circuit is provided corresponding to each encoding rule sequentially output from the rule memory, and the grade or rearrangement order of the input label output from the rearrangement means and the output from the rule memory. A minimum grade detecting means for obtaining a detection result regarding the minimum grade based on the first or last valid bit appearing in each encoding rule, and a corresponding output label installed corresponding to each output label as a consequent part A maximum grade detecting means for obtaining a detection result regarding the largest one of the minimum grades based on the detection result obtained by each of the minimum grade detecting means installed in correspondence with each rule.

[0014]

According to the present invention, the input labels included in the antecedent part of all rules are rearranged by the input label rearranging circuit in the order of the grade. As an example, assuming that the seven rules described above in relation to the description of the related art are defined and the grades of the input labels A to N included in each rule are the values described above, By rearranging the input labels included in the subject part in the order of the magnitude of the grade, a result as shown in FIG. 6 is obtained.

As described above, the input labels included in the antecedent part of each rule are spatially rearranged in descending order of the grade, so that the input label having the smallest grade can be arranged in the rightmost input label. For a plurality of rules that are labels (indicated by circles) and have a common output label, the input label that has the maximum value among the minimum grades of the min operation result is the label arranged on the leftmost side (double (Circled). In this way, by rearranging the input labels included in the antecedent part of each rule spatially in the order of the grade, the result of the min-max operation can be easily known from the arrangement order.

The rearrangement result shown in FIG. 6 is suitable for discrimination by humans, but is not suitable for mechanical discrimination. Therefore,
According to the present invention, from the viewpoint of facilitating automatic discrimination with a minimum amount of data, first, encoding of each rule defined in the system prior to the rearrangement of the input labels is performed. Is performed. The encoding of this rule predefines the arrangement order of all input labels defined in all input channels in the system, and for each rule, whether or not each input label is included, if This is realized by arranging information represented by valid bits (for example, “1”) and, when not included, by invalid bits (for example, “0”), in the same order as the arrangement order defined for the input labels.

In the example of FIG. 6, if the arrangement order in alphabetical order is defined for each input label from A to N, rule (1) is that only input labels A and B are included in the antecedent part. To include, the encoding rule that encoded this (1)
Is "110000000000000000" as shown in FIG.
0 ". Similarly, since rule (5) includes only the input labels C and D in the antecedent part, the encoding rule
(5) is "00110000000" as shown in FIG.
000 ".

Next, each of the above encoding rules is set in a predetermined order,
Preferably, two-dimensional arrays of valid / invalid bits as illustrated in FIG. 9 are obtained by arranging those having a common output label so as to be adjacent to each other. When the two-dimensional array of valid / invalid bits is vertically traced from bottom to top in FIG. 9, that is, when all encoding rules are scanned for an arbitrary input label, the input labels are arranged in a predetermined order. Whether or not the rule is included in the antecedent part of each of the arranged rules is represented by a bit array represented by a valid bit (“1”) when the rule is included and by a valid bit (“0”) when not included. Become.

Such an array of valid / invalid bits for one column is hereinafter referred to as a "bit group corresponding to the rule of each input label".
Called. For example, in the case of FIG. 9, the rule corresponding bit group of the input label A is “100000”, and the rule corresponding bit group of the input label N is “0001000”.
Such a rule corresponding bit group of each input label is previously stored in a memory such as a ROM accessed by the identification code (a to n) of each input label. Such a memory is hereinafter referred to as a “rule memory” or “rule ROM”, and an identification code of an input label for specifying a read address of the rule memory is referred to as a “label code”. As described above, according to the present invention, a rule is encoded, and this encoding rule is stored as a rule-corresponding bit string in a rule ROM having an address designated by a label code.

Further, when the rule-corresponding bit group of each input label shown in FIG. 9 is spatially rearranged according to the order of the grade of each input label, the result shown in FIG. 10 is obtained. The spatial arrangement in FIG. 10 corresponds to the spatial arrangement in FIG. 6 described above. In the rearrangement from FIG. 6 to FIG. 10, even if the arrangement order of the input labels included in the respective antecedents of a certain rule or its encoding rule is changed or replaced, the contents of the rule or its encoding rule are changed. Is assumed to be unchanged at all. this is
The rule if A and B then X is obtained by changing the order of the input labels in the antecedent part.
This is because even if it is transformed into A then X, the contents of the rule are not changed.

As described above, by spatially rearranging the bit groups corresponding to the rules of each input label in the descending order of the grade of the input label, it is possible to obtain the arrangement of FIG. 10 which is easily mechanically determined. That is, the most significant bit ("1") located at the rightmost position is detected for each of the encoding rules included in FIG. 10, and then, for each of one or a plurality of encoding rules commonly including an arbitrary output label has been detected. Of the rightmost valid bits of the input bit, the input label corresponding to the leftmost valid bit is detected, and finally, the grade of the detected input label is selected. , Which is the result of the min-max operation for the output label.

As described above, a min-max operation can be performed based on a spatially arranged rule-corresponding bit group. The configuration of such a spatial min-max operation is the same as that of the present application. It is disclosed in other patent applications filed before and after. The min-max operation circuit of the present invention performs a time-series min-max operation using the order of appearance of the rule corresponding bits. Regardless of whether a spatial or time-series method is adopted, the processing time is greatly reduced by a configuration in which input labels are once rearranged in order of grade. That is, according to the conventional min-max operation circuit, since the magnitude of the grade of the input label included in the antecedent part is compared for each rule, for example, the rule including the input labels A and B in the antecedent part is used. If there are ten, the magnitude comparison of each grade is repeated for ten rules, that is, ten times. On the other hand, in the min-max operation circuit of the present invention, even if there are any number of rules including the input labels A and B in the antecedent part, the magnitude comparison of each grade only needs to be performed once. ,
The operation time is greatly reduced.

The input label rearrangement circuit necessary for the time-series min-max operation temporarily rearranges the grades of the input labels calculated for each input label together with the corresponding label codes in the order of magnitude, and then re-arranges them. By supplying corresponding label codes as read addresses of the rule memory in accordance with the order of the grade of the rearranged input labels, the corresponding rule corresponding bit groups are sequentially output. Focusing on each bit position of the rule-corresponding bit group sequentially output from the rule memory, each encoding rule held in the rule memory appears in a time-series manner while being deformed by the replacement of the input label.

Then, in the min-max operation circuit of the present invention,
A minimum grade detection circuit for detecting the minimum grade included in each encoding rule is provided at each bit position of the rule corresponding bit group sequentially output from the rule memory.
Each minimum grade detection circuit firstly sets the order of the grade and rearrangement of the input label output from the input label rearrangement circuit, and in each encoding rule output from the rule memory,
Alternatively, a detection result regarding the minimum grade is obtained based on the last valid bit. That is, if the rule memory is accessed in ascending order of the input label grade,
The grade output from the rearrangement circuit together with the first valid bit of each encoding rule can be detected as the minimum grade. Conversely, if the rule memory is accessed in the descending order of the grade of the input label, the grade output from the rearrangement circuit together with the last valid bit of each encoding rule can be detected as the minimum grade.

Further, in the min-max operation circuit of the present invention, a maximum grade detection circuit is provided corresponding to each output label. Each maximum grade detection circuit is based on the detection result of the minimum grade obtained by each minimum grade detection circuit installed corresponding to each rule that includes each output label as a consequent part. Get.

The above-described min-max operation including rearrangement of the rule-corresponding bit group of each input label may be implemented by software or hardware. In addition, in the case of realizing by software and the case of realizing by a hardware circuit, a variety of concrete realizing methods can be considered. Hereinafter, typical examples of these specific realization methods will be described with reference to examples.

[0027]

FIG. 1 is a block diagram showing a configuration of a min-max operation circuit for fuzzy inference according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a grade of an input label and a label code in order of magnitude of the grade. An input label rearrangement circuit to be arranged, 20 is a rule ROM, 30 is a grade holding register group, 40 is a logic circuit group, 51 is a grade bus, 52 is a label code bus, and 53 is a valid flag signal line. For the sake of illustration, the latter part including the rule ROM 20, the grade holding register group 30, and the logic circuit group 40 is illustrated for only one output channel. That is,
The latter part has a number equal to the total number of output channels, for example, if the total number of output channels is 10, the same number of 1
Only 0 sets are installed.

On the grade bus 51, the grades of the input labels are arranged in the order of arrangement of the plurality of input channels in the preceding grade arithmetic circuit (not shown), and for each input channel in the order of arrangement of the plurality of input labels defined for the input channels. The operation is executed, and the grade of each input label of each input channel appears in the order of execution of the operation.
Assuming a typical system where the total number of input channels is 8 and the total number of input labels in each input channel is 9, a total of 72 input label grades will appear on grade bus 51.

The label code of the input channel / input label corresponding to the grade of the input label appearing on the grade bus 51 appears on the label code bus 52 simultaneously with the grade of the input label. The label code of each input channel / input label may be represented by a combination of the serial number of the input channel and the serial number of the input label included in this input channel, such as the third input label of the second input channel, Alternatively, all input labels arranged in the order of arrangement of input channels and in the order of arrangement of input labels defined for each channel may be represented by serial numbers assigned.

In a typical fuzzy inference, most of the input label grades appearing on the grade bus 51 are zero. For example, for each input channel, if each of the nine input label membership functions is defined such that only the nearest neighbors intersect, then each input channel will output two non-zero input label grades. You. That is, a total number of 7 for 8 input channels in total
Only 16 of the two input label grades are not zero, and the remaining 56 grades are zero grades (hereinafter referred to as "zero grades"). In this min-max operation circuit, the processing time is reduced and the circuit scale is reduced by executing an exceptional process for the zero grade which occupies most of the grade of the input label. As a part of this, from the grade arithmetic circuit of the preceding input label (not shown), a valid flag indicating that the operation result is not zero grade is output on the valid flag signal line 53 if the operation result is zero grade. You.

First, in the input label reordering circuit 10, the input label grades including a large number of zero grades appearing sequentially on the grade bus 51 are discarded by the input label and rearranged according to the size order of the non-zero grades. The array is executed. This input label rearrangement circuit 10 is basically composed of two groups of data registers arranged in tandem, and one of the groups of data registers holds the grade of the input label and the other group of data registers. The group holds a corresponding label code.

The discarding of the zero grade and the rearrangement of the grades of the input labels in accordance with the order of the magnitude of the non-zero grade are performed on the grade bus 51 only when a valid flag appears on the valid flag signal line 53. This is realized by holding the appearing grade in one of the data register groups of each system together with the corresponding identifier while selecting the holding destination according to the magnitude relation. Such an input label rearrangement circuit 1
0 can be realized based on an appropriate technique, but preferably, the processing time can be reduced by using a circuit disclosed in “Data Sorting Circuit” filed by the present applicant before and after this application. It is particularly suitable in this respect. The details of the input label rearrangement circuit will be described later.

When the rearrangement of the grade and the label code by the input label rearrangement circuit 10 is completed, the initial value zero is set for all of the grade register groups 30.
In accordance with the consecutive addresses supplied from the address counter 54, the grades of the rearranged input labels are changed from the input label rearrangement circuit 10 to the grade bus 51 in ascending order.
Is output to At the same time, the corresponding label code is output from the input label rearranging circuit 10 onto the label code bus 52. The label code output on the label code bus 52 is supplied to an address input terminal of the rule ROM 20 so that a rule-corresponding bit group held at this address is output from the rule ROM 20 to the logic circuit 40.
Is output to

The logic circuit 40 that receives the rule-corresponding bit group output from the rule ROM 20 includes nine partial logic circuits 41, 42,..., 49 provided corresponding to the nine output labels. It is configured. Each partial logic circuit has the same number of minimum grade detection circuits 410 and 42 as the maximum number of rules that can be defined for the corresponding output label.
OR gates 411 and 421 which create and output a logical sum of 0... 490 and each output of these minimum grade detection circuits.
... And a maximum grade detection circuit composed of 491.

The minimum grade detecting circuit 410 outputs a corresponding encoding rule appearing at a corresponding rule bit position among the rule corresponding bits sequentially read from the rule ROM 20 when the input label rearrangement circuit 10 outputs the grade of the input label. It is configured to detect the first valid bit "1" that appears therein and output "1" to the input terminal of the OR gate 411. That is, even if the second and third valid bits “1” appear in the corresponding encoding rule, “1” is not output from the corresponding minimum grade detection circuit 410. The configuration of the minimum grade detection circuit 410 will be described later in detail.

When the rearrangement of the input labels by the input label rearranging circuit 10 is completed, the grade register 31
To 39 are initialized to zero. Thereafter, the input label rearranging circuit 10 sequentially outputs rearranged input labels and label codes in ascending order of the grade. The label code output from the input label rearranging circuit 10 onto the bus 52 is supplied to an address input terminal of the rule ROM 20, and the rule-corresponding bit groups held in the rule ROM 20 are output in the descending order of the input label grade. Each bit constituting each rule-corresponding bit group, that is, each encoding rule is included in each minimum grade detection circuit 410-410.
490.

Each minimum grade detection circuit 410 detects the first valid bit “1” appearing in the corresponding coding rule sequentially read from the rule ROM 20 and outputs “1” to the OR gate 411. With this, OR gate 41
From “1”, “1” for instructing data holding to the corresponding grade register 31 is output. The grade register 31 that has received the holding instruction holds the grade of the input label appearing on the grade bus 51. That is, each minimum grade detection circuit 410 causes the data register 31 to hold the grade of the one or a plurality of input labels included in the antecedent part of the corresponding rule that is first output from the input label rearrangement circuit 10. Perform the function.

Here, considering that the grades of input labels appear on the grade bus 51 in ascending order, the input held in the register 31 based on the first valid bit appearing in the corresponding coding rule. The label grade is the smallest one contained in the antecedent part of the corresponding encoding rule. That is, each of the unit logic circuits 410 performs a part of the function for implementing the min operation for each input grade included in the antecedent part of the corresponding rule.

As for the grade register 31 installed corresponding to the first output label, the minimum grade detection circuit 410 installed corresponding to each rule sharing this output label outputs "1". Is output, the grade of the input label appearing on the grade bus 51 is held. At this time, the grade of the input label already held is replaced with the grade of the newly held input label. Therefore, when the output of the grade of the input label from the input label rearranging circuit 10 is completed, the grade of the input label held in the grade register 31 is "1" lastly output from each of the minimum grade detection circuits 410. It is nothing but the grade of the smallest input label contained in the corresponding rule. Here, considering that the grade of the input label outputted on the grade bus 51 appears later as the grade becomes larger, the input label held in the data register 31 by the last valid bit appearing in each encoding rule is considered. The label grade is equal to the maximum value (max) of the minimum values (min) of the input label grades detected for each encoding rule included in the corresponding output label.

That is, each of the minimum grade detection circuits 410 alone performs a part of the function of the min operation for each input grade included as a prerequisite part in each rule, and is installed in parallel with each other and each output terminal is provided. With the overall configuration of logical addition by the OR gate 411,
Part of the function of the min-max operation. This mi
The remaining part of the n-max operation function depends on the function of the input label grade rearrangement circuit 10 in which the smaller the grade on the grade bus 51, the earlier the output of the input label grade. This min-max operation function is also applicable to the partial logic circuits 42 to 49 installed corresponding to the other output labels of this output channel, and also to each output label for all other output channels not shown. The same applies to all other partial logic circuits installed.

In this way, the grade rearrangement circuit 10
, When a total of 16 non-zero grades are output, the grades of each input label of each input channel are compared.
The grade of each output label of each output channel calculated based on the min-max calculation is held in the grade register.
The grade of each output label of each output channel held in the grade register is transferred to the subsequent defuzzification circuit via the grade bus 51, where it is subjected to defuzzification processing by the center of gravity method or the like. The output data is output to each output channel.

Each minimum grade detection circuit is represented by a minimum grade detection circuit 410 as shown in FIG.
Flip-flop 411a and 2-input AND gate 411
b) and a JK flip-flop 411
c, 411g, switch 411d, and logic gate 411
e, 411f. The main operation of the minimum grade detection circuit is to share a part of the function of the min-max operation during the output of the grade of the rearranged input label, as described above. First, a differentiating function of outputting "1" for only a half clock period when the output of the OR gate 411f of the preceding stage changes from "0" to "1" by the subsequent stage including the D flip-flop 411a and the two-input AND gate 411b. Has been realized. On the other hand, the part consisting of the JK flip-flop 411g and the OR gate 411f in the preceding stage is for inhibiting the function of the latter stage with respect to the non-use rule. In addition, in the part consisting of the JK flip-flop 411c and the OR gate 411f in the former stage, an invalid input label not included in the corresponding rule appears during the rearrangement of the input label grade by the input label rearrangement circuit 10, If the valid input label included in the rule is zero grade, or min-max
After the first valid bit specified in the antecedent part of each rule appears in the calculation process, that is, after the minimum grade of the rule appears, the function of the latter stage is stopped.

One input terminal of the NOR gate 411e in the preceding stage is connected to the input label rearranging circuit 10 to determine whether the input label rearranging circuit 10 is executing rearrangement or outputting the grade of the arranged input label. In this case, a signal indicated by "0" is input, and in the latter case, a signal indicated by "1" is input. To the other input terminal of the NOR gate 411e, "1" is input from the valid flag signal line 53 of FIG. 1 if the grade of the input label to be rearranged is zero, and "0" is input if it is not zero.

First, the above-described input label rearrangement circuit 10
Prior to the start of the rearrangement, the initial value "1" is set in the JK flip-flop 411g and the initial value "0" is set in the JK flip-flop 411c based on the preset signal. Thereafter, when rearrangement is started by the input label rearrangement circuit 10, the rule ROM 2
0 is accessed while receiving the label code appearing on the label bus 52 at the address terminal. During the rearrangement of the input labels, "0" is continuously input to one input terminal of the NOR gate 411e as described above.

When "0" indicating that the grade of the input label on the grade bus 51 is not zero appears at the other input terminal of the NOR gate 411e, the output of the NOR gate 411e becomes "1", and the switch 411d is turned on in the figure. The state is switched to the state shown by the dotted line. In this state, the input terminal IN
When the effective bit “1” in the encoding rule appears in
The state of the K flip-flop 411g is inverted from the initial value “1” to “0”. On the other hand, when "1" indicating that the grade of the input label is zero appears at the other input terminal of the NOR gate 411e when the valid bit "1" appears at the input terminal IN, the output of the NOR gate 411e becomes " It becomes 0, and the switch 411d is switched to the state shown by the solid line in the figure, and the state of the JK flip-flop 411c is inverted from the initial value "0" to "1". Therefore, the output of the OR gate 411f at the time when the rearrangement of the input labels is completed is determined by the case where it is specified that the grade of the corresponding input label is not zero grade for all the valid bits “1” in the encoding rule. 0, and in other cases, that is, when at least one zero-grade input label is specified for the valid bit “1” in the encoding rule, or when the valid bit “1” is included in the encoding rule. If no one appears, it is kept at the initial value "1".

Thereafter, when the output of the label code corresponding to the grade of the rearranged input labels from the input label rearranging circuit 10 is started, the switch 411d is switched to the state shown by the solid line in FIG. The valid / invalid bit of the coding rule read from the JK flip-flop 411c through this switch 411d.
It is supplied to the input terminal. At the start of this output, J
If the states of the K flip-flops 411c and 411g are both "0", "0" is supplied to the inverting input terminal of the two-input AND gate 411b, so that the valid / invalid bit of the encoding rule is initially "1". Output terminal OU when
"1" is output from T over a half clock period,
The grade of the input label appearing on the grade bus 51 is held in the grade register 31.

On the other hand, JK flip-flop 41
If 1c or 411g is held at “1” at the start of the output of the grade of the rearranged input label,
Since the "1" signal is continuously supplied to the inverting input terminal of the two-input AND gate 411b, "1" is not output from the output terminal OUT even if the rule corresponding bit becomes "1".
That is, the operation at the time of outputting the grade of the input label by the minimum grade detection circuit 410 is prohibited. As described above, the preceding part in the minimum grade detection circuit 410 in FIG. 2 is configured such that the grade of any of the input labels included in the antecedent part of the corresponding encoding rule is zero, or that the encoding rule is If the rule is an unused rule that does not include any input label, the minimum grade detection circuit is prohibited from participating in the min operation when re-outputting the grade of the input label. Perform the function. The necessity of such a function is based on the following three reasons.

The first reason is that, in the input label rearranging circuit 10 in the preceding stage in this embodiment, the zero-grade discarding of the input label included in the corresponding rule is performed in parallel with the rearrangement of the non-zero-grade input label. Performed, but the original min-ma
According to the principle of x operation, the zero grade included in such a rule cannot be simply discarded or ignored. That is, according to the original min-max operation, the zero-grade of the input label included in the rule is also subject to the min operation, like other non-zero grades, and the rule that includes this zero-grade input label in the antecedent part Must yield a min operation result of zero.

Therefore, if such a zero grade is simply discarded in order to simplify the input label rearrangement circuit 10, the smallest one among the other non-zero grades becomes the min operation result for the rule, and Occurs.
Therefore, in order to prevent such an error, if the zero grade included in the corresponding rule is discarded,
When calculating the max
1-bit information for commanding to inhibit min operation is stored. This is because the contents of each grade register are initially set to zero, and the inhibition of the min operation based on the 1-bit information produces the same result as holding the zero grade.

The second reason is that "the fuzzy inference grade arithmetic circuit" which is separately performed by the present applicant before and after this patent application.
In the case of using the grade arithmetic circuit disclosed in the patent application entitled “Unassigned”, when the input label is rearranged by the input label rearrangement circuit 10, the input label grade defined by the Π-type membership function becomes invalid during the operation. Data may be output. In such a case, min-max
It is necessary to prohibit the operation, and for such a reason, the min operation is prohibited by the information of one bit.

The third reason is that among the rules contained in an arbitrary output label, the rule that is not used at all is mi
This is because it needs to be excluded from the n-max calculation. This is necessary, for example, when a specific rule held in the rule memory is invalidated later or when the effect on the calculation result is reduced by appropriate weighting. As a discriminator of this valid rule, the JK flip-flop 41 in FIG.
1 g is added.

By the way, at the end of the min-max operation at the time of re-output, the grade of the non-zero output label is held in the corresponding grade register of each output channel, for example, each of nine grade registers per output channel. Is done.
Up to nine output label grades per output channel are read out to a subsequent defuzzification circuit and used to truncate the membership function of the corresponding output label. In order to shorten the operation time for this defuzzification, for the output label, unlike the case of the input label, the corresponding membership function was replaced by a line of unit height set at the position of the center of gravity. The singleton data is used, and the singleton data is truncated according to the grade of each output label, thereby obtaining singleton data having a height equal to the grade of the output label.

According to a patent application entitled "Fuzzy Inference Defuzzification Method" filed separately by the present applicant, in order to further reduce the defuzzification operation time, all the truncated singleton data is used. There is disclosed an approximation method in which only two singleton data are selected in ascending order of height and the center of gravity is calculated using these data instead of performing the center of gravity calculation. In order to perform such an approximation method, it is necessary to select only two output labels from the nine output labels held in the nine grade registers 31 to 39 in descending order. If this selection is to be made in the subsequent defuzzification circuit, a large number of comparison operations will be required, and the processing time will be prolonged. Hardware is required.

Such a problem can be solved by selectively holding only the largest one and the next largest among the output label grades of the operation result in parallel with the above-described min-max operation. FIG. 3 shows a configuration of a selection and holding circuit according to another embodiment of the present invention, which can selectively hold the grade of the output label.

The selective holding circuit shown in FIG. 3 is obtained by replacing the nine grade registers 31 to 39 of FIG. 1 with the elements shown in FIG. 1. In order to clarify the correspondence with FIG.
The nine OR gates 411 to 491 and the grade bus 51 which are common to FIG. 1 are illustrated so as to overlap with FIG. The selective holding circuit includes a grade register 1 connected in cascade.
11 to 113, label registers 1 also connected in cascade
21 to 123, a match determination circuit 114 for determining the match between the grades held in the registers, a match determination circuit 124 for determining the match between the labels held in the registers, and the like.

The outputs of the OR gates 411 to 491 are input to the label register 121 as they are, and their logical sum is input to the D-type flip-flop 132 via the OR gate 131. Therefore, the OR gates 411 to 49
When the output of any one of "1" becomes "1", the D-type flip-flop 132 is set to "1", the grade appearing on the grade bus 51 is held in the grade register 111, and the outputs of the OR gates 411 to 491 are output. It is held in the label register 121. However, the label here is different from the identification code of the input label for accessing the rule ROM 20 in FIG.
The input labels are indicated by bit positions where “1” is set. The grade held in the grade register 111 is compared with the content of the grade register 112 in the comparing circuit 114, and the label register 121
Is compared with the contents of the label register 122.

A. When the contents of the label registers 121 and 122 do not match, and the contents of the grade registers 111 and 112 do not match, the contents of the grade register 112 are
3 and the contents of the grade register 111 are transferred to the grade register 112. At the same time,
The logical product of the contents of the label register 122 and the inverse of the contents of the label register 121 is transferred to the label register 123 through the switch 127 and the AND gate 128, and the OR gate 126 is added to the label register 122.
The contents of the label register 121 are transferred through.

B. When the contents of the label registers 121 and 122 do not match, but the contents of the grade registers 111 and 112 match, the logical product of the contents of the label register 123 and the inverted contents of the label register 121 is determined by the switch 127 and the AND gate 128. Then, the logical OR of the contents of the label register 121 and the contents of the label register 122 is transferred to the label register 122 through the OR gate 126.

C. When the contents of the label registers 121 and 122 match but the contents of the grade registers 111 and 112 do not match, the contents of the grade registers 111 are the grade registers 11
2

D. If the contents of the label registers 121 and 122 match and the contents of the grade registers 111 and 112 also match, no operation is performed.

In the above A, the maximum value of the grades that have appeared on the grade bus 51 so far is the grade register 1
In this case, the grade that has been the maximum value is transferred from the grade register 112 to the grade register 113 as the grade having the second largest value, and the content of the grade register 111 is set as the new maximum value of the grade. The data is transferred to the grade register 112. In this way, the grade register 112 holds the maximum value of the grade that has appeared so far on the grade bus 51, and the grade register 113 has the grade of the second largest value that has appeared so far on the grade bus 51. Is held. The label registers 122 and 123 hold the labels corresponding to the maximum value of the grade and the grade having the second largest value. By transferring the label held in the label register 122 to the label register 123 while calculating the logical product of the inverted contents of the label register 121, the same label as the label newly held in the label register 122 is held in the label register 123. Is prohibited.

When the last grade has appeared on the grade bus 51, the grade registers 112 and 11
3 holds the maximum grade and the second largest grade of each output channel, and the label registers 122 and 123 hold the corresponding output labels.
The contents held in each register are read out and processed by the defuzzification circuit at the subsequent stage, so that definite output data is created.

FIG. 4 is a block diagram showing a part of the configuration of a min-max operation circuit for fuzzy inference according to another embodiment of the present invention, in which the same reference numerals as in FIG. 1 are used. The components are the same as those already described with reference to FIG. 1, and a duplicate description thereof will be omitted.

In this embodiment, the input label rearrangement circuit 10
When the rearrangement of the input labels is completed, the entry addresses in the rearrangement circuit 10 holding the respective grades are output on the bus 55 in the descending order of the grade as the rearrangement order. Each of the minimum grade detection circuits 510, 520,... Installed corresponding to each encoding rule read from the rule ROM 20 stores valid bits appearing in the corresponding encoding rule output from the rule memory 20. By keeping the rearrangement order of the input labels being output from the input label rearrangement circuit 10 to the bus 55 in synchronization, the last occurrence of the input label having the lowest grade in the corresponding coding rule, that is, the input label having the lowest grade It is composed of a register that holds the rearrangement order as a detection result. The maximum grade detection circuits 51, 52,... Provided corresponding to the respective output labels are the largest ones among the rearrangement orders held in the corresponding minimum grade detection circuits 510, 520,. Is selected and held.

After the output from the input label rearranging circuit 10 is completed, the maximum grade detecting circuits 51, 52,...
The rearrangement order stored in the input label rearrangement circuit 1 via the bus 55 is used as an entry address for reading.
0, and the grade of the input label to be selected as the result of the min-max operation for each output label is output on the grade bus 51.

Each of the minimum grade detection circuits 510 and 5
The two-input AND gate and flip-flop added to 20... Are additional circuits for exceptional processing for zero grade. That is, the input label rearrangement circuit 10
When a valid zero grade is appearing during the rearrangement, the output of the corresponding two-input AND gate goes high, and the subsequent flip-flop is set. Each of the minimum grade detection circuits to which the flip-flop is set is prohibited from holding the above-described rearrangement order in the register portion at the time of output from the input label rearrangement circuit 10. Further, the rearrangement order register corresponding to the rule in which the flip-flop is set is excluded from comparison targets in a subsequent max comparison operation.

FIG. 5 is a block diagram showing the configuration of the input label rearranging circuit 10 shown in FIGS. 1 and 4. Reference numeral 51 denotes a grade bus in which the grade of an input label output from a preceding grade arithmetic circuit (not shown) appears. , 52 are label code buses, and 53 is a signal line on which a valid flag appears as a write enable (WE) signal. However, in this example, the valid / invalid flag is inverted from the case described with reference to FIGS. 1, 2 and 4, and is "0" for zero grade and "1" for non-zero grade. 211,
212, 213 ..., 221, 222, 223 ...
Are data registers with selectors, each having a built-in selector and connected in cascade, and 231, 232, 2
33 ... are 2 in the data register with selector.
This is a group of selection control circuits arranged in cascade corresponding to each data register group with a selector for controlling the selection operation of the input selector.

Data register groups 211 and 211 with selector
12, 213... Are grade registers G
R and 2 arranged before the grade register GR.
And an input grade selector GS. One input terminal A of the grade selector GS is a grade bus 5
1, the other input terminal B is connected to the output terminal of the grade register GR in the data register with selector at the preceding stage, and the output terminal is connected to the grade register GR at the subsequent stage.
Is connected to the input terminal of Each of the data register groups with selectors 221, 222, 223,... Includes a label code register LR and a two-input label code selector LS arranged at a stage preceding the label record register LR. One input terminal A of the label code selector LS is connected to the label code bus 52, and the other input terminal B is connected to the output terminal of the label code register LS in the data register with selector at the preceding stage and output. The terminal is connected to the input terminal of the subsequent label code register LS.

Grade selector GS and label selector L
In both cases, S makes the input terminal A and the output terminal conductive when the selection command SA is high, makes the input terminal B and the output terminal conductive when the selection command SB is high, and selects the selection commands SA and SB.
Are low, neither input terminal A nor input terminal B is conducted to the output terminal. Note that a combination in which both the selection commands SA and SB are high is prohibited. .. Arranged in cascade correspond to the grade and the grade bus 5 held in the corresponding grade register.
1, a comparison circuit CMP for performing a magnitude comparison with a new grade appearing on the first circuit, a D-type flip-flop FF for retaining a magnitude comparison result by the comparison circuit, and a logic circuit including two AND gates A1 and A2. Have. The comparison circuit CMP stores the data Di stored in the grade register of its own stage.
Is compared with the grade DDn appearing on the grade bus, and when DDn ≦ Di, the output is raised to a high level.

First, before the grade of the input label begins to appear on the grade bus 51, the grade registers GR of the data registers 211, 212, 213,... With selectors of each stage are preset via the preset signal line RST. You. Preset grade registers G for each stage
R holds the upper limit value of the grade appearing on the grade bus 51, for example, the upper limit value [FF] _H if the grade is 8-bit unsigned data. Hereinafter, for convenience of explanation, the grade of the input label is 8-bit data, and the upper limit value set as the initial value is [FF] _H.

After completion of the preset, the grade of the input label calculated by the preceding grade calculation circuit (not shown) is output to the grade bus 51, and the label code corresponding to this grade is output to the label code bus 52. You. Only when the value of the grade output on the grade bus 51 is valid data other than zero, a write enable signal (WE) for instructing to retain the grade is supplied from the preceding stage grade arithmetic circuit to the valid flag signal line 53. Is output.

When the first non-zero grade DD1 appears on the grade bus 51 in synchronization with the rising edge of the clock signal (not shown), the selection control circuit 231 of each stage
In the comparison circuit CMP in 232, 233,..., The magnitude of the grade DD1 appearing on the grade bus 51 is compared with the grade Di held in the grade register GR. Since the grade DD1 appearing on the grade bus 51 is equal to or less than the maximum value [FF] _H of the grade,
The output of the comparison circuit CMP in the selection control circuit of each stage becomes high, and this high signal is held in the D-type flip-flop FF in the selection control circuit of each stage in synchronization with the falling edge of the clock signal. The judgment result of the own stage is DD1 ≦ D
A high signal for notifying the selection control circuit at the subsequent stage of i is output on the signal line S2.

In each stage of the selection control circuit, the signal line S2 from the preceding stage selection control circuit is supplied as a signal line S1 in its own stage to a logic circuit composed of AND gates A1 and A2. However, only the first-stage selection control circuit 231 does not have the previous-stage selection control circuit, and the low signal is constantly supplied on the signal line S1. Therefore, the first stage selection control circuit 2
At 31, the outputs of the AND gates A 1 and A 2 become high (H) and low (L), respectively, under the magnitude comparison result DD 1 ≦ Di, and the corresponding grade selector GS supplies the (H, L) A selection command signal according to the combination is supplied.
The corresponding grade selector GS receiving this selection command signal
Is appearing on the grade bus 51 by conducting between the one input terminal A connected to the grade bus 51 and the input terminal of the corresponding grade register GR in synchronization with the falling edge of a clock signal (not shown). Is transferred to and held in the corresponding grade register GR.

On the other hand, in the second and subsequent selection control circuits 232, 233, 234,..., The signal lines S1 connected to the previous selection control circuits 231, 232, 233,.
Since a high signal based on the magnitude comparison result DD1 ≦ Di in the preceding stage appears above, the outputs of the AND gates A1 and A2 are low and high, respectively. The corresponding grade selector GS receiving the selection command signal based on the combination of (L, H) conducts between the input terminal B and the input terminal of the corresponding grade register GR in synchronization with the falling edge of the clock signal. Therefore, in the data registers with selectors 212, 213, 214... In the second and subsequent stages, the data registers 211, 212, 21
The maximum value [FF] _{H of} the grade held as an initial value in the grade register GR in 3... Is shifted and held in the corresponding grade register GR.

As a result, the grade DD1 which first appears on the grade bus 51 is held in the grade register GR in the first stage data register with selector 211, and the data registers with selectors 212 and 2 in the subsequent stage.
13, 214... Hold the initial value [FF] _H shifted from the grade register GR of the data registers 211, 212, 213. Next, when the second non-zero grade DD2 appears on the grade bus 51, two different data transfer operations are performed in accordance with the magnitude relationship between this and the grade DD1 that first appeared. First, the operation when DD2 ≦ DD1 will be described.

The first stage selection control circuit 231 compares the newly appearing grade DD2 with the grade DD1 held in the grade register GR.
In this case, since DD2 ≦ DD1, the same selection operation as when the first grade DD1 appears appears, and the new grade DD is synchronized with the falling edge of the clock signal.
2 is held in the grade register GR in the data register 211 with selector at the first stage.

On the other hand, for the data registers with selectors 212, 213, 214... Of the second and subsequent stages, the combination of the signals of the AND gates A1 and A2 in the corresponding selection control circuits 232, 233, 234. As in the previous case, all become (L, H), so DD1 held in the grade register GR in the data registers 211, 212, 213,... Of the preceding stage and the upper limit value of the grade [FF]
_H is shifted and held. This grade register GR
The shift operation between the two is also performed in synchronization with the falling edge of the clock signal simultaneously with the operation of holding the grade from the grade bus 1.

As a result, the grade DD2 which appears second on the grade bus 51 is held in the grade register GR in the data register 211 with selector at the first stage,
The grade register GR in the data register with selector 212 in the second stage holds the grade DD1 shifted from the data register with selector 211 in the previous stage, and the data registers with selector 213 in the third and subsequent stages.
.. Holds the initial value [FF] _H shifted from the data registers with selectors 212, 213,.

Next, the operation in the case where the grade DD2 which appears second on the grade bus 51 is larger than the grade DD1 which appears first (DD2> DD1) will be described. In this case, the output of the comparison circuit CMP in the first stage selection control circuit 231 becomes low, and the AND gates A1, A2
Is (L, L). First stage data register with selector 211 receiving selection command of this combination
Of the input terminal A
Also does not conduct to the input terminal of the corresponding grade register GR. Therefore, the previously held grade DD1 continues to be held in the grade register GR in the data register with selector 211 of the first stage.

On the other hand, the second-stage selection control circuit 23
The output of the comparison circuit CMP in 2 becomes high because the corresponding grade register GR holds the initial value [FF] _H shifted from the previous-stage grade register GR last time. Further, the pre-stage selection control circuit 2 that appears on the signal line S2
Since the comparison result of 31 is low, AND gate A
The combination of the outputs of A1, A2 is (H, L). The grade selector GS in the corresponding selector-equipped data register 212 that receives the selection command for this combination turns on the input terminal A and the input terminal of the corresponding grade register GR.
As a result, the second-stage data register with selector 212
In the grade register GR, the grade DD2 (> DD1) appearing on the grade bus 1 is held.

Third and subsequent selection control circuits 233 and 234
.., The result of the magnitude comparison in the own stage and the result of the magnitude comparison in the selection control circuits 232, 233,... Of the preceding stage are high, and the combination of the outputs of the AND gates A1 and A2 is (L, H). As a result, the corresponding data registers with selectors 213, 214... Hold the initial value [FF] _H shifted from the data registers with selectors 212, 213.

Thus, the grade DD which first appeared
1 is first held in the grade register GR in the data register with selector 211 in the first stage, and if the second appearance grade DD2 is equal to or less than the grade DD1, this is held in the first stage grade register and held in this. The grade DD1 is shifted to and held by the second-stage grade register GR. Conversely, grade DD2
Is larger than the grade DD1, this is held in the second-stage grade register GR, and the first-stage grade register GR keeps holding the first grade DD1.

The above data transfer operation can be summarized as follows. A1. When the grade appearing on the grade bus 51 is smaller than or equal to any of the grades held in the grade register of the previous stage and the own stage, except for the selection control circuit of the first stage, The grade held in the preceding grade register is transferred to the own grade register. A2. If the grade appearing on the grade bus 51 is larger than the grade held in the preceding grade register but smaller than or equal to the grade held in the own grade register, the appearing grade is assigned to the own grade register. To the grade register. A3. If the grade appearing on the grade bus 51 is larger than the grade held in the grade register of the own stage, the transfer to the grade register of the own stage is not performed, and the current value is kept retained.

B. If the grade appearing on the B1. Grade bus 51 is smaller than or equal to the grade held in its own grade register, the first-stage selection control circuit transfers the appearing grade to its own grade register. B2. When the grade appearing on the grade bus 51 is larger than the grade held in the grade register of the own stage, the transfer to the grade register of the own stage is not performed.

Referring to FIG. 5, selector-equipped data registers 221 and 212 arranged corresponding to selector-equipped data registers 211, 212, 213,.
, 22... Correspond to the corresponding selection control circuits 231,
32, 233,... In accordance with the selection command from each of the data registers 211, 212, 213,.
Performs the same operation as. Accordingly, the label code bus 52 corresponding to the grade output on the grade bus 51
The label code appearing above is held in the label code register LR of each stage corresponding to the grade held in GR in the grade register of each stage.

By setting a shape such that only two adjacent membership functions have an intersection as a membership function for defining an input label of each input data channel of fuzzy inference, a maximum of two input functions per input channel can be obtained. Is calculated. Therefore, by setting the number of stages of the data register with selector to twice the number of input data channels, all non-zero grades appearing on the grade bus can be sorted in ascending order.

The grades of the input labels sorted in the order of the sizes are placed on the grade bus 51 from the corresponding grade register GR via the gate circuit GG by the read enable signal RE supplied to each stage in accordance with the arrangement order of each stage. Is output. In synchronization with the output of the grade of the input label, the corresponding label code is read from the label code register LR to the gate circuit LG by the read enable signal RE.
And is output on the label code bus 52 via.

As described above, in order to reduce the amount of hardware and the processing speed, exception processing is performed for zero grade. However, when there is a margin in the amount of hardware and the processing speed, a configuration that does not include such exception processing may be adopted.

Further, a configuration may be adopted in which a predetermined threshold value larger than zero is set, and a grade lower than this threshold value is subjected to exception processing.

The rearrangement order (entry address) from the rearrangement circuit 10 in the descending order of the grade of the input label.
To output the minimum grade detection circuits 510 and 520.
··· The configuration in which the register is held in the above is exemplified. However, instead of the rearrangement order, the grades of the input labels are directly output from the rearrangement circuit 10 in the descending order, and are held in the registers in the minimum grade detection circuits 510, 520... It is also possible to adopt a configuration in which the largest one of the held minimum grades is detected by the maximum grade detection circuits 51, 52,.

Further, the configuration in which the grades of the input labels are rearranged in the register group connected in cascade together with the corresponding label codes in the order of magnitude is illustrated. However, when the above rearrangement is realized by software,
A configuration in which the holding position of the label code corresponding to the above input grade is fixed in the memory, and the grade of the input label and the corresponding label code are rearranged in descending order of magnitude and output after rearrangement using a pointer. It can also be.

Further, a configuration in which the subsequent stage including the logic circuit group 40 of FIG. 1 is provided corresponding to each output channel has been exemplified. However, if the increase in the operation time can be tolerated, a single logic circuit 40 is provided for a plurality of output channels, and this is shared by shifting the time for each output channel, thereby reducing the amount of hardware in the subsequent stage. It is also possible to achieve reduction. If the increase in operation time can be further tolerated, further reduce the amount of hardware by using the minimum grade detection circuit in a single logic circuit with the time shifted between each output label. Is also possible.

Further, in order to realize a high-speed processing of the whole fuzzy inference, a rearrangement circuit and a preceding grade operation circuit are connected in cascade, and the grade operation and the rearrangement of the operated grade are performed in a pipeline system. The configuration to be executed is exemplified. However, when such high speed is not required, a buffer memory may be provided between the rearrangement circuit and the grade operation circuit, and the rearrangement may be started after all the grade operations are completed. it can.

[0094]

As described above in detail, the min-max operation circuit of fuzzy inference according to the present invention collectively sorts the input labels included in the antecedents of all rules in the descending order of the grade. Since the arrangement is rearranged, there is an advantage that the waste of repeating the magnitude comparison of the same grade for each rule is eliminated, and the processing time is greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a min-max operation circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a minimum grade detection circuit 410 of FIG. 1;

FIG. 3 is a block diagram showing another example of the configuration of the grade register of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a min-max operation circuit according to another embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a preferred configuration of the input label rearranging circuit 10 in FIGS. 1 and 4;

FIG. 6 is a conceptual diagram for explaining the concept of the present invention in which input labels included in the antecedent part of each rule are replaced in descending order of grade.

FIG. 7 is a conceptual diagram for explaining the concept of an encoding rule according to the present invention.

FIG. 8 is a conceptual diagram for explaining the concept of an encoding rule according to the present invention.

FIG. 9 is a conceptual diagram for explaining the concept of a rule corresponding bit group held in a rule memory in the present invention.

FIG. 10 is a conceptual diagram for explaining the concept of a rule-corresponding bit group rearranged in descending order of input label grade and an encoding rule modified by replacement of input labels.

[Explanation of symbols]

 10 Grade rearrangement circuit 20 Rule ROM (rule memory) 40 Logic circuit 410,510 Minimum grade detection circuit 411,31,51 Maximum grade detection circuit 51 Grade bus 52 Label bus

Claims (12)

(57) [Claims] A determining means for determining in advance the magnitude relationship of the grades of the input labels relating to fuzzy inference; and computing means for executing a min-max operation on the grades of the input labels in accordance with the order of magnitude determined by the determining means. Mi of fuzzy inference characterized by having
n-max operation circuit. 2. A method according to claim 2, wherein each rule includes, in accordance with a predetermined arrangement defined for each input label included in the antecedent part of each rule of fuzzy inference, whether each rule includes said input label in each antecedent part. An encoding rule to be indicated by an invalid bit is defined for each rule, and a valid / invalid bit group of each input label (hereinafter, referred to as a “rule-corresponding bit group”) included in each of the encoding rules thus defined is defined. By holding the coding rule at an address specified by the identification code (hereinafter, referred to as “label code”) of the input label, the encoding rules are spread over a plurality of addresses and are arranged in a predetermined direction in the arrangement direction of each bit of the rule corresponding bit group. A rule memory that holds the data while arranging them in the order of After rearranging the input labels along with the order of the labels, the grades of the rearranged input labels or the rearrangement order of the input labels are output in descending order or in ascending order, and the corresponding label codes are supplied as read addresses of the rule memory. An input label rearranging means for outputting a corresponding rule corresponding bit group, and a grade or an input label output from the rearrangement circuit, which is provided corresponding to each encoding rule sequentially output from the rule memory. Minimum grade detection means for obtaining detection information on the minimum grade based on the order of rearrangement and the first or last valid bit appearing in each encoding rule output from the rule memory; Installed corresponding to each rule that includes a corresponding output label as a consequent part min-max operation circuit fuzzy inference, characterized in that a maximum grade detection means for obtaining detection information about the largest of the minimum grade on the basis of the detection information is a minimum grade detection means to obtain. 3. The input label rearranging unit according to claim 2, wherein the input label rearranging unit includes a unit that outputs a grade of the rearranged input labels in ascending order. Means for obtaining, as output, the first valid bit in each encoding rule output from the rule memory at the time of output as detection information relating to the minimum grade, wherein each maximum grade detection means is a corresponding minimum grade detection means. A fuzzy inference method comprising means for obtaining the last one of the obtained detection information as the detection information for the largest one of the minimum grades.
min-max operation circuit. 4. The input label rearranging unit according to claim 3, wherein the input label rearranging unit receives the detection information on the largest one of the minimum grades output from each of the maximum grade detecting units and determines the grade of the input label being output. Min-max of fuzzy inference characterized by having a grade holding means for holding as a grade of an output label
Arithmetic circuit. 5. The grade according to claim 4, wherein the grade holding means is arranged in a predetermined number of columns that is smaller than the total number of the output labels, and the grades of the predetermined number of output labels are arranged in order from the largest one. Min- of fuzzy inference characterized by the fact that
max arithmetic circuit. 6. The fuzzy inference min-max operation circuit according to claim 5, wherein the predetermined number is two. 7. The input label rearranging unit according to claim 2, wherein the input label rearranging unit includes a unit that outputs a rearrangement order of the input labels in descending order of grade of the rearranged input labels. By retaining the rearrangement order of the input labels being output from the input label rearranging means based on each effective bit appearing in each encoding rule output from the rule memory, Means for obtaining the rearrangement order of the smallest input label that appeared last as detection information relating to the minimum grade, wherein each of the maximum grade detection means has the minimum rearrangement order held by the corresponding minimum grade detection means. Means for obtaining the largest one as detection information relating to the largest one of the minimum grades, and a corresponding input using the detection information as an address. Means for outputting a label grade from the rearrangement circuit.
n-max operation circuit. 8. The input label rearranging means according to claim 2, further comprising: means for outputting a grade of the rearranged input labels in descending order, wherein each of the minimum grade detecting means is outputted from the rule memory. By maintaining the grade of the input label being output from the input label rearranging means based on each valid bit appearing in each encoding rule, the grade of the smallest input label that appears last in each encoding rule is maintained. As a detection result regarding the minimum grade, wherein each of the maximum grade detection means detects the maximum one of the data held in the corresponding one of the minimum grade detection means with respect to the maximum one of the minimum ones. Min- of fuzzy inference characterized by having means to obtain the result
max arithmetic circuit. 9. The input label rearrangement unit according to claim 2, wherein the input label rearrangement unit sets the grade of each input label to be rearranged that is equal to or more than a predetermined threshold as the target of the rearrangement and output, and An input label grade of less than is excluded from the rearrangement and output according to an instruction signal indicating that, and a corresponding label code is supplied as a read address of the rule memory to output a corresponding rule corresponding bit group. Exception handling means, wherein the minimum grade detection means, during rearrangement of input labels by the input label rearrangement means, in the rearrangement corresponding to valid bits appearing in each coding rule output from the rule memory Only when the grade of the input label is equal to or more than the threshold value, the minimum value at the time of output of the input label The characterized by comprising exception handling means for enabling delayed detection of fuzzy inference min-
max arithmetic circuit. 10. The fuzzy inference min-max operation circuit according to claim 9, wherein the predetermined threshold is a minimum finite value that can be processed by the min-max operation operation circuit. 11. The input label rearranging unit according to claim 2, wherein the calculated input label grade is supplied to the input label rearranging unit in the order of operation by the preceding grade arithmetic unit. A fuzzy inference min-max arithmetic circuit, wherein the preceding grade arithmetic means operates in a pipeline manner. 12. The input label rearranging circuit according to claim 2, wherein the input label rearranging circuit includes a plurality of grade registers arranged in tandem and holding a predetermined initial value by initial setting, and an input label installed corresponding to the grade registers. A first operation for forming a data transfer path from the grade bus where the first grade appears to the corresponding grade register, a second operation for forming a data transfer path from the grade register of the adjacent stage to the corresponding grade register, and any of the above. Grade transfer path forming means controlled to execute any one of non-operations that do not form a data transfer path, label code registers arranged in tandem with the grade registers, and these label codes・ A label code that is installed corresponding to the register and a label code appears A first operation for forming a data transfer path leading to a data register, a second operation for forming a data transfer path from a label code register in an adjacent stage to a corresponding label code register, and any of the above data transfer paths. A label code transfer path forming unit that is controlled to execute any one of non-operations not to be formed; and a command for instructing each of the operations to the grade transfer path forming unit and the label code transfer path forming unit. A plurality of transfer control circuits provided correspondingly, wherein each of the transfer control circuits determines a magnitude relation between a grade held in a corresponding grade register and a grade appearing on the grade bus. Circuit, the size determination result of the own stage by the size determination circuit, and the size of the adjacent stage similarly performed by the size determination circuit in the transfer control circuit of the adjacent stage. And a logic circuit for issuing a selection command of the operation to the corresponding grade transfer path forming means and the label code transfer path forming means based on a combination of a constant result, the logic circuit, a. If the magnitude determination result of the own stage is the first result and the magnitude determination result of the adjacent stage is the second result opposite thereto, the first operation is instructed to the corresponding transfer path forming means. Output a signal to b. If the magnitude determination result of the own stage is the first result, and the magnitude determination result of the adjacent stage is the same first result, the second operation is performed by the corresponding transfer path forming means. Outputting a command signal; c. If the magnitude determination result of the own stage is a second result, the signal for instructing the non-operation to the corresponding transfer path forming means is output regardless of the magnitude determination result of the adjacent stage. A min-max operation circuit for fuzzy inference characterized by: