JPH06110575A - Automatic delay adjusting mechanism for lsi - Google Patents

Abstract

PURPOSE:To operate a digital circuit for exchanging signals between plural LSI synchronously with a clock while guaranteeing hold time without lowering the operating clock even when the operating speed is dispersed by the manufacture dispersion of the LSI or the fluctuation of operational environments. CONSTITUTION:Although a delay adjusting circuit 3 delays a clock synchronizing signal 101 outputted from a signal generation part 1 so as to satisfy the hold time of a signal reception part 2, the delay time of the signal generation part 1 is indirectly measured by a delay measurement circuit 4 and corresponding to the result, the delay time of the delay adjusting circuit 3 is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic delay adjusting mechanism for an LSI, and more particularly to a digital LS for transmitting / receiving a clock synchronization signal.
The present invention relates to a delay time automatic adjustment mechanism for an LSI that adjusts the delay time of an I clock synchronization signal.

[0002]

2. Description of the Related Art In the prior art, in a digital LSI, when a clock synchronization signal is transferred between a plurality of LSIs,
An LS that receives a signal even when the operation speed of the LSI that sends the signal is minimum so that the operation can be performed even if the operation speed varies due to variations in the manufacturing process and changes in the operating environment.
Even if the delay circuit that delays the signal by a certain time so as to satisfy the hold time of I is provided in the LSI that transmits the signal or the LSI that receives the signal, and the operation speed of the LSI that transmits the signal is the maximum, The frequency of the operation clock is determined so as to satisfy the setup time of the LSI for receiving.

[0003]

In the above-mentioned conventional technique, even if the actual operating speed is the maximum, the signal is delayed for a certain period of time assuming the minimum case. Therefore, the signal should be delayed more than necessary. Therefore, there is a drawback that it cannot operate at the frequency of the operation clock that is originally operable.

[0004]

An automatic delay adjusting mechanism for an LSI according to the first invention is a digital circuit for transmitting and receiving a signal synchronized with a clock between a plurality of LSIs, and the LSI of the LSI It is provided with means for measuring the operating speed and means for adjusting whether or not to delay the signal according to the result measured by the measuring means.

The automatic delay adjusting mechanism for an LSI of the second invention is the automatic delay adjusting mechanism for an LSI according to the first invention, wherein the measuring means compares the time passing through the measuring delay circuit with the cycle of the clock. The clock period comparison means is included.

According to a third aspect of the present invention, there is provided an automatic delay adjusting mechanism for an LSI according to the first aspect of the automatic delay adjusting mechanism for an LSI, wherein the measuring means is a delay line provided outside the LSI and having a small delay variation. It includes delay line comparing means for comparing the passing time and the passing time of the delay circuit for measurement.

The automatic delay adjustment mechanism for an LSI according to the fourth aspect of the present invention provides a means for measuring the operating speed of the LSI in a signal sending LSI in a digital circuit for passing a signal synchronized with a clock between a plurality of LSIs. The LSI for receiving a signal is provided with means for adjusting whether or not to delay the signal according to the measurement result from the measuring means.

According to a fifth aspect of the present invention, there is provided a delay automatic adjustment mechanism for an LSI, wherein a digital circuit for transmitting and receiving a signal synchronized with a clock between a plurality of LSIs includes a delay circuit for measurement in the LSI for transmitting a signal, The receiving LSI is provided with means for measuring the operation speed of the sending LSI for the signal connected to the delay circuit, and means for adjusting whether or not the signal can be sent.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Clock synchronization signal 10 output from the signal generator 1
1 is a clock synchronization signal 10 via the delay adjustment circuit 3.
2, which is input to the signal receiving unit 2. Further, the clock signals 104 and 105 from the clock generator 5 are input to the signal generator 1 and the signal receiver 2 at the clock terminals, respectively. Delay time information 1 output from the delay measurement circuit 4
03 is input to the delay adjustment circuit 3. The signal generation unit 1 and the signal reception unit 2 exist in different LSIs.

FIG. 2 is a block diagram showing an example of the delay measuring circuit 4 when comparing the time passing through the measuring delay circuit with respect to the clock cycle. External clock signal 20
1 is a stable clock with a highly accurate cycle. In the comparison circuit 12, the clock that has passed the measurement delay circuit 11 by a logical OR and a logical delay between the clock that is half or one cycle after the external clock signal 201 and the clock that has been delayed by the measurement delay circuit 11 If the difference is late, the pulse of the difference is sent to the stabilizing circuit 13 to make a comparison in time. The stabilizing circuit 13 integrates the input pulse for a long period with respect to the clock cycle, and outputs delay time information 103.

FIG. 3 shows the time taken for a delay line, which is a delay circuit provided outside the LSI and having a small delay variation,
FIG. 6 is a block diagram showing an example of a delay measuring circuit 4 in the case of comparing with a time passing through a measuring delay circuit. The pulse generator 15 may have low precision in both the pulse width and the repetition period. However, this pulse width needs to be longer than the difference when the difference between the delay time of the measurement delay circuit 11 and the delay time of the delay line 14 is the largest. The pulse output from the pulse generator 15 is input to the measurement delay circuit and the delay line 14 having a high delay time accuracy. The comparator circuit 12 logically ORs the pulse delayed through the measurement delay circuit 1 and the pulse delayed through the delay line.
And when the pulse passing through the measurement delay circuit 11 is slower by logical AND, the pulse of the difference between the pulses is sent to the stabilizing circuit 13 to perform the temporal comparison. The stabilizing circuit 13 integrates the input pulse for a period longer than the clock cycle, and outputs delay time information 103.

The measurement delay circuit 11 and the signal generator 1 are provided in the same LSI. This is because the variation in the delay time is extremely small among a plurality of logic elements in a single LSI, so that the signal generation is indirectly performed by measuring the delay time of the measuring delay circuit 11 in the delay measuring circuit 4. This is because it is possible to determine whether the delay time of the unit 1 is close to the maximum value or the minimum value.

FIG. 4 is a block diagram showing the configuration of the delay adjustment circuit 3. The selection circuit 22 uses the clock synchronization signal 10
1 and the signal obtained by delaying the clock synchronization signal 101 by the delay circuit 21 are selected by the delay time information 103.

Although the clock signal 104 and the clock signal 105 output from the clock generator 5 are logically the same, there is a time error and they are represented by clock _skew : t _SKEW . Further, the signal generation unit 1 takes a delay time: t _DELAY from receiving the clock signal 104 to outputting the clock synchronization signal 101. The delay adjustment circuit 3 delays the clock synchronization signal 101 by a delay time: t _ADJ based on the delay time information 103 from the delay measurement circuit 4 and outputs it as a clock synchronization signal 102. The signal receiving unit 2 samples the clock synchronization signal 102 with the cross signal 105, but requires a setup time: t _SETUP and a hold time: t _HOLD for the clock. Further, when the clock cycle is represented by T, since it is a transfer in a clock cycle formula, T ≥ t _DELAY + t _ADJ + t _SETUP + t _SKEW ... condition 1 and t _DELAY + t _ADJ ≥ t _HOLD + t _SKEW ... ... condition It is necessary to satisfy the two conditions 2 even under the influence of variations in the manufacturing tolerance of the LSI and changes in the operating environment such as temperature and voltage. Generally the variation of t _DELAY is large, t the maximum value of t _{DELAY DELAY (MAX),} the minimum value t
_When expressed as _{DELAY (MIN)} , from conditions 1 and 2, t _{ADJ ≤T} -t _{DELAY (MAX)} -t _SETUP -t _SKEW ... condition 3 and t _{ADJ ≥t HOLD} + t _SKEW -t _{DELAY (MIN)} ... ...... Condition 4 is set. Here, when t _HOLD + t _SKEW ≤t _{DELAY (MIN)} , t _ADJ = 0, that is, the delay adjustment circuit 3 is not necessary, but when t _HOLD + t _SKEW > t _{DELAY (MIN)} , the selection circuit The delay time t _{ADJ +} of the delay adjusting circuit 3 when 22 selects the output of the delay circuit 21 is set as t _{ADJ +} = t _HOLD + t _SKEW −t _{DELAY (MIN)} . The delay time t _ADJ- of the delay adjustment circuit 3 when the selection circuit 22 does not select the delay circuit 21 is set to 0 as _much as possible.

[0016] In this way, the large t _ADJ If t _DELAY is small, if t _DELAY is large t _ADJ
Can be small. In other words, even if the t _DELAY is minimized, satisfies the condition 4, the minimum period of case without delay adjustment: minimum period when relative T _OFF, adjust the delay: T _ON, from the condition 3, T _ON = T _OFF − (t _{ADL +} −t _ADJ− ) and high speed operation becomes possible.

One embodiment of the present invention described above is a case where the measurement of the operating speed and the delay adjustment are performed in two stages. Although the explanation is omitted in the present embodiment, the same applies to the case of three stages or more. It can be realized by the method.

[0018]

According to the present invention, by adjusting the delay on the basis of the result of the delay measurement, it is possible to speed up the operation clock by passing the clock synchronization signal between the LSIs and improve the system performance. Have.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of the delay measuring circuit shown in FIG.

3 is a block diagram of an example of the delay measuring circuit shown in FIG.

4 is a detailed block diagram of the delay adjustment circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 signal generation part 2 signal reception part 3 delay adjustment circuit 4 delay measurement circuit 5 clock generator 11 measurement delay circuit 12 comparison circuit 13 stabilization circuit 14 delay line 15 pulse generator 21 delay circuit 22 selection circuit 101 clock synchronization signal 102 Clock synchronization signal 103 Delay time information 104 Clock signal 105 Clock signal 201 External clock signal

Claims (5)

[Claims] 1. A digital circuit for transmitting and receiving a signal in synchronization with a clock between a plurality of LSIs, and means for measuring the operation speed of the LSI in the LSI for transmitting the signal,
The LS is provided with means for adjusting whether or not to delay the signal according to a result measured by the measuring means.
I delay automatic adjustment mechanism. 2. The automatic delay adjustment mechanism for an LSI according to claim 1, wherein said measuring means includes a clock cycle comparing means for comparing the time passing through the delay circuit for measurement with respect to the cycle of the clock. 3. A delay line comparing means for comparing a time passing through a delay line, which is a delay circuit provided outside the measuring means LSI and having a small delay variation, with a time passing through a delay circuit for measurement. Automatic delay adjustment mechanism for the described LSI. 4. A digital circuit for transmitting and receiving a signal in synchronization with a clock between a plurality of LSIs, wherein a means for measuring the operating speed of the LSI is provided in the LSI for transmitting the signal, and the LSI is provided in the LSI for receiving the signal. An automatic delay adjusting mechanism for an LSI, comprising means for adjusting whether or not to delay the signal according to a measurement result from the measuring means. 5. A digital circuit for transmitting and receiving a signal in synchronization with a cross between a plurality of LSIs, wherein a delay circuit for measurement is provided in the LSI for transmitting the signal, and the delay circuit is connected in the LSI for receiving the signal. Signal transmission LS
An automatic delay adjustment mechanism for an LSI, comprising: a means for measuring the operation speed of I and a means for adjusting whether or not the signal can be sent.