JPH06110426A - Image processor - Google Patents

Abstract

PURPOSE:To constitute the image processor by using a simple circuit by performing control so that data of a window-ON signal by one horizontal scanning line which are written in a storage means are read out in a period wherein an image is displayed. CONSTITUTION:In a horizontal blanking period wherein a horizontal blanking period signal, the inverse of HBL is at level L, a selector SE1 selects a CPU write clock, the inverse of CPUWR inputted to an input terminal (0) and outputs it to respective input terminals of shift registers SR1-SR32 and a decoder DE1, on the other hand, enters an enabled state to decode data of an inputted address and outputs the decoded signal from respective inversion output terminals to respective load signal terminals LD of the shift registers SR1-SR32. The data of the window-ON signal are inputted from a CPU, and the decoder DE1 outputs an L level load signal to the shift register SR1 and an H-level load signal to other shift registers SR2-SR32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device such as a CRT display controller.

[0002]

2. Description of the Related Art FIG. 6 shows an image on a CRT display showing a conventional window processing in which specific image processing is performed only on a predetermined area.

In the image processing apparatus of the conventional example, a certain area such as a predetermined area on the screen is processed such that a specific screen is not displayed or image processing is performed by adding or subtracting an image only in the specific area. In order to perform the image processing (hereinafter, referred to as window processing), a window for which specific processing is to be performed by using a start address value and an end address value that respectively indicate positions in the horizontal direction on one horizontal scanning line. Was being set.

[0004]

For example, as shown in FIG. 6, when the inside of the character "ABC" is the window for which specific processing is to be performed, six windows W1 are displayed on the horizontal scanning line of the nth line. To W6 need to be set, and the start address value and end address value need to be given in each window W1 to W6. A single horizontal scanning line requires a memory for storing such an address value, and a large amount of memory is required to set all of the characters in "ABC" in the window. There is a problem that a hardware circuit for performing window processing using a memory is large and complicated.

The object of the present invention is to solve the above problems, to construct a simple circuit as compared with the conventional example, and to perform window processing for performing specific image processing only in a predetermined area. An object is to provide an image processing device.

[0006]

According to a first aspect of the present invention, an image processing apparatus scans a horizontal scanning line a plurality of times in a vertical direction and performs a predetermined process on an image signal forming an image on a screen. An image processing apparatus for performing the above, which comprises storage means for storing data of a window-on signal for one horizontal scanning line indicating that specific image processing is to be performed on a predetermined area on the screen, and a horizontal blanking period. The data of the window-on signal for one horizontal scanning line is written in the storage means, the predetermined processing is performed on the image signal, and the processed image of the image signal is written in the storage means during the period of displaying on the display means. Storage control means for controlling to read the data of the window-on signal for one horizontal scanning line.

An image processing apparatus according to a second aspect of the present invention is an image processing apparatus which scans a horizontal scanning line a plurality of times in the vertical direction and performs a predetermined process on an image signal forming an image on a screen. , First storage means for storing data of a window-on signal for one horizontal scanning line of an odd line indicating that specific image processing is performed on a predetermined area on the screen, and performing the specific image processing That stores the data of the window-on signal for one horizontal scanning line of the even line indicating that
Of the horizontal scanning lines and the line switching signal indicating the switching of the horizontal scanning lines, the data of the window-on signal for one horizontal scanning line of the even lines is displayed when the image of the image signal of the even lines is displayed. 1 of the odd line following the displayed even line while reading from the means
The data of the window-on signal for the horizontal scanning line is converted to the first
Of the image signal of the odd-numbered line, the data of the window-on signal for one horizontal scanning line of the odd-numbered line is read from the first storage means and displayed. Storage control means for controlling to write the data of the window-on signal for one horizontal scanning line of the even lines following the odd lines into the second storage means.

Further, the image processing apparatus according to claim 3 is
The image processing apparatus according to claim 2, wherein the line switching signal is data output from a control device of the image processing apparatus.

[0009]

In the image processing apparatus according to the present invention, the storage control means writes the data of the window-on signal for one horizontal scanning line into the storage means during the horizontal blanking period, and the predetermined data for the image signal. Control is performed so that the data of the window-on signal for one horizontal scanning line written in the storage unit is read during the period in which the image of the processed image signal is displayed on the display unit after the processing.

Further, in the image processing apparatus according to the second aspect of the present invention, the storage control means, based on a line switching signal indicating switching of the horizontal scanning line, displays the image of the even-numbered line in the even-numbered line. The data of the window-on signal for one horizontal scanning line is read from the second storage means, and the data of the window-on signal for one horizontal scanning line of the odd-numbered line following the displayed even line is stored in the first storage. When the image of the odd-numbered line image signal is displayed, the odd-numbered 1
The data of the window-on signal for the horizontal scanning line is converted to the first
And the data of the window-on signal for one horizontal scanning line of the even-numbered line following the displayed odd-numbered line is written into the second storage unit.

Further, in the image processing device according to claim 3, in the image processing device according to claim 2, preferably, the line switching signal is data output from a control device of the image processing device.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a game device for performing window processing according to a first embodiment of the present invention.

The game device of this embodiment displays background image data (hereinafter referred to as background data), which is the background of the image output from the background processing section 20, and the background in the background. Image data of an object (hereinafter, referred to as object data) that is input from the object processing unit 30 and that is a character, a person such as a main character of a game, an object such as an animal (hereinafter, referred to as an object) that appears in the game (hereinafter, referred to as an object). Of the above, a priority control display unit 10 for controlling which is displayed preferentially is provided. In the priority control display unit 10, the CPU 11 of the game device specifies only a predetermined specific area on the screen. To perform image processing, a window-on signal indicating the specific area is supplied to the horizontal block for one horizontal scanning line segment. 32 to write to the trunking period
A window control processing unit 13 including a number of shift registers SR1 to SR32 is provided.

As shown in FIG. 1, the background processing unit 20 is connected to a text image memory 21 for storing text data and a character memory 22 for storing character data (font data), and the background processing unit 20 is connected. Generates background data relating to the background of the image using the data stored in the memories 21 and 22 and outputs the background data to the data interface 14 of the priority control processing unit 10. On the other hand, in the object processing unit 30, an attribute memory 31 for storing attribute data indicating attributes of an object (priority information at the time of screen display, color palette data, character name) and a character memory 32 for storing character data (font data). The object processing unit 30 generates object data using the data stored in the memories 31 and 32, and outputs the object data to the data interface 14 of the priority control processing unit 10 via the line memory 33. Here, the background data and the object data each include character data, color data, a priority signal, and a transparency signal indicating whether or not each surface is made transparent.

The priority control processing unit 10 inputs background data and object data, window-on signal data for window control input from the CPU 11 which controls the entire game apparatus, various signals, and priority determination. Based on the data of the priority signal for determining the priority, which of the multiple surfaces of the background data and the surface of the object data is to be preferentially displayed on the front surface is determined, and the surface selection signal is set to the color code memory address. Processing unit 16 and display control processing unit 50
And outputs the image data from the memory 40 by controlling the color code memory 40 that stores the R, G, B image data of the color graphic corresponding to the color code based on the background data and the object data. It is read and output to the display control processing unit 50. Further, the display control processing unit 50 selects the surface of the image data based on the image data output from the color code memory 40 and the surface selection signal output from the priority control processing unit 10, and displays the selected surface. R, G, B color image signals are generated from the image data and output to the display 60 for display.

FIG. 2 shows the priority control processing unit 1 of FIG.
It is a block diagram of 0. As shown in FIG. 2, the priority control processing unit 10 includes a CPU interface 12 that performs interface conversion of signals and data transmitted and received between the processing unit 10 and the CPU 11, a window control processing unit 13, and the processing unit. A data interface 14 for performing interface conversion of data transmitted / received between 10, the background processing unit 20, and the line memory 33, a priority determination unit 15, and a color code memory address processing unit 16.

Character data and color data of the background data output from the background processing unit 20 are input to the color code memory processing unit 16 via the data interface 14, and the other transparent signals and priority signals are input. Is input to the priority determination unit 15.
On the other hand, the object processing unit 30 to the line memory 33
Character data and color data out of the object data input via the data interface 1
Is input to the color code memory processing unit 16 via 4,
Other transparent signals and priority signals are input to the priority determination unit 15. Furthermore, the priority signal output from the CPU 11 is input to the priority determination unit 15 via the CPU interface 12, and the data of the window-on signal output from the CPU 11 and various signals for window control are input to the CPU interface 12. It is input to the window control processing unit 13 via the.

As will be described later in detail, the window control processing unit 13 controls the CP during the horizontal blanking period.
CPU write clock of low active from U11 CPU
A window-on signal for one horizontal scanning line, which is input in synchronization with WR- (hereinafter, indicated by a bar of CPUWR in the drawing), is temporarily stored, and each dot of the display is displayed at the time of display on the CRT display 60. In synchronization with a low-active dot clock signal DOTCK- (indicated by a DOTCK bar in the drawing) which is a synchronization signal, the data is read bit by bit and output to the priority determination unit 15. Next, the priority determination unit 15 preferentially displays which surface among the plurality of surfaces including the plurality of background surfaces and the object surface based on the input priority signal, transparency signal, and window-on signal. It is determined according to a predetermined priority procedure, and a surface selection signal indicating a surface to be displayed with priority is output to the color code memory address processing unit 16 and the display control processing unit 50. Here, when the window on signal is at the H level, it indicates that the predetermined window processing is performed on the pixel of the dot, and when the window on signal is at the L level, the window processing is not performed on the pixel of the dot. Indicates.

Color code memory address processing unit 16
Generates an address and a read signal of the color code memory 40 for displaying an image on the CRT display 60 on the basis of the input character data, color data and a surface selection signal, and outputs the read signal to the color code memory 40. Then, the image data is read from the memory 40 and output to the display control processing unit 50.

FIG. 3 is a block diagram of the window control processing unit 13 of FIG. In this embodiment and the second and third embodiments described below, the number of display dots in the horizontal direction on the CRT display 60 is 256,
Pixel data of 256 bits per horizontal scanning line is CRT
It is input and displayed on the display 60.

As shown in FIG. 3, the window control processing unit 13 includes 32 8-bit shift registers SR1 to SR that are connected in cascade and store data of window-on signals for one horizontal scanning line of 256 bits in total.
32, a decoder DE1, and a selector SE1.

The serial out terminal SO of the shift register SR32 is connected to the serial in terminal SI of the shift register SR31, the serial out terminal SO of the shift register SR31 is connected to the serial in terminal SI of the shift register SR30, and so on. The serial out terminal SO of the shift register SR2 is the shift register SR.
1 is connected to the serial-in terminal SI, which
The shift registers SR1 to SR32 are connected to each other in cascade, and the serial out terminal S of the shift register SR1 is connected.
O becomes an output terminal of the window-on signal, and the terminal is connected to the priority determination unit 15. Further, the 8-bit data bus of the CPU 11 is connected to each of the shift registers SR1 to SR3.
2 is connected to each load input terminal of the shift register SR
Each load signal terminal LD- of 1 to SR32 (indicated by LD bar in the drawing) is connected to each 32-bit inverting output terminal of the decoder DE1.

A CPU showing one shift register for writing in order to write the data of the window-on signal into each shift register SR1 to SR32 by 8 bits at a time.
Address data is input from the CPU 11 to the decoder DE1 and a CPU write clock CPUWR for writing 8-bit data to one shift register
-Is input to the 0th input terminal (0) of the selector SE1. In addition, a dot clock DOTC for reading the window-on signal bit by bit when displaying an image
K- is input from the CPU 11 to the first input terminal (1) of the selector SE1. Further, a low-active horizontal blanking period signal HBL indicating the horizontal blanking period.
-(Indicated by HBL bar in the drawing) is input to the inversion enable input terminal GB of the decoder DE1 and the selection signal input terminal S of the selector SE1. In addition,
The output terminal Q of the selector SE1 is connected to each clock input terminal of the shift registers SR1 to SR32.

In the window control processing unit 13 configured as described above, the selector SE1 is input to the 0th input terminal (0) during the horizontal blanking period when the horizontal blanking period signal HBL- is at L level. The CPU write clock CPUWR- is selected and output to each clock input terminal of the shift registers SR1 to SR32, while the decoder DE1 is enabled and the data of the input address is decoded to output the decoded signal to each inverted output terminal. To each shift register SR1 to SR32
Output to each load signal terminal LD-. From the CPU 11, the shift registers SR1, SR2, SR3, ...
When the data of the window-on signal is input via the data bus in parallel to R32 in the order of 8 bits and, for example, the data to be written to the shift register SR1 is output, the CPU address indicating the shift register SR1 is input. At this time, the decoder DE1 outputs an L level load signal to the shift register SR1 and outputs an H level load signal to the other shift register SR2.
Through SR32. As a result, the data of the window-on signal input from the CPU 11 via the data bus is loaded and stored in the shift register SR1. Thereafter, similarly, the data of the window-on signal is loaded and stored in each of the shift registers SR2 to SR32, and as a result, during the horizontal blanking period, the window-on signal of 256 bits of one horizontal scanning line is output. The data is stored in the shift registers SR1 to SR32.

Next, in the image display period following the horizontal blanking period, the horizontal blanking period signal HBL- becomes H level, and the selector SE1 inputs the dot clock DOTCK input to the first input terminal (1).
The signal − is selected and output to each clock input terminal of the shift registers SR1 to SR32, while the decoder DE1 is disabled. At this time, the shift register SR
The data of the 256-bit window-on signal stored in 1 to SR32 is connected in cascade to the shift registers SR1 to S synchronized with the dot clock DOTCK-.
In R32, the data is shifted bit by bit from the shift register SR32 toward SR1 and serially output bit by bit from the serial out SO of the shift register SR1 to the priority determination unit 15. Next, the priority determination unit 15
Which one of the plurality of background surfaces and the object surface has priority over each dot, that is, one pixel, based on the input priority signal, the transparent signal, and the window-on signal. Whether or not to display the data is determined by a predetermined priority procedure, and a surface select signal indicating a surface to be displayed with priority is output to the color code memory address processing unit 16 and the display control processing unit 50, and as described above. An image of image data of background data or object data is displayed on the CRT display 60.

As described above, the window control processing unit 13 for temporarily storing the data of the window-on signal for one horizontal scanning line period is provided with 32 8-bit shift registers SR1 to SR32 and 1 decoder DE.
Since it is configured to include one and one selector SE1, a circuit capable of performing window processing can be configured with a simple circuit configuration as compared with the conventional example. Also, window processing can be performed on a region having a complicated shape.

Although the window control processing unit 13 is used in the first embodiment described above, the present invention is not limited to this, and circuits 13a and 13b as shown below may be used. The other circuit configurations are the same.

<Second Embodiment> FIG. 4 is a block diagram of a window control processing unit 13a according to the second embodiment.

As shown in FIG. 4, the window control processing unit 13a of the second embodiment displays the 256-bit window-on signal of the odd-numbered horizontal scanning lines when displaying the pixel data of the even-numbered horizontal scanning lines. The data is stored in 32 shift registers SR1 to SR32 by 8 bits at a time, and 1 bit is read from the 32 shift registers SR101 to SR132 connected in series to each other and output to the priority determination unit 15, while the odd line In displaying the pixel data of the horizontal scanning lines of, the data of the window-on signal of 256 bits of the horizontal scanning lines of the even lines are stored in 32 shift registers SR101 to SR132 by 8 bits and are connected in cascade. Reads one bit at a time from each of the shift registers SR1 to SR32. And outputs to the priority determining unit 15. The processing unit 13a includes 32 8-bit shift registers SR1 to SR32 that are connected in cascade and store data of a total of 256 bits of a window-on signal of odd-numbered horizontal scanning lines, and are connected in cascade to each other in even-numbered lines. 32 8-bit shift registers SR101 to SR132 for storing a total of 256 bits of window-on signal data of horizontal scanning lines, 2 decoders DE1 and DE2, and 3 selectors SE1, SE2 and S
E3 and a delay flip-flop FF1 are provided.

The shift registers SR1 to SR32 are the first
In the same manner as in the first embodiment, the shift registers SR101 to SR132 are connected to each other in cascade and to the decoder DE1, and the shift registers SR101 to SR132 are connected to each other in cascade and also to the decoder DE2. The serial-out terminal SO of the shift register SR1 serves as an output terminal of the window-on signal on the odd-numbered line, and the signal is sent from the terminal to the priority determination unit 15 via the first input terminal (1) and the output terminal Q of the selector SE3. Is output. In addition, the shift register S
The serial-out terminal SO of R101 serves as an output terminal of the window-on signal in the even-numbered line, and the signal is output from the terminal to the priority determination unit 15 via the 0th input terminal (0) and the output terminal Q of the selector SE3. It

Similar to the first embodiment, the shift register S
Data of a CPU address indicating one shift register of R1 to SR32 or one shift register of shift registers SR101 to SR132 is input to the decoders DE1 and DE2. Decoder DE1 3
Each 2-bit inversion output terminal is connected to each load signal terminal LD- of the shift registers SR1 to SR32, and each 32-bit inversion output terminal of the decoder DE2 is each load signal terminal L of the shift registers SR101 to SR132.
It is connected to D-.

The CPU write clock CPUWR- for writing the data of the 8-bit window-on signal to one shift register is connected to the shift register SR1 via the 0th input terminal (0) of the selector SE1 and its output terminal Q.
Through SR32, and the shift registers SR101 through SR13 through the first input terminal (1) of the selector SE2 and the output terminal Q thereof.
2 is input to each clock input terminal. Further, the dot clock DOTCK- for reading out the window-on signal of the horizontal scanning line immediately before the horizontal scanning line of the data of the window-on signal to be written bit by bit from the CPU 11 is the first input terminal (1) of the selector SE1. And its output terminal Q to the clock input terminals of the shift registers SR1 to SR32 and the selector SE2.
Is input to each clock input terminal of the shift registers SR101 to SR132 via the 0th input terminal (0) and the output terminal Q thereof.

Further, as shown in FIG. 6, the L level is set to the L level immediately before the end of the horizontal blanking period set at the end of one horizontal scanning line, and the horizontal scanning from one horizontal scanning line to the subsequent horizontal scanning is performed. A line switching signal LI− (indicated by a bar of LI in the drawing) indicating switching to the line and switching of processing of the processing unit 13a is input to the clock input terminal of the flip-flop FF1. The inverting output terminal QB of the flip-flop FF1 is connected to the signal input terminal D, and the signal output terminal Q is connected to each selection signal input terminal S of the selectors SE1, SE2, SE3 and the inverting enable input terminal GB of the decoder DE1. , The decoder DE2 via the inverter INV
Of the inversion enable input terminal GB.

Since the flip-flop FF1 is configured as described above, the L level line switching signal LI is used.
Every time a-is input to the flip-flop FF1, the signal from the signal output terminal Q of the flip-flop FF1 is inverted from the L level to the H level or from the H level to the L level, and the window of the horizontal scanning line of the odd line is turned on. It becomes L level at the time of writing the signal data and at the time of displaying the image data of the even-numbered horizontal scanning lines, and at the time of writing the window-on signal data of the even-numbered horizontal scanning lines and the odd-numbered horizontal scanning lines H when displaying image data
It becomes a level. Before the display of the image data of the first horizontal scanning line, the line switching signal LI− is input, whereby the signal from the signal output terminal Q of the flip-flop FF1 becomes L level, and the first The data of the window-on signal of the th horizontal scanning line is written.

In the window control processing section 13a configured as described above, the signal from the signal output terminal Q of the flip-flop FF1 becomes L level when displaying the image data of the horizontal scanning lines of even lines. At this time,
The decoder DE1 is enabled and the selector SE
3 is switched to the 0th input terminal (0) side, and the CPU write clock CPUWR- changes the selector SE1.
Of the shift register SR1 to SR32 via the 0th input terminal (0) and the output terminal Q thereof, and the dot clock DOTCK- is connected to the 0th input terminal (0) of the selector SE2. Its output terminal Q
Is input to each clock input terminal of the shift registers SR101 to SR132. Therefore, the data of the window-on signal of the odd-numbered horizontal scanning lines input from the CPU 11 via the data bus is 8 bits at a time, in the same manner as in the first embodiment, in synchronization with the CPU write clock CPUWR- in each shift register. The shift registers SR101 to S32 are sequentially written into SR1 to SR32 and
The window-on signal of the even-numbered horizontal scanning lines stored in R132 is serially output bit by bit from the serial out terminal SO of the shift register SR101,
It is output to the priority determination unit 15 via the 0th input terminal (0) of the selector SE3 and its output terminal Q. Next, the priority determination unit 15 determines, based on the input priority signal, the transparent signal, and the window-on signal, one dot for each pixel, that is, one pixel for each of a plurality of background surfaces and object surfaces. Which of the surfaces is to be preferentially displayed is determined by a predetermined priority procedure, and a surface select signal indicating the surface to be preferentially displayed is output to the color code memory address processing unit 16 and the display control processing unit 50. As described above, the image of the image data of the background data or the object data is displayed on the CRT display 60.

On the other hand, at the time of displaying the image data of the odd-numbered horizontal scanning lines, the signal from the signal output terminal Q of the flip-flop FF1 becomes H level. At this time, the decoder D
E2 is enabled, the selector SE3 is switched to the first input terminal (1) side, and the CPU write clock CPUWR- is shifted via the first input terminal (1) of the selector SE2 and its output terminal Q. Register S
The dot clock DOTCK- is input to each clock input terminal of the shift registers SR1 to SR32 through the first input terminal (1) of the selector SE1 and its output terminal Q while being input to each clock input terminal of R101 to SR132. To be done. Therefore, the 8-bit data of the window-on signal of the even-numbered horizontal scanning lines input from the CPU 11 via the data bus is synchronized with the CPU write clock CPUWR- in each shift register SR101.
Through SR132, the window-on signals of the odd-numbered horizontal scanning lines stored in the shift registers SR1 through SR32 are sequentially transferred to the shift register S1.
It is serially output bit by bit from the serial output terminal SO of R1 and is the first input terminal (1) of the selector SE3.
And its output terminal Q to the priority determination unit 15. Then, the priority determination unit 15 performs the priority determination process in the same manner as described above and outputs a surface selection signal indicating a surface to be displayed preferentially to the color code memory address processing unit 16 and the display control processing unit 50, and As described above, the image of the background data or the image data of the object data is displayed on the CRT display 60.

<Third Embodiment> FIG. 5 is a block diagram of the window control processing unit 13b of the third embodiment.

The window control processing unit 13b of the third embodiment is characterized in that it has a flip-flop FF2 instead of the flip-flop FF1 as compared with the second embodiment. Differences from the embodiment will be described.

In the third embodiment, the L level is set at the time of writing the window-on signal data of the horizontal scanning lines of the odd lines and at the time of displaying the image data of the horizontal scanning lines of the even lines, and the horizontal scanning of the even lines is performed. The line switching data, which becomes H level at the time of writing the data of the window-on signal of the lines and at the time of displaying the image data of the horizontal scanning lines of the odd lines, is transmitted through the write register (not shown) in the CPU 11 to the flip-flop. CPU write clock CPUWR input to the clock input terminal of the flip-flop FF2
Signal input terminal D of the flip-flop FF2 in synchronization with −
Then, it is input to each selection signal input terminal S of the selectors SE1, SE2 and SE3 and the inversion enable terminal GB of the decoder DE1, and also to the inversion enable terminal GB of the decoder DE2 via the inverter INV.

The window control processing unit 13b of the third embodiment configured as described above operates similarly to the second embodiment except the operation of the flip-flop FF2.

<Other Embodiments> In the above embodiments,
Although the character system in which the character data is input to the priority control processing unit 10 and processed is described, the present invention is not limited to this, and the priority control processing unit 1 is not limited thereto.
It is also possible to use a bitmap method in which the dot image data is input to 0 for processing.

Although the color code memory 40 is used in the above embodiments, the present invention is not limited to this, and R, G, B color data, for example, may be used as the display data. In this case, the color data is sent from the priority control processing unit 10 to the display control processing unit 50.

In the above embodiment, the line memory 33
However, the present invention is not limited to this, and a frame memory that stores object data for one frame may be used.

In the above embodiment, the CPU 11 and the priority control processing unit 10 are directly connected,
The present invention is not limited to this, and a DMA circuit may be provided between the CPU 11 and the priority control processing unit 10, and the data of the window-on signal may be DMA-transferred via the DMA circuit.

Although one background processing section 20 is provided in the above embodiments, a plurality of background processing sections 20 may be provided.

[0047]

As described above in detail, according to the image processing apparatus of the first aspect of the present invention, the data of the window-on signal for one horizontal scanning line is written in the storage means during the horizontal blanking period, and the image is displayed. Predetermined processing is performed on the signal, and control is performed so that the data of the window-on signal for one horizontal scanning line written in the storage means is read during a period in which the image of the processed image signal is displayed on the display means. Therefore, the circuit can be configured with a simpler circuit as compared with the conventional example, and the window processing can be performed on a region having a complicated shape.

Further, in the image processing apparatus according to the second aspect, based on the line switching signal indicating the switching of the horizontal scanning lines, one horizontal scanning line portion of the even lines is displayed when the image of the image signal of the even lines is displayed. The window-on signal data is read from the second storage means, and the window-on signal data for one horizontal scanning line of the odd-numbered line following the displayed even-numbered line is controlled to be written in the first storage means. At the time of displaying the image of the image signal of the odd line, the data of the window-on signal for one horizontal scanning line of the odd line is read from the first storage means, and the horizontal scanning of the even line following the displayed odd line is performed. Since the data of the window-on signal of the line segment is controlled to be written in the second storage means, it is simpler than the conventional example. It is possible to configure the circuit, it is possible to perform the windowing to a region of complicated shape.

[Brief description of drawings]

FIG. 1 is a block diagram of a game device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a priority control processing unit in FIG.

FIG. 3 is a block diagram of a window control processing unit in FIG.

FIG. 4 is a block diagram of a window control processing unit according to a second embodiment.

FIG. 5 is a block diagram of a window control processing unit according to a third embodiment.

FIG. 6 is a diagram showing an image on a CRT display showing window processing of a conventional example in which specific image processing is performed only on a predetermined area.

[Explanation of symbols]

10 ... Priority control processing section, 11 ... CPU, 12 ... CPU interface, 13 ... Window control processing section, 14 ... Data interface, 15 ... Priority determination section, 16 ... Color code memory address processing section, 20 ... Background processing section, 30 ... Object processing unit, 40 ... Color code memory, 50 ... Display control processing unit, 60 ... Display, SR1 to SR32, SR101 to SR132 ... Shift register, DE1, DE2 ... Decoder, SE1, SE2, SE3 ... Selector, INV ... Inverter, FF1, FF2 ... Delay type flip-flop.

Claims (3)

[Claims] 1. An image processing apparatus for performing a predetermined process on an image signal forming an image on a screen by scanning a horizontal scanning line a plurality of times in the vertical direction, and for a predetermined area on the screen. Storage means for storing window-on signal data for one horizontal scanning line indicating that specific image processing is to be performed; and window-on signal data for one horizontal scanning line for writing data in the storage means during a horizontal blanking period. , Control is performed so as to read out the data of the window-on signal for one horizontal scanning line written in the storage means during a period in which the image of the processed image signal is displayed on the display means by performing a predetermined process on the image signal. An image processing apparatus comprising a storage control unit. 2. An image processing apparatus which scans a horizontal scanning line a plurality of times in the vertical direction to perform a predetermined process on an image signal forming an image on a screen, wherein First storage means for storing the data of the window-on signal for one horizontal scanning line of an odd number line indicating that specific image processing is to be performed, and one horizontal scanning line of an even number line indicating to perform the specific image processing. The second storage means for storing the data of the window-on signal for one minute, and the line switching signal indicating the switching of the horizontal scanning lines, based on the one horizontal scanning line of the even lines at the time of displaying the image of the image signal of the even lines. Data of the window-on signal is read out from the second storage means, and the data of the window-on signal for one horizontal scanning line of the odd-numbered line following the displayed even-numbered line is changed to the first data. Of the image signal of the odd-numbered line, the data of the window-on signal for one horizontal scanning line of the odd-numbered line is read from the first storage means and displayed. 1 of even line following odd line
The data of the window-on signal for the horizontal scanning line is converted into the second
An image processing apparatus, comprising: a storage control unit that controls to write to the storage unit. 3. The image processing device according to claim 2, wherein the line switching signal is data output from a control device of the image processing device.