JPH0611015B2 - Chip coil manufacturing method - Google Patents

Chip coil manufacturing method

Info

Publication number
JPH0611015B2
JPH0611015B2 JP58088045A JP8804583A JPH0611015B2 JP H0611015 B2 JPH0611015 B2 JP H0611015B2 JP 58088045 A JP58088045 A JP 58088045A JP 8804583 A JP8804583 A JP 8804583A JP H0611015 B2 JPH0611015 B2 JP H0611015B2
Authority
JP
Japan
Prior art keywords
void layer
layer forming
forming portion
laminated
laminated body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58088045A
Other languages
Japanese (ja)
Other versions
JPS59213118A (en
Inventor
治文 万代
充弘 村田
国三郎 伴野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP58088045A priority Critical patent/JPH0611015B2/en
Publication of JPS59213118A publication Critical patent/JPS59213118A/en
Publication of JPH0611015B2 publication Critical patent/JPH0611015B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041Printed circuit coils
    • H01F41/043Printed circuit coils by thick film techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)

Description

【発明の詳細な説明】 本発明は、チップコイルの製造方法に関する。The present invention relates to a method for manufacturing a chip coil.

近年、半導体素子の発展に伴って、電子機器、電子回路
の小型化、高集積化の要求からコイルのチップ化が進め
られている。このチップコイルは、巻線型と積層型に大
別される。巻線型のチップコイルでは、Qを始めとする
特性は良好であるが、巻線が露出しているために取扱い
上難点がある。この欠点を解決するために全体を樹脂モ
ールドしたものが市販されているが大幅にコスト高とな
っている。一方、積層型のチップコイルは、磁性材料か
ら成るペーストとAg、Pdなどから成る電極ペーストを交
互に印刷した後に焼結されて製造されるが、電極材の比
抵抗が高いためにQが悪く、また貴金属を使用するため
にコスト高となっている。
In recent years, along with the development of semiconductor elements, the coil is being made into a chip because of the demand for miniaturization and high integration of electronic devices and circuits. This chip coil is roughly classified into a wire wound type and a laminated type. A wire-wound chip coil has good characteristics such as Q, but has a difficulty in handling because the wire is exposed. In order to solve this drawback, a resin-molded product is commercially available, but the cost is significantly high. On the other hand, the laminated chip coil is manufactured by alternately printing a paste made of a magnetic material and an electrode paste made of Ag, Pd, etc., and then sintering the paste, but the Q of the electrode chip is poor due to the high specific resistance of the electrode material. Also, the cost is high due to the use of precious metals.

本発明の目的は、上述の技術的課題を解決し、Qが高く
低コストのチップコイルの製造方法を提供することであ
る。
An object of the present invention is to solve the above technical problems and to provide a method for manufacturing a chip coil having a high Q and a low cost.

以下、図面によって本発明の実施例について詳細に説明
する。第1図(a)〜(g)は本発明の一実施例のチップコイ
ルの製造工程を説明するための平面図であり、第2図は
完成したチップコイルの断面図である。本発明に従うチ
ップコイルの製造方法では、先ず絶縁性の磁性体生シー
トの積層体1〜7が準備される。この積層体1〜7の内
の積層体2〜6は、焼成の際に分解または追出されるカ
ーボンなどの可燃材料若しくは可燃材料と磁性体粉末か
ら成るペーストによって、空隙層形成部8〜12がスク
リーン印刷などによって形成される。これらの空隙層形
成部8〜12は、後述のように焼成によって空隙層とな
る。積層体2の空隙層形成部8は、積層体2の下部の縁
に露出して上部に至り、積層体2の上端に平行に延在す
る。この下部の縁に露出した部分17は、後述のように
一方の端子となる。積層体3の空隙層形成部9は、貫通
したスルーホール13が形成された上部から下部に至
り、下端に平行に延在する。このスルーホール13は、
積層体3を積層体2上に載せたときに、積層体2の空隙
層形成部8の端部に臨む所定の位置に形成される。積層
体4の空隙層形成部10は、上端と平行に延び、さらに
貫通したスルーホール14が形成された下部に至る。こ
のスルーホール14は、積層体4を積層体3上に載せた
ときに、積層体3の空隙層形成部9の端部に臨む所定の
位置に形成される。積層体5の空隙層形成部11は、貫
通したスルーホール15を有し、積層体3と同様に形成
されている。積層体6の空隙層形成部12は、貫通した
スルーホール16が形成されている下部から上部に至
り、上端に露出して平行に延在する。上端に露出してい
る部分18は後述のように他方の端子となる。スルーホ
ール16は、積層体6を積層体5上に載せたときに、積
層体5の空隙層形成部11の端部に臨む所定の位置に形
成されている。第1図では、積層体1〜7が、1枚ずつ
準備された例を示したけれども、他の実施例として、積
層体2〜6を多数枚それぞれ印刷した後にカットして準
備してもよい。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1 (a) to 1 (g) are plan views for explaining the manufacturing process of the chip coil of one embodiment of the present invention, and FIG. 2 is a sectional view of the completed chip coil. In the method of manufacturing the chip coil according to the present invention, first, the laminated bodies 1 to 7 of the insulating magnetic green sheets are prepared. In the laminates 2 to 6 among the laminates 1 to 7, the void layer forming portions 8 to 12 are formed by a combustible material such as carbon that is decomposed or expelled during firing or a paste composed of a combustible material and magnetic powder. It is formed by screen printing or the like. These void layer forming portions 8 to 12 become void layers by firing as described later. The void layer forming portion 8 of the laminated body 2 is exposed at the lower edge of the laminated body 2, reaches the upper portion, and extends parallel to the upper end of the laminated body 2. The portion 17 exposed at the lower edge serves as one terminal as described later. The void layer forming portion 9 of the laminated body 3 extends from the upper portion where the through hole 13 penetrating is formed to the lower portion and extends in parallel to the lower end. This through hole 13
When the laminated body 3 is placed on the laminated body 2, it is formed at a predetermined position facing the end of the void layer forming portion 8 of the laminated body 2. The void layer forming portion 10 of the laminated body 4 extends in parallel with the upper end and reaches the lower portion where the through hole 14 is further formed. The through hole 14 is formed at a predetermined position facing the end of the void layer forming portion 9 of the laminated body 3 when the laminated body 4 is placed on the laminated body 3. The void layer forming portion 11 of the laminated body 5 has a through hole 15 penetrating therethrough and is formed similarly to the laminated body 3. The void layer forming portion 12 of the stacked body 6 extends from the lower portion where the through hole 16 is formed to the upper portion, is exposed at the upper end, and extends in parallel. The portion 18 exposed at the upper end becomes the other terminal as described later. The through hole 16 is formed at a predetermined position facing the end of the void layer forming portion 11 of the laminated body 5 when the laminated body 6 is placed on the laminated body 5. Although FIG. 1 shows an example in which the laminated bodies 1 to 7 are prepared one by one, as another embodiment, a plurality of laminated bodies 2 to 6 may be printed and then cut to prepare. .

以上のように構成されている複数枚の積層体1〜7を準
備した後、本発明では、積層体1上に積層体2を載せ、
さらにその上に積層体3を載せ、順次このようにして積
層体1〜7を積層する。この積層された状態において
は、積層体2の空隙層形成部8は、積層体3のスルーホ
ール13を介して空隙層形成部9に連なり、同様に積層
体3の空隙層形成部9は、積層体4のスルーホール14
を介して空隙層形成部10に連なる。以下このように積
層体6の空隙層形成部12までコイル状に連なる。
After preparing a plurality of laminated bodies 1 to 7 configured as described above, in the present invention, the laminated body 2 is placed on the laminated body 1,
Further, the laminate 3 is placed thereon, and the laminates 1 to 7 are sequentially laminated in this manner. In this laminated state, the void layer forming portion 8 of the laminate 2 is connected to the void layer forming portion 9 through the through hole 13 of the laminate 3, and similarly, the void layer forming portion 9 of the laminate 3 is Through hole 14 of laminated body 4
Through the gap layer forming portion 10. Thereafter, the void layer forming portion 12 of the laminated body 6 is connected in a coil shape in this manner.

上記した例では、積層体1〜4を1枚ずつ準備したが、
多数枚それぞれ印刷されたものをカットして準備しても
よい。また積層体1〜4および空隙層形成部8〜12を
順次印刷方式で形成してもよい。
In the above example, the laminated bodies 1 to 4 were prepared one by one,
It may be prepared by cutting a plurality of printed sheets. Further, the laminated bodies 1 to 4 and the void layer forming portions 8 to 12 may be sequentially formed by a printing method.

このように積層した後、焼成炉に入れて所定の高温度で
焼成して一体的な焼結体とする。空隙層形成部8〜12
のペーストは、前述のように焼成の際に分解または追出
される可燃材料若しくは可燃材料と磁性体粉末から成る
ので、焼成によって積層体2〜6の前記ペーストで印刷
された空隙層形成部8〜12は、空隙層となる。この空
隙層は、スルーホール13,14,15,16を介して
コイル状に連続する。
After stacking in this way, it is placed in a firing furnace and fired at a predetermined high temperature to form an integral sintered body. Void layer forming part 8 to 12
The paste of No. 2 is composed of a combustible material or a combustible material that is decomposed or expelled during firing as described above, and a magnetic substance powder. Therefore, the void layer forming portions 8 to 8 printed with the paste of the laminates 2 to 6 by firing. 12 is a void layer. This void layer is continuous in a coil shape through the through holes 13, 14, 15, 16.

そして、このように内部に連続する空隙層が形成された
焼結体の部分17、18が存在する相対する端部に、焼
付けによりポーラス状の外部端子19,20を形成す
る。
Then, the porous external terminals 19 and 20 are formed by baking at the opposite ends where the portions 17 and 18 of the sintered body in which the continuous void layers are formed are present.

次いで、この両端部に外部端子19,20が形成された
焼結体をPb,Snあるいはこれらの合金などの低融点金属
の溶融槽に浸漬し、加圧する。これにより、溶融した金
属をポーラス状の外部端子19,20を介して充填す
る。その後、溶融槽から出して自然放冷することによっ
てコイル状に連続した導電部が第2図に示されるように
形成される。このように本発明に従うチップコイルの製
造方法では、低融点金属によってコイル状に連続した導
電部を形成するので、コストが低く、しかもQが高いチ
ップコイルを得ることが可能となる。
Next, the sintered body having the external terminals 19 and 20 formed on both ends thereof is dipped in a melting bath of a low melting point metal such as Pb, Sn, or an alloy thereof, and pressurized. As a result, the molten metal is filled through the porous external terminals 19 and 20. After that, it is taken out of the melting tank and naturally cooled to form a continuous conductive portion in a coil shape as shown in FIG. As described above, in the method of manufacturing the chip coil according to the present invention, since the conductive portion continuous in a coil shape is formed of the low melting point metal, it is possible to obtain a chip coil having a low cost and a high Q.

また、上記の溶融槽から焼結体を取り出す際、外部端子
19,20が、溶融金属が外に流れ出す際のバリアとな
り、内部に欠陥のないコイル状の連続した導電部を形成
することができる。
Further, when the sintered body is taken out from the above-mentioned melting tank, the external terminals 19 and 20 serve as barriers when the molten metal flows out, so that a coil-shaped continuous conductive portion having no defect can be formed inside. .

上記積層体3について説明すれば、空隙層形成部9は第
3図に示すようにコ字型に形成してもよい。また図示し
ないが積層体4の空隙層形成部10は逆コ字型となる。
Explaining the laminate 3, the void layer forming portion 9 may be formed in a U shape as shown in FIG. Although not shown, the void layer forming portion 10 of the laminated body 4 has an inverted U-shape.

以上のように本発明によれば、スルーホールを介してコ
イル状に連続した空隙層を焼成によって形成し、前記空
隙層およびスルーホールに溶融状態の低融点金属を圧入
してコイル状に連続した導電部を形成するので、低コス
トでしかもQの高いチップコイルを得ることが可能とな
る。
As described above, according to the present invention, a void layer continuous in a coil shape is formed through firing through a through hole, and a low-melting-point metal in a molten state is press-fitted into the void layer and the through hole to continuously form a coil shape. Since the conductive portion is formed, it is possible to obtain a chip coil having low cost and high Q.

さらに、溶融金属の充填の後溶融槽から焼結体を取り出
す際、外部端子が、溶融金属が外に流れ出す際のバリア
となり、内部に欠陥のないコイル状の連続した導電部を
形成することができるので、これによりインダクタンス
特性にバラツキのないチップコイルを製造することがで
きるようになる。
Further, when the sintered body is taken out of the melting tank after the molten metal is filled, the external terminal serves as a barrier when the molten metal flows out, and a continuous coil-shaped conductive portion having no defect can be formed inside. As a result, it becomes possible to manufacture a chip coil having no variation in inductance characteristics.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(g)は本発明の一実施例の製造工程を説明す
るための平面図、第2図は完成したチップコイルの断面
図、第3図は本発明の他の実施例の平面図である。 1〜7…積層体、8〜12…空隙層形成部、13〜16
…スルーホール。
1 (a) to 1 (g) are plan views for explaining a manufacturing process of an embodiment of the present invention, FIG. 2 is a sectional view of a completed chip coil, and FIG. 3 is another embodiment of the present invention. It is a top view of an example. 1-7 ... laminated body, 8-12 ... void layer formation part, 13-16
… Through holes.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】焼成によって空隙層となる空隙層形成部
と、前記空隙層形成部の端部の所定位置に貫通したスル
ーホールとを有する絶縁性の積層体を複数枚準備し、各
積層体の前記空隙層形成部が前記スルーホールを介して
コイル状に連続するように前記積層体を積層し、前記積
層された積層体を焼成して前記空隙層形成部を空隙層と
成すとともに、焼結体の両端部にポーラス状の外部端子
を形成し、前記空隙層および前記スルーホールに溶融状
態の低融点金属をポーラス状の外部端子を介して充填し
てコイル状の連続した導電部を形成することを特徴とす
るチップコイルの製造方法。
1. A plurality of insulating laminates having a void layer forming portion to be a void layer by firing and a through hole penetrating at a predetermined position at an end portion of the void layer forming portion are prepared, and each laminate is provided. The laminated body is laminated so that the void layer forming portion is continuous in a coil shape through the through hole, and the laminated laminate body is fired to form the void layer forming portion as a void layer, and is baked. Porous external terminals are formed at both ends of the united body, and the void layer and the through hole are filled with a low melting point metal in a molten state through the porous external terminals to form a continuous conductive portion in a coil shape. A method of manufacturing a chip coil, comprising:
JP58088045A 1983-05-18 1983-05-18 Chip coil manufacturing method Expired - Lifetime JPH0611015B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58088045A JPH0611015B2 (en) 1983-05-18 1983-05-18 Chip coil manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58088045A JPH0611015B2 (en) 1983-05-18 1983-05-18 Chip coil manufacturing method

Publications (2)

Publication Number Publication Date
JPS59213118A JPS59213118A (en) 1984-12-03
JPH0611015B2 true JPH0611015B2 (en) 1994-02-09

Family

ID=13931855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58088045A Expired - Lifetime JPH0611015B2 (en) 1983-05-18 1983-05-18 Chip coil manufacturing method

Country Status (1)

Country Link
JP (1) JPH0611015B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245202A (en) * 1984-05-21 1985-12-05 Nippon Ferrite Ltd Inductance element
JPS63299222A (en) * 1987-05-29 1988-12-06 Toko Inc Manufacture of laminated inductor
JPS63299221A (en) * 1987-05-29 1988-12-06 Toko Inc Manufacture of laminated inductor
JPH01287905A (en) * 1988-05-13 1989-11-20 Murata Mfg Co Ltd Inductance element and manufacture thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771110A (en) * 1980-10-20 1982-05-01 Matsushita Electric Ind Co Ltd Chip coil

Also Published As

Publication number Publication date
JPS59213118A (en) 1984-12-03

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