JPH06109781A - Power reset circuit and display error prevention device using the circuit - Google Patents

Abstract

PURPOSE:To constitute a power reset circuit without using either of enhancement and depression type processes. CONSTITUTION:Reference voltage REF2 is generated, by use of a transistor Tr incidental to an MOS process, and a Zener diode connected thereto. This reference voltage REF2 drops at a gradient approximately equal to the case of power voltage VDD, when the voltage VDD is equal to or above the breakdown voltage of another Zener diode ZD. In this case, another reference voltage REF1 is available from the division of the voltage VDD with resistors R3 and R4. The reference voltage REF1 is compared with the reference voltage RE2 via a comparator 10. When the reference voltage REF1 is higher than the reference voltage REF2, a power reset signal RESET is generated at high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply reset circuit that resets the operation of an on-board device in response to a decrease in power supply voltage.

[0002]

2. Description of the Related Art In equipment such as a microcomputer, a power supply reset circuit is usually mounted because a malfunction occurs when the power supply voltage drops. This power supply reset circuit is configured as an IC or a part thereof, and has a configuration as shown in FIG. 10, for example.

This figure shows an enhancement type NMOS FET and a depletion type NMOS FE.
This is a circuit that generates two kinds of reference voltages by T and compares them to generate a power supply reset signal.

That is, a depletion type NMOS FE
Tr1 which is T and enhancement type NMOS FET
While using Tr2 that is a transistor to detect a decrease in the power supply voltage V _DD to generate a reference voltage REF1, an enhancement type NMOS FET, Tr3, and a depletion type NM are used.
Tr4, which is an OS FET, is used to detect a decrease in the power supply voltage V _DD and generate a reference voltage REF2. Comparator 10
Compares these reference voltages REF1 and REF2 and sets the power supply reset signal RESET to H when the former is high. That is, the reference voltages REF1 and REF2 generated by such a circuit are REF1 <REF2 in a region where the power supply voltage V _DD is high as shown in FIG. 11, but REF1> REF when the power supply voltage V _DD is reduced.
It becomes 2. Therefore, using such a change in the reference voltage,
By comparing REF1 and REF2 in the comparator 10, it is possible to detect a decrease in the power supply voltage V _DD .
By supplying the power supply reset signal RESET thus obtained to each circuit of the microcomputer or the like, it is possible to reset and prevent malfunction.

[0005]

However, when a circuit is to be constructed by using the enhancement type NMOS FET and the depletion type NMOS FET in this way, a mask or the like is prepared for each of the enhancement type and the depletion type. Since it is necessary to provide a manufacturing process for this, the manufacturing cost increases. Also,
Enhancement type and depletion type NMOS FE
Since T is formed by another diffusion process, its threshold voltage varies with different tendencies. Further, although this threshold value changes with temperature, the tendency of this change is different between the enhancement type and the depletion type. Therefore, in the related art, in addition to the problem that the manufacturing cost is high, there is a problem that the voltage value of the power supply reset signal changes due to the variation of the threshold value and its temperature characteristic.

The present invention has been made to solve the above problems, and it is an enhancement type NMOS FET and a depletion type NMOS FET.
An object of the present invention is to make it possible to manufacture a power supply reset circuit by a MOS process without using the above and the like, thereby reducing the manufacturing cost and suppressing variations in power supply reset signals and temperature changes thereof.

[0007]

In order to achieve such an object, a power supply reset circuit according to a first aspect of the present invention divides a power supply voltage V _DD into a first reference voltage REF1.
A voltage dividing means for generating a voltage, a switching element that outputs a voltage that drops at a gradient substantially the same as the power supply voltage V _DD when turned off as a second reference voltage REF2, and a first reference voltage RE.
Comparing means for comparing F1 with the second reference voltage REF2 and outputting the power supply reset signal RESET when the first reference voltage REF1 is high, the first reference voltage REF1
And the second reference voltage REF2 are compared, the power supply voltage _VDD
Is detected.

In the power supply reset circuit according to the second aspect of the present invention, the power supply voltage V _DD is divided to generate the first reference voltage R.
Voltage dividing means for generating EF1 and power supply voltage V when turned on
The second reference voltage R is a voltage that decreases with almost the same gradient as _DD.
The switching element that outputs as EF2 is compared with the first reference voltage REF1 and the second reference voltage REF2, and the second reference voltage REF2 is compared.
Power supply reset signal RE when the reference voltage REF2 of
And comparing means for outputting SET, and detecting a decrease in the power supply voltage V _DD by comparing the first reference voltage REF1 and the second reference voltage REF2.

Further, the power supply reset circuit according to a third aspect of the present invention is characterized in that the switching element is a parasitic transistor generated in a MOS process.

According to a fourth aspect of the present invention, there is provided an on-screen display control means for displaying characters on a screen of a display device in a superimposed manner based on data stored in a volatile storage element. , Power supply voltage V
_And a power supply reset circuit of the present invention which outputs a power supply reset signal and supplies at least the volatile memory element when _DD is lowered.

[0011]

In the power reset circuit according to the first or second aspect of the present invention, the first reference voltage REF1 is the power supply voltage V.
It is generated by the partial pressure of _DD . Therefore, the first reference voltage REF1 drops with a slope smaller than the slope with which the power supply voltage V _DD drops. On the other hand, the switching element outputs, as the second reference voltage REF2, a voltage that drops at a gradient substantially equal to the power supply voltage V _DD when it is off or on. Therefore, when the switching element is off or on, the slope of decrease of the second reference voltage REF2 is the same as the first reference voltage REF1.
Since the power supply voltage V _DD has a certain value, the both values are equal. Therefore, by comparing the magnitude relationship between the first reference voltage REF1 and the second reference voltage REF2, it is possible to detect a decrease in the power supply voltage V _DD and use this to generate a power supply reset signal. . Further, the power supply reset circuit having such a configuration uses the second reference voltage R as the switching element.
Since only the switching element for generating EF2 is used, it is not necessary to use both the depletion type process and the enhancement type process during manufacturing.

In a third aspect, the switching element according to the first or second aspect is configured as a parasitic transistor. That is, since a transistor that is parasitically generated in the MOS process can be used as the transistor according to the first to fifth aspects, the number of manufacturing steps does not increase due to the transistor configuration.

According to another aspect of the present invention, the power supply reset circuit supplies the power supply reset signal to at least the volatile storage element when the power supply voltage V _DD drops. This volatile storage element stores data indicating a character or the like to be superimposed and displayed on the screen of the display device. Therefore, even when the power supply voltage is lowered and then restored, the characters and the like relating to the on-screen display are not disturbed and displayed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. The same components as those of the conventional example shown in FIGS. 10 and 11 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 shows the configuration of a power supply reset circuit according to the first embodiment of the present invention. As shown in this figure, this embodiment includes Tr1 to Tr4 in the conventional example.
Instead of transistor Tr, Zener diode ZD,
Resistors R1 to R4 are used. In addition, this embodiment is a circuit manufactured by a P sub N well MOS process.

The resistors R3 and R4 generate the reference voltage REF1 by dividing the power supply voltage V _DD . The reference voltage REF1 is input to the non-inverting input terminal of the comparator 10. The emitter of the transistor Tr is connected to the inverting input terminal of the comparator 10. The reference voltage REF2 is output from the emitter of the transistor Tr.

The transistor Tr for generating the reference voltage REF2 is a transistor parasitically generated in the MOS process as described later. The base of the transistor Tr is connected to the power supply via the Zener diode ZD, and is also grounded via the resistor R2.
The collector of the transistor Tr is grounded, and the emitter is connected to the power supply via the resistor R1.

The operation of this embodiment is shown in FIG. As shown in this figure, the reference voltage REF1 is a voltage obtained by dividing the power supply voltage V _DD by the resistors R3 and R4, and therefore decreases in proportion to the power supply voltage V _DD . On the other hand, the reference voltage REF2 decreases non-linearly by the operation of the transistor Tr, and the region C in which the power supply voltage V _DD is equal to or higher than the breakdown voltage V _Z of the Zener diode ZD and the region A in which the transistor Tr is turned on and the voltage between base and emitter is V _F or lower. Then, the voltage decreases with the same gradient as the power supply voltage V _DD . In the power supply voltage _{V DD V F} or _{V Z} the following areas see B, voltage REF2 takes a constant value.

The non-linear decrease of the reference voltage REF2 is due to the following operation. That is, in the region A where the power supply voltage V _DD is lower than V _F , the transistor T
Since r is off, its base-emitter voltage is equal to the power supply voltage V _DD . Since the reference voltage REF2 is the emitter potential of the transistor Tr, it increases with a larger gradient than the reference voltage REF1 as shown in the figure.

Next, when the power supply voltage V _DD exceeds V _F , the transistor Tr is turned on, so that the reference voltage REF2 becomes
The value of the power supply voltage V _DD at this point is maintained. That is, in the region B where the power supply voltage V _DD is equal to or higher than the voltage V _F , the reference voltage REF2 is maintained at V _F. After that, when the power supply voltage V _DD reaches the breakdown voltage V _Z of the Zener diode ZD, the base potential of the transistor Tr is pulled up to the power supply voltage V _DD , so that the transistor Tr is turned off again. Therefore, the power supply voltage _{V DD} in the Zener diode ZD breakdown voltage _{V Z} or more regions C, the reference voltage REF2 is increased at the same slope as the power supply voltage _{V DD.} Reference voltage REF2 in this manner, a non-linear with respect to power supply voltage _{V D D.}

Such reference voltages REF1 and REF2
As is clear from the tendency of, both have the same value at a certain point in the regions B and C. In the region of the power supply voltage V _DD sandwiched by these two points, the reference voltage REF1
Since> REF2, the output of the comparator 10 becomes H.
In this embodiment, the power supply reset signal RE is utilized by utilizing this characteristic.
This is to generate SET.

That is, when the electric circuit having the configuration shown in FIG. 1 is mounted on a device such as a microcomputer, the reference voltage REF1 is accompanied by a decrease in the power supply voltage V _DD.
And REF2 have a relationship of REF2> REF1 to REF1>
Change to REF2. At this time, the output of the comparator 10 is L
Since the value changes from the H value to the H value, by using the output of the comparator 10 as the power supply reset signal RESET, it is possible to apply a reset to each part of the device such as the microcomputer according to the decrease of the power supply voltage V _DD .

FIG. 3 shows how the transistor Tr is generated. As shown in this figure, N on the P-sub
When the well is doped and the N well is further doped with P ⁺ and N ⁺ , the P sub is the collector, the N well is the base, and the N well is N.
A parasitic transistor is formed by using P ⁺ doped on the well as an emitter. The transistor Tr in the present embodiment is configured by using such a parasitic transistor, and therefore does not require any special manufacturing process.

As described above, according to this embodiment, since the power supply reset circuit can be constructed without using both the enhancement type and the depletion type processes, the manufacturing process is simplified and the manufacturing cost is reduced. Will be reduced. In addition, the power supply reset signal R such as the variation in the threshold value between the enhancement type and the depletion type and the temperature change thereof.
Since the change factor of ESET is eliminated, the power supply reset signal can be generated more stably. In addition, since no special process is required for manufacturing the transistor Tr, the number of manufacturing steps does not increase.

Further, in this embodiment, the Zener diode ZD is connected to the base of the transistor Tr. However, the present invention is not limited to such a configuration. For example, as shown in FIG. 4 as the second embodiment, the terminal 12 may be provided at the base of the transistor Tr and the reset signal RESET (-) may be applied from the outside of the terminal 12. With such a configuration, when the reset signal RESET (-) is H, the transistor Tr operates in a breakdown manner.

FIG. 5 shows the configuration of a power supply reset circuit according to the third embodiment of the present invention. In this embodiment, N
It is a circuit manufactured by the sub-P well MOS process.

In this embodiment, the reference voltage REF1 is input to the inverting input terminal of the comparator 10. The emitter of the transistor Tr is connected to the non-inverting input terminal of the comparator 10.

The transistor Tr for generating the reference voltage REF2 is a P-sub N-well MO transistor as shown in FIG.
It is a transistor that is parasitically generated in the S process. That is, as shown in FIG. 7, when the P well is doped on the N sub, and the P well is further doped with N ⁺ and P ⁺ , the N sub is doped on the collector, the P well on the base, and the P well on the P well. A parasitic transistor is formed using N ⁺ as an emitter. Transistor T in this embodiment
r is also constructed by using such a parasitic transistor, and thus does not require a special manufacturing process.

FIG. 6 shows the operation of this embodiment. As shown in this figure, the reference voltage REF2 is non-linearly lowered by the operation of the transistor Tr, and the region C in which the power supply voltage V _DD is equal to or higher than the breakdown voltage V _Z of the Zener diode ZD and the base-emitter voltage at which the transistor Tr is turned on. In a region A below V _F , it takes a constant value. In the power supply voltage _{V DD V F} or _{V Z} the following areas see B, voltage REF2 is reduced by the same gradient and the power supply voltage _{V DD.}

The non-linear decrease of the reference voltage REF2 is due to the following operation. That is, in the region A where the power supply voltage V _DD is lower than V _F , the transistor T
Since r is off, its base potential is equal to ground potential. The reference voltage REF2 is the emitter potential of the transistor Tr and is therefore constant as shown in the figure.

[0031] Referring now supply voltage _{V DD} is greater than _{V F,} the transistor Tr is turned on, the reference voltage REF2 is
The rise starts in proportion to the power supply voltage V _DD . That is,
In the region B in which the power supply voltage V _DD is equal to or higher than the voltage V _F , the reference voltage REF2 increases more steeply than the reference voltage REF. After that, when the power supply voltage V _DD reaches the breakdown voltage V _Z of the Zener diode ZD, the base potential of the transistor Tr is pulled down to the ground voltage, so that the transistor Tr is turned off again. Therefore, in the region C where the power supply voltage V _DD is equal to or higher than the Zener diode ZD breakdown voltage V _Z ,
The reference voltage REF2 becomes constant. In this way, the reference voltage RE
F2 is non-linear with respect to the power supply voltage V _DD .

Such reference voltages REF1 and REF2
As is clear from the tendency of, both have the same value at a certain point in the regions B and C. In the region of the power supply voltage V _DD sandwiched by these two points, the reference voltage REF1
Since <REF2, the output of the comparator 10 becomes H.
In this embodiment, the power supply reset signal RE is utilized by utilizing this characteristic.
This is to generate SET.

That is, when the electric circuit having the structure shown in FIG. 5 is mounted on a device such as a microcomputer, the reference voltage REF1 is accompanied by a decrease in the power supply voltage V _DD.
And REF2 have a relationship of REF2 <REF1 to REF1 <
Change to REF2. At this time, the output of the comparator 10 is L
Since the value changes from the H value to the H value, by using the output of the comparator 10 as the power supply reset signal RESET, it is possible to apply a reset to each part of the device such as the microcomputer according to the decrease of the power supply voltage V _DD .

As described above, also in this embodiment, the power supply reset circuit can be constructed without using both the enhancement type process and the depletion type process.

Further, in this embodiment, the Zener diode ZD is connected to the base of the transistor Tr. However, the present invention is not limited to such a configuration. For example, as shown in FIG. 8 as the fourth embodiment, the terminal 12 may be provided at the base of the transistor Tr and the reset signal RESET (−) may be applied from the outside of the terminal 12.

The power reset circuit according to each embodiment of the present invention can be manufactured as an IC by the MOS process as described above, and can also be manufactured by the discrete or bipolar process. Nor. In addition, the Zener diode ZD in the first or third embodiment may be used in a form connected to the terminal 12 in the second or fourth embodiment, that is, externally attached to the IC.

FIG. 9 shows an example of application of each embodiment of the present invention. The device shown in this figure is a video tape recorder (V) having an on-screen display function for superimposing characters and the like on the screen of the display 13.
TR) 14. The on-screen display function is, for example, a function of displaying characters or symbols indicating a channel and a volume on the screen of the display 13. This function is normally performed by an on-screen display IC (OSDI
It is realized by C). In this figure, OSDIC
Is indicated by reference numeral 16.

The OSDIC 16 inputs a video signal indicating a video to be displayed on the screen of the display 13. This video signal represents, for example, a tape playback video supplied from a video playback circuit (not shown) or a video supplied from another device (for example, a television receiver). OSD
The IC 16 reads out data such as characters to be superimposed and displayed from the built-in RAM, processes the video signal based on this data, and outputs a video signal VIDE including images such as characters.
Generate O. At that time, by using the synchronization signal,
Controls the timing of mixing signals related to characters and the like. Therefore, the display 1 is based on the video signal VIDEO.
When an image is displayed on the screen of No. 3, characters or the like will be superimposed and displayed at a predetermined position on the screen.

The VTR 14 in this figure further includes a power supply reset circuit 18 according to any one of the embodiments of the present invention. The power supply reset circuit 18 monitors the power supply voltage by the operation described above, and supplies the reset signal RESET to the OSDIC 16 according to the decrease in the power supply voltage. Therefore, when the power supply voltage decreases, the data on the RAM indicating the characters and the like is cleared.

As described above, the circuits according to the respective embodiments of the present invention are applied to the reset of the OSDIC 16 of the VTR 14, especially the RAM.
When used for resetting data, it is possible to prevent screen disturbance due to power restoration. That is, after the power supply voltage drops, R
When the power is restored without resetting the AM, the data on the RAM at the time of power restoration is not guaranteed, and therefore the characters etc. superimposed on the screen of the display 13 are disturbed for a while. When the reset is added as shown in this figure, the screen is not disturbed, and the person watching the display 13 is not uncomfortable. Also, necessary data can be received from a microcomputer or the like (not shown).

[0041]

As described above, according to the present invention,
The second reference voltage REF is a voltage that is output when the switching element is turned off or on and that drops with a slope that is substantially the same as the power supply voltage.
Since it is set to 2, the power reset circuit can be manufactured without using both the enhancement type and depletion type processes, and the manufacturing process can be simplified and the manufacturing cost can be reduced. Further, unlike the case where both the depletion type and enhancement type MOS FETs are used, the power source reset signal is stabilized because it is not affected by the variation in threshold value of each FET and its temperature characteristic.

Further, according to the present invention, the voltage for turning off or turning on the switching element can be given from a built-in Zener diode, an external Zener diode or the like. Further, when externally attached, the operation can be set by selecting the Zener diode to be externally attached.

According to the third aspect of the present invention, since the transistor for generating the second reference voltage REF2 is configured as a transistor parasitically generated in the MOS process, the transistor can be formed without increasing the number of manufacturing steps. Can be configured.

According to the fourth aspect of the present invention, when the power supply is lowered and then restored, the data relating to the on-screen display is reset, so that the screen is not disturbed and the screen is easier to see. Can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a power supply reset circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation of this embodiment.

FIG. 3 is a diagram showing a generation mechanism of a parasitic transistor in this embodiment.

FIG. 4 is a circuit diagram showing a configuration of a power supply reset circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a power supply reset circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing the operation of this embodiment.

FIG. 7 is a diagram showing a generation mechanism of a parasitic transistor in this embodiment.

FIG. 8 is a circuit diagram showing a configuration of a power supply reset circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing an application example of each embodiment.

FIG. 10 is a circuit diagram showing a configuration of a power supply reset circuit according to a conventional example.

FIG. 11 is a diagram showing the operation of this conventional example.

[Explanation of symbols]

10 comparator 12 terminal 13 display 14 video tape recorder (VTR) 16 on-screen display IC (OSDIC) 18 power reset circuit REF1, REF2 reference voltage V _DD power supply voltage Tr transistor ZD Zener diode R1 to R4 resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 17/22 G 9184-5J

Claims (4)

[Claims] 1. A voltage dividing means for dividing a power supply voltage to generate a first reference voltage, and a second voltage dividing means for decreasing a voltage which is substantially the same as the power supply voltage when turned off.
A switching element that outputs as a reference voltage, and a comparison unit that compares the first reference voltage and the second reference voltage and outputs a power supply reset signal when the first reference voltage is high. A power supply reset circuit characterized by detecting a decrease in a power supply voltage by comparing a reference voltage and a second reference voltage. 2. A voltage dividing means for dividing a power supply voltage to generate a first reference voltage, and a voltage dividing means for decreasing a voltage which is substantially the same as the power supply voltage when turned on.
A switching element that outputs as a reference voltage, and a comparison unit that compares the first reference voltage and the second reference voltage and outputs a power supply reset signal when the second reference voltage is high. A power supply reset circuit characterized by detecting a decrease in a power supply voltage by comparing a reference voltage and a second reference voltage. 3. The power supply reset circuit according to claim 1, wherein the switching element is a parasitic transistor generated in a MOS process. 4. An on-screen display control means for superimposing and displaying characters and the like on a screen of a display device based on data stored in a volatile storage element, and at least a power supply reset signal is output when a power supply voltage drops. Supplying to said volatile memory element.
A power supply reset circuit described above, and a screen erroneous display prevention system.