JPH06105156A - Binarization circuit - Google Patents

Abstract

PURPOSE:To improve picture quality by revising a threshold signal timing to deviate timewise a threshold signal generated in response to a level of an analog picture signal with respect to the analog picture signal so as to suppress void and black level distortion. CONSTITUTION:A capacitor 3 is used to delay timewise a slice level signal outputted from a slice level control circuit 1 by connecting the capacitor 3 to an output terminal of the circuit 1. As a result, a part where the relation of quantity between an analog picture signal and a slice level signal is inverted is caused between the analog picture signal fed to a noninverting input terminal of a comparator 2 and the slice level signal fed to an inverting input terminal. The part is advanced timewise than a substantial character read timing and an edge part of a character read by an image sensor is converted into a binary picture signal for the emphasis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarizing circuit for converting an analog image signal into a binarized image signal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a facsimile apparatus to which a conventional binarization circuit is applied. In FIG. 4, the facsimile apparatus 101 includes a document reading / recording unit 102, a panel unit 103, and a document reading / recording unit 10.
2 and the interface circuit 104 between the panel unit 103,
Mechanism control unit 105, panel unit 103, and mechanism control unit 10 including drivers and sensors such as a document feed motor
5, the interface circuit 106, the CPU 107, and the RO
M108, RAM109, network controller 110, modem 11
1, a communication control unit 112, an information compression / decompression unit 113, and a system bus 114 including a data bus and the like.

The document reading / recording unit 102 is composed of a reading operation unit 102a, a recording operation unit 102b, a reading / recording processing unit 102c, a line memory 102d and a line memory control unit 102e.

Next, the operation will be described with reference to the flowchart of FIG. First, when a power switch (not shown) is turned on, the line memory 102d and the RAM 109 are cleared, and further initialization such as CPU reset is performed (step S1). Next, it is judged whether or not a calling signal is received (step S2), and when the calling signal is received, transmission control is performed by the network control unit 110 (step S2).
6) The reception preparation completion signal is sent from the network control unit 110 to the line via the modem 111 (step S7). After that, the image signal sent from the line is transmitted to the network control unit 110 →
The data is output to the data bus via the modem 111 → communication control unit 112 and stored in the RAM 109. The RAM 109 is used as a reception buffer, and the image signals stored in the RAM 109 are sequentially compressed by the information compression / decompression unit 113 via the data bus.
Sent to. The image signal whose redundancy has been restored by the information compression / decompression unit 113 is stored in the line memory 102d, and the image signal stored in the line memory 102d is read out from the line memory 102d again to be read processing unit / recording processing unit 102c. After that, the image is reproduced as an image record by the recording operation unit 102d (step S8).

Next, it is judged whether or not the reception is completed (step S9), and when the reception is completed, it is further judged whether or not a document is placed (step S3). When a document is placed, it is determined whether or not there is a transfer request (step S4). When there is a transfer request, the mechanism control unit 105 drives a motor for taking in the document to place the document on the plate. (Step S10), and the light source for reading the original is turned on (step S1).
1).

Next, the reading scanning unit 102a scans the original, reads analog image information from the original, and performs shading correction (step S12). The analog image information read by the reading operation unit 102a is converted into a binary image signal via the reading processing unit 102a and is temporarily stored in the line memory 102d. Further information compression /
The redundancy is removed while reading from the line memory 102d according to the mode of the restoration unit 113, and the data is stored in the RAM 109 via the data bus (step S13). At this time, the RAM 109 is used as a transmission buffer,
It is sent to the modem 109 via the communication control unit 112. The signal modulated by the modem 109 is sent from the network control unit 110 to the line (step S14).

FIG. 6 is a circuit block diagram when the document is scanned by the reading scanning unit 102a, the image on the document is read, and the analog image signal obtained as a result is converted into a binary image signal. 6, 121 is a slice level control circuit, 122 is a comparator, and the analog image signal is supplied to the non-inverting input terminal of the comparator 122 and the input terminal of the slice level control circuit 121. The slice level control circuit 121 is a circuit that controls the magnitude of the slice level (threshold) signal to be output according to the level of the input analog image signal. The slice level signal output from the slice level control circuit 121 is supplied to the inverting input terminal of the comparator 122.

FIG. 7 and FIG. 8 are waveform charts showing the waveforms of respective parts of a circuit which is composed of a slice level control circuit 121 and a comparator 122 and which converts an analog image signal into a binary image signal. Depending on the magnitude relationship between the slice level signal generated by the slice level control circuit 121 and the slice level control circuit 121, “white” and “black” are converted into binary information of “1” and “0” by the comparator 122 and output.

[0009]

In the conventional binarization circuit, when converting an analog image signal into a binary image signal,
When the level change of the analog image signal is large and falls below the slice level signal output from the slice level control circuit 121, a binary image signal is obtained as shown in FIG. MTF (Modulation Transfer F
For example, when the level change of the analog image signal is small due to the unction, there is a problem that white characters are continuously drawn, thin characters disappear, or blackened, as shown in FIG.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to suppress the phenomenon of thin characters appearing white or crushed black at a low cost and improving the image quality. It is an object to provide a digitization circuit.

[0011]

According to the present invention, an analog image signal is read by an image sensor or the like, the analog image signal is obtained based on an analog image signal obtained and a threshold signal generated according to the level of the analog image signal. In a binarization circuit for converting the signal into a binarized image signal, the threshold signal output timing changing means for shifting the threshold signal generated according to the level of the analog image signal with respect to the analog image signal in time. It is characterized by having.

[0012]

In the binarization circuit according to the present invention, the threshold signal generated according to the level of the analog image signal is temporally divided with respect to the analog image signal, and based on the analog image signal and the threshold signal. Since the binarized image signal is obtained, even if the level change of the analog image signal is small due to the MTF of the image sensor of the reading operation unit, this can be detected and the binarized image signal can be obtained at low cost. ,
In particular, as a result of the edge portion of the character being emphasized, it is possible to suppress the phenomenon that a thin character is hollowed out or crushed into black, and the image quality can be improved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, an example in which the binarization circuit is applied to a facsimile device will be described, but the present invention is not limited to this, and can be widely applied to devices using the binarization circuit such as a copying machine. It is a thing. Since the configuration of the facsimile apparatus of this embodiment is the same as that of FIG. 4, illustration and description thereof will be omitted, and description will be made below with reference to FIG. Figure 1
FIG. 6 is a circuit block diagram for scanning an original by the reading scanning unit 102a in the facsimile apparatus of this embodiment, reading an image on the original, and converting an analog image signal obtained as a result into a binary image signal.

In FIG. 1, 1 is a slice level control circuit, 2 is a comparator, and an analog image signal is supplied to a non-inverting input terminal of the comparator 2 and an input terminal of the slice level control circuit 1. The slice level control circuit 1 is a circuit that outputs a slice level (threshold value) signal whose size changes according to the level of the input analog image signal. When the analog image signal is at the “white” level, it is at the “white” level. While the slice level signal having the magnitude corresponding to the "black" level is output, the slice level signal having the magnitude corresponding to the "black" level is output. The output terminal of the slice level control circuit 1 is connected to the inverting input terminal of the comparator 2. A capacitor 3 is connected to the output terminal of the slice level control circuit 1.

Next, the operation of the circuit shown in FIG. 1 will be described. When the level change of the supplied analog image signal is small due to the MTF of the image sensor of the reading operation unit, conventionally, the level change of the analog image signal does not reach the slice level signal output from the slice level control circuit 1. The level change of the analog image signal cannot be detected. On the other hand, by connecting the capacitor 3 to the output terminal of the slice level control circuit 1, the capacitor 3 delays the slice level signal output from the slice level control circuit 1 in time. As a result, the relationship between the analog image signal supplied to the non-inverting input terminal and the slice level signal supplied to the inverting input terminal of the comparator 2 is as shown in FIG. 2, and the magnitude of the analog image signal and the slice level signal is large or small. The part where the relationship is reversed occurs. This portion is ahead of the original timing of character reading in time, and the edge portion of the character read by the image sensor is converted into a binary image signal and emphasized.

FIG. 3 is a waveform diagram showing the relationship among the analog image signal, the slice level signal, and the binary image signal when the capacitor 3 is used and when it is not used.

In this embodiment, the slice level signal is delayed with respect to the analog image signal by using the capacitor, but the invention is not limited to the capacitor, and the slice level signal is relatively delayed with respect to the analog image signal. Or anything that can be advanced.

[0018]

As described above, according to the present invention, the threshold signal is temporally divided with respect to the analog image signal, and the image signal binarized based on the analog image signal and the threshold signal is generated. Therefore, even if the level change of the analog image signal is small due to the MTF of the image sensor of the reading operation unit, this can be detected at a low cost and a binarized image signal can be obtained, and especially the edge part of the character is emphasized. As a result, there is an effect that it is possible to improve the image quality by suppressing the phenomenon that thin characters are rendered white or crushed in black.

[Brief description of drawings]

FIG. 1 is a block diagram of a binarizing circuit for converting an analog image signal into a binary image signal according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an analog image signal, a slice level signal, and a binary image signal according to an embodiment of the present invention.

FIG. 3 is a waveform diagram showing a relationship among an analog image signal, a slice level signal, and a binary image signal with and without a capacitor.

FIG. 4 is a block diagram showing a configuration of a conventional facsimile apparatus.

FIG. 5 is a flowchart showing the operation of a conventional facsimile apparatus.

FIG. 6 is a block diagram of a binarizing circuit for converting a conventional analog image signal into a binary image signal.

FIG. 7 is a waveform diagram when converting a conventional analog image signal into a binary image signal.

FIG. 8 is a waveform diagram showing an analog image signal, a slice level signal, and a binary image signal when the level change of the conventional analog image signal is small.

[Explanation of symbols]

 1 Slice Level Control Circuit 2 Comparator 3 Capacitor 101 Facsimile Machine

Claims (1)

[Claims] 1. An image signal obtained by reading an original image with an image sensor or the like and binarizing the analog image signal based on the obtained analog image signal and a threshold signal generated according to the level of the analog image signal. In the binarization circuit for converting into the analog image signal, there is provided threshold signal output timing changing means for shifting the threshold signal generated according to the level of the analog image signal with respect to the analog image signal in time. Binarization circuit to be.