JPH06103767A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To provide a semiconductor memory device where operation current is extremely reduced by means of a memory cell selection circuit which can reduce consumption current at the time of selecting and driving a memory cell. CONSTITUTION: In the memory device of a non-multiplexed address-type, one word line is equally divided into two lines so that the same number of memory cells are given and they are set to be the divided word lines LWL and UWL. The respective divided word lines are connected to private row decoders LRD and URD inputting same decoding signals. A row decoder selector 56 operating based on the address signal CA7 of the highest bit in column address signals executes control so that only one row decoder is enabled and only one divided word line is selected. The number of bit lines where charging/discharging are executed at the time of selecting and driving the memory cell is set to be the half of a conventional number. Thus, consumption current becomes half.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to non-multiplexed addresses.
d address) relates to a memory cell selection circuit of a memory device.

[0002]

2. Description of the Related Art In a semiconductor memory device having a memory cell array having a large number of memory cells, a row address signal and a column address (column add) are known as a generally known technique for selecting a specific memory cell.
ress) signals are known. That is,
By decoding the row address signal to select any one of the many word lines and decoding the column address signal to select any one of the many bit lines, You can select one memory cell.

Multiplexed address
address) In the memory device, the row address signal and the column address signal are input with a time difference through the same input terminal. On the other hand, a non-multiplexed address memory device such as PSRAM (Pseu
do SRAM), the number of address signal input terminals is made equal to the sum of the number of row and column address signals, and row address signals and column address signals are simultaneously input through the respective input terminals. .

The memory device shown in FIG. 5 is an example of a non-multiplexed address memory device, and is a 4-megabit PSR.
The configuration of the AM is schematically shown in a block diagram.

The memory cell array 10 includes 2048 × 256 × 8 (= 4, 1) in a matrix of 2048 word lines and 256 × 8 (= 2048) bit lines.
94, 304) memory cells. The row address buffer 12 has TTL level row address signals A0 to A0 input through the row address signal input terminal.
A10 is input, and CMOS level row address signals RA0 to RA10 are output. The column address buffer 14 receives the TTL-level column address signals A11 to A18 input via the column address signal input terminals.
Input to the CMOS level column address signal CA
0 to CA7 are output. The row decoder 16 and the column decoder 18 receive row address signals RA0 to RA from the row address buffer 12 and the column address buffer 14, respectively.
10 and column address signals CA0 to CA7 are respectively received, and these are decoded to select a word line and a bit line. Sense amplifier / I / O gate 20
Includes a sense amplifier for reading data from the bit line and an I / O gate for transmitting the data read by the sense amplifier to eight data input / output lines.

Then, the data input buffer 22 transmits the data input through the data input / output terminals I / O1 to I / O8 to the data input / output lines. The data output buffer 24 stores the read data transmitted from the sense amplifier to the data input / output line in the data input / output terminal I / O.
1 to I / O8.

The refresh controller 26 controls the refresh operation, and the refresh timer 28 provides the refresh master clock. The refresh counter 30 is controlled by the refresh controller 26 to generate a refresh address signal and supply it to the row decoder 16. The control signal generating circuit 31 includes a control signal CE, a bar OE / bar RFSH, and a bar WE which are supplied from the outside.
Are combined to generate a control signal necessary for the operation of each part.

Therefore, the memory device shown in FIG.
It has eight memory column blocks each having 56 bit lines, and each memory column block shares 2048 word lines with each other. Also, PSRA
The M memory cell is a dynamic cell including one transistor and one capacitor. FIG. 6 shows the relationship between the dynamic cell and the word line WL and the bit line BL. FIG. 6 specifically shows a part of the memory cell array 10 of FIG. Since the structure of the memory cell array as shown in the figure is a well-known technique, the description thereof will be omitted.

FIG. 7 is a block diagram showing an example of a conventional word line selection circuit. FIG. 7 is a block diagram showing the relationship between the memory cell array corresponding to one memory column block in FIG. 5, a column decoder and a row decoder.

2048 word lines WL0 to WL204
7 are divided into 8 groups, and each word line group is connected to each row decoder 32, 34, 36. That is, the memory column block shown in the figure is further divided into eight row blocks, and row decoders 32, 34 and 36 are provided to each row block in a ratio of 1: 1. Only one of the row decoders 32, 34 and 36 can be operated by the block selection address signal in the row address signal. Are decoded to selectively drive one of the word lines.

On the other hand, 256 bit lines BL0 to BL2
The column decoder 38 is connected to the column decoder 38, and the column decoder 38 outputs eight column address signals CA0 to CA7.
Is selected to select any one of 256 bit lines.

Therefore, the memory column block shown in FIG. 7 has a total of 2048 × 256 (= 524,288) dynamic memory cells.

In FIG. 7, when one word line is selected to selectively drive a specific memory cell, all 256 memory cells connected to the selected word line are activated. Since the data of these activated memory cells are transmitted to the corresponding bit line, 2
All of the 56 bit lines BL0 to BL255 perform the charging and discharging operations, resulting in wasting power.

That is, when a predetermined word line is selected to access a specific memory cell, all the bit lines connected to the memory cells sharing this word line perform the charge / discharge operation. As a result, a large amount of bit line charge / discharge current will flow. As a result, the memory cell operating current including the bit line charging / discharging current, the sense amplifier driving current, and the word line driving current when operating the memory cell increases as the capacity of the memory device increases. is there. Therefore, in particular,
In a highly integrated memory device used in a portable computer using a battery power source, such as a laptop or a notebook computer, it is an essential issue to reduce the operating current. Therefore, it is necessary to solve such a problem. Has been done.

[0015]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor memory device which requires a smaller operating current. Another object of the present invention is to provide a memory cell selection circuit capable of reducing the operating current required for selective driving of memory cells in a non-multiplexed address memory device having dynamic memory cells. .

[0016]

In order to achieve such an object, the present invention relates to a non-multiplexed address memory device having dynamic memory cells,
One word line is equally divided into at least two so as to have the same number of memory cells to form divided word lines, and each divided word line is connected to each row decoder that receives the same decoding signal, And, only one of the row decoders is enabled by using the address signal of the most significant bit of the column address signal so that only one of the divided word lines is selected. Is one of the features.

[0017]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a block diagram of an embodiment of a word line selection circuit according to the present invention. Similar to FIG. 7, FIG. 1 shows the relationship between a memory cell array corresponding to one memory column block in the memory cell array shown in FIG. 5, a column decoder, and a row decoder. Therefore, the same number of memory cells (524, 288) as in FIG.
It can be seen that the number of bits and that of bit lines (256) are included.

As shown in FIG. 1, the memory column block is divided into a first memory column block 40 and a second memory column block 42 by dividing the 256 bit lines into two. The first memory column block 40 has 2048
The second memory column block 42 has 2,048 × 128 (= 262,144) dynamic memory cells in a matrix composed of two divided word lines LWL0 to LWL2047 and 128 bit lines BL0 to BL127. Is 2048 divided word lines UWL0 to UWL
2047 and 128 bit lines BL128 to BL255
2,048 × 128 (= 26
2, 144) dynamic memory cells.

First and second memory column blocks 40,
The divided word line located at 42 is manufactured in such a manner that one word line is divided into two so as to have the same number of memory cells. The divided word lines LWL0 to LWL2047 of the 2048 first memory column blocks 40 and the divided word lines UWL0 to UWL2047 of the 2048 second memory column blocks 42 are divided into eight groups, respectively. Column block 42
The eight divided word line groups located in the first memory column block 40 are connected to the row decoders URD1 to URD8 at a ratio of 1: 1, and the eight divided word line groups located in the first memory column block 40 are connected to the row decoders LRD1 to LR, respectively.
It is connected 1: 1 to D8. In the following description, the row decoders LRD1 to LRD8 will be referred to as a first decoder group, and the row decoders URD1 to URD8 will be referred to as a second row decoder group.

A row decoder selector 56 is provided for controlling the first row decoder group and the second row decoder group so as to enable them complementarily to each other. The row decoder selector 56 receives the address signal CA7 of the most significant bit MSB in the column address signal,
Refresh control signal φR that specifies refresh operation
Control signal CARFi generated by combining with FSH
Is supplied to the second row decoder group and its inversion signal CARFi is supplied to the first row decoder group so that the first row decoder group and the second row decoder group are mutually complementary enabled.

Then, the first row decoder group and the second row decoder group
The same row address signal is applied to the row decoder groups, so that the row decoders URD1 to URD8 are generated according to the block selection address signal in the row address signals.
Any one of them and the corresponding row decoder L
Any one of RD1 to LRD8 (that is,
URD1 and LRD1, URD2 and LRD2, ...) Are selected.

However, the control signal CARFi and the bar CAR
The level of Fi is simultaneously set to, for example, a logic “high”,
It is also possible to enable the row decoder group and the second row decoder group at the same time. At this time, the divided word lines of the first memory column block 40 and the divided word lines of the second memory column block 42 are mutually connected. Works like a connected one. Therefore, the word line shown in FIG. 1 is divided into the first memory column block 40 and the second memory column block 42 and operates as the respective divided word lines, while the word line shown in FIG. It is also possible to perform a refresh operation similar to the conventional one by operating similarly to the conventional memory column block shown.

FIG. 2 shows an embodiment of a concrete circuit of the row decoder as shown in FIG. The row decoder of this example has a power supply voltage V to a control node CN via a common channel.
Four N-channel transistors 60, 62, 6 whose channels are connected in series between the P-channel transmission gate 58 transmitting cc and the control node CN and the ground voltage Vss terminal.
4 and 66. Then, four N-channel transistors 7 each having its source terminal connected to the ground voltage Vss terminal and its gate terminal connected to the control node CN
Each of the drain terminals of 8, 80, 82, and 84 receives a signal φXi (i = 0 to 3) input from a predecoder described later to each of the drain terminals, and receives the control node CN.
Four N-channel transistors 68, 70, 72, 7 whose gate terminals receive the output of the inverter 76 connected to
The divided word lines UWL0 to UWL3 (LWL0 to LWL3) are connected in a ratio of 1: 1 to four connection nodes N0, N1, N2, and N3 whose source terminals of 4 are connected in a ratio of 1: 1.

Therefore, when the control node CN maintains the logic "low" state, the divided word lines UWL0 to UWL are
3 (LWL0 to LWL3), signals φX0 to φX3 are transmitted, and conversely, when the control node CN maintains the logic "high" state, the divided word lines UWL0 to UWL3 (LWL0
~ LWL3) are all connected to the ground voltage Vss end. Further, among the four N-channel transistors 60, 62, 64 and 66 which are connected in series between the control node CN and the ground voltage Vss terminal and perform the NAND operation, the gate terminals of the N-channel transistors 60, 62 and 64. Is the DRA2 obtained by decoding the row address signal
3, the DRA 45, and DRA 67 control the gate terminal of the N-channel transistor 66 to output a control signal CARFi (bar CAR) from the row decoder selector 56.
Controlled by Fi). Therefore, the control signal CAR
This row decoder is enabled only if Fi (bar CARFi) maintains a logic "high". Incidentally, FIG.
Since each row decoder shown in FIG. 2 controls 256 word lines, the actual structure of the row decoder is such that 64 row decoders shown in FIG. 2 are included, and each row decoder has a signal φXi (i = 0 to 0). 6 by sharing 3)
It can be seen that 4 × 4 (= 256) word lines are controlled.

FIG. 3 shows an embodiment of the row predecoder circuit for supplying the boosting level signal φXi shown in FIG. The row predecoder circuit of this example has an operation control section 9 for selecting a normal operation mode or a redundancy mode.
6, a decoding unit 98 that receives the row address signal and performs a NOR operation, and the decoding unit 98.
And an output unit 100 that outputs a signal φXi boosted to a predetermined level.

In the decoding unit 98, both ends of each channel are connected between the node N10 and the ground voltage Vss end, and row address signals RA0, RA0 are provided to respective gate terminals.
N receiving RA1, RA8, RA9, RA10 one by one
It has channel transistors 86, 88, 90, 92, 94. The five N-channel transistors perform a NOR operation, and row address signals RA8 and RA are accordingly generated.
9, block selection by decoding RA10,
That is, one row decoder of each of the first row decoder group and the second row decoder group of FIG. 1 is selected, and row address signals RA0 and R0 are selected.
By decoding A1, one of the four boosting signals φXi (i = 0 to 3) is enabled to logic “high”.

The row predecoder in the actual circuit is
Decoder precharge signal φDPX, redundant enable signal φRRE, address signals RA0, RA1, RA8, R
A9, RA10, and boosted master clock φ
It can be seen that eight circuits as shown in FIG. 3 having X as an input are included, and thus the row decoder shown in FIG. 1 is provided with a 1: 1 row predecoder.

FIG. 4 shows the row decoder selector 5 shown in FIG.
6 shows an example of a concrete circuit of No. 6. The row decoder selector 56 of this example has a first NOR gate 102 which receives the refresh control signal φRFSH as an input to the first input terminal and a most significant bit address signal CA7 of the column address signals as an input to the second input terminal, Refresh control signal φRF
The column address signal C is input with SH as the input of the first input terminal.
A second NOR gate 106 having A7 as an input to the second input terminal via the inverter 104, and a first NOR gate 10
The inverter 108 inverts the output of the second NOR gate 106 to output the signal CARFi, and the inverter 110 inverts the output of the second NOR gate 106 to output the signal CARFI.

When the refresh control signal φRFSH maintains the logic "low", the first NOR gate 102
The output of the second NOR gate 106 is controlled by the column address signal CA7. That is, when the column address signal CA7 is applied with a logic "high", the first N
The output of the OR gate 102 becomes a logic "low", and the second N
Since the output of the OR gate 106 is logic "high", the control signal CARFi output from the inverter 108 is logic "high", and the control signal CARFi output from the inverter 110 is logic "low". On the other hand, when the column address signal CA7 is applied at a logic "low", the output of the first NOR gate 102 is at a logic "high" and the second N
Since the output of the OR gate 106 is logic "low", the control signal CARFi is logic "low" and the control signal bar CAR
Fi becomes a logical "high".

When the refresh control signal φRFSH is applied at a logic "high", the most significant bit address signal CA7 in the column address signal has no effect and the first Nth
Since the outputs of the OR gate 102 and the second NOR gate 106 are logic "low", the control signal CARFi and the bar CARFI are logic "high".

As can be seen from the above description, the memory column block shown in FIG. 1 is divided into a total of 16 blocks for access operation, so that in normal access operation, one word is used. The number of bit lines that will be charged or discharged when a line is selected is 128, which is half of the 256 bit lines. Therefore, the charging / discharging current of the bit line is reduced to half compared with the conventional one.

In such an operation, one word line is divided into at least two divided word lines so as to have the same number of memory cells, and the same decoding signal is input to each divided word line. One of the two row decoders using the most significant bit address signal of the column address signals so that only one of the divided word lines is selected. It is achieved by enabling only one.

In the embodiment shown in FIG. 1, one column address signal and 16 row decoders are used for 16
The case where the division operation is performed by the individual blocks has been described as an example. However, it is also possible to add a column address signal and a row decoder to separate into more blocks.
That is, the memory cell array can be divided into 2 ^N blocks by subdividing into 2 ^N blocks using N column address signals and adding a row decoder for each block. By doing so, the memory cell operating current including the bit line charging / discharging current for operating the memory cell, the bit line sense amplifier driving current, the word line driving current, etc. is reduced to approximately 1/2 ^N. Therefore, the operating current of the memory cell can be significantly reduced.

[0034]

As described above, by using the memory cell selection circuit according to the present invention, the operating current can be greatly reduced, and the noise at the ground voltage end generated by the current consumption is thereby reduced. It also has an excellent effect of reducing the like. Therefore, the power consumption of the semiconductor memory device can be further reduced, which can greatly contribute to downsizing of the computer.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory cell selection circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific embodiment of the row decoder in FIG.

FIG. 3 is a circuit diagram showing a specific example of a row predecoder for the row decoder shown in FIG.

FIG. 4 is a circuit diagram showing a specific example of a row decoder selector in FIG.

FIG. 5 is a block diagram illustrating an example of a non-multiplexed address memory device.

FIG. 6 is a circuit diagram showing details of main parts of the memory cell array in FIG.

FIG. 7 is a block diagram showing an example of a memory cell selection circuit according to a conventional technique.

[Explanation of symbols]

 38 column decoder 40 first memory column block 42 second memory column block 56 row decoder selector LRD1-8 row decoder URD1-8 row decoder LWL0-2047 divided word line UWL0-2047 division word line BL0-255 bit line

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[Procedure amendment]

[Submission date] July 19, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a non-multiplexed address (non ^- mul).
The present invention relates to a memory cell selection circuit of a multiplexed address memory device.

[0002]

2. Description of the Related Art As a general known technique for selecting a specific memory cell in a semiconductor memory device having a memory cell array having a large number of memory cells, a row address signal and a column address are known. ) Methods of utilizing signals are known. That is, by decoding a row address signal to select any one of a large number of word lines, and decoding a column address signal to select any one of a large number of bit lines. , One memory cell can be selected.

Multiplexed address
In a lexed address memory device,
The row address signal and the column address signal are input with a time difference through the same input terminal. On the other hand, in a non-multiplexed address memory device, such as a PSRAM (Pseudo SRAM), the number of address signal input terminals is equal to the sum of the number of row and column address signals, and the row address signal and the column address signal are different from each other. It is designed to be input simultaneously through the input terminals.

The memory device shown in FIG. 5 is an example of a non-multiplexed address memory device .
4 is a block diagram schematically showing the configuration of a 4-megabit PSRAM.

The memory cell array 10 includes 2048 × 256 × 8 (= 4, 1) in a matrix of 2048 word lines and 256 × 8 (= 2048) bit lines.
94, 304) memory cells. The row address buffer 12 has TTL level row address signals A0 to A0 input through the row address signal input terminal.
A10 is input, and CMOS level row address signals RA0 to RA10 are output. The column address buffer 14 receives the TTL-level column address signals A11 to A18 input via the column address signal input terminals.
Input to the CMOS level column address signal CA
0 to CA7 are output. The row decoder 16 and the column decoder 18 receive row address signals RA0 to RA from the row address buffer 12 and the column address buffer 14, respectively.
10 and column address signals CA0 to CA7 are respectively received, and these are decoded to select a word line and a bit line. Sense amplifier / I / O gate 20
Includes a sense amplifier for reading data from the bit line and an I / O gate for transmitting the data read by the sense amplifier to eight data input / output lines.

Then, the data input buffer 22 transmits the data input through the data input / output terminals I / O1 to I / O8 to the data input / output lines. The data output buffer 24 stores the read data transmitted from the sense amplifier to the data input / output line in the data input / output terminal I / O.
1 to I / O8.

The refresh controller 26 controls the refresh operation, and the refresh timer 28 provides the refresh master clock. The refresh counter 30 is controlled by the refresh controller 26 to generate a refresh address signal and supply it to the row decoder 16. The control signal generating circuit 31 includes a control signal CE, a bar OE / bar RFSH, and a bar WE which are supplied from the outside.
Are combined to generate a control signal necessary for the operation of each part.

Therefore, the memory device shown in FIG.
8 memory column blocks with 56 bit lines
The memory column blocks share 2048 word lines with each other. The memory cell of the PSRAM is a dynamic cell composed of one transistor and one capacitor. FIG. 6 shows the relationship between the dynamic cell and the word line WL and the bit line BL. FIG. 6 specifically shows a part of the memory cell array 10 of FIG. Since the structure of the memory cell array as shown in the figure is a well-known technique, the description thereof will be omitted.

FIG. 7 is a block diagram showing an example of a conventional word line selection circuit. FIG. 7 is a block diagram showing the relationship between the memory cell array corresponding to one memory column block described above, and the column decoder and the row decoder.

2048 word lines WL0 to WL204
7 are divided into eight groups, and each word line group is connected to each row decoder 32, 34 , . That is, the memory column block shown in the figure is further divided into eight row blocks, and each row block has
Each row decoder 32, ..., 36 are provided. Only one of the row decoders 32, 34, ..., 36 is enabled by the block selection bit in the row address signal, and the enabled row decoder selects the word line selection bit in the row address signal. Are decoded to selectively drive one of the word lines.

On the other hand, 256 bit lines BL0 to BL2
The column decoder 38 is connected to the column decoder 38, and the column decoder 38 outputs 8-bit column address signals CA0 to C0.
A7 is decoded to select any one of 256 bit lines.

Therefore, the memory column block shown in FIG. 7 has a total of 2048 × 256 (= 524,288) dynamic memory cells.

In FIG. 7, when one word line is selected to selectively drive a specific memory cell, all 256 memory cells connected to the selected word line are assigned to the bit lines BL0 to BL255. Since the data of the connected memory cells are transmitted to the corresponding bit lines, the 256 bit lines BL0 to BL0 are connected.
BL255 is to consume unnecessary power becomes to perform all charging and discharging operations.

That is, when a predetermined word line is selected to access a specific memory cell, all the bit lines connected to the memory cells sharing this word line perform the charge / discharge operation. As a result, a large amount of bit line charge / discharge current will flow. As a result, the memory cell operating current including the bit line charging / discharging current, the sense amplifier driving current, and the word line driving current when operating the memory cell increases as the capacity of the memory device increases. is there. Therefore, in particular,
In a highly integrated memory device used in a portable computer using a battery power source, for example, a laptop computer or a notebook computer, it is an essential issue to reduce the operating current. Therefore, it is necessary to solve such a problem. Has been done.

[0015]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor memory device which requires a smaller operating current. Another object of the present invention is to provide a memory cell selection circuit capable of reducing the operating current required for selective driving of memory cells in a non-multiplexed address memory device having dynamic memory cells. .

[0016]

In order to achieve such an object, the present invention divides a word line, which has been conventionally used as one line, into at least two equal parts having the same number of memory cells. A row decoder is provided for each of the divided word lines, and one row decoder of these row decoders is operated only when a specific bit in the column address signal is logical "high", and the other row decoder is operated. the specific bits are to be operated only when the logic "low", and the output of one of the row decoder to the word line group to feed transfer, the specific bit
Connected to bit lines that are not selectively connected when logic "low"
Connected memory cells and the other row decoder
To the word line group that transmits the output of
Is connected to the bit line that is not selectively connected when is a logic "high"
Connected memory cells, and
Make sure that the same row address signal is input to the
Connected to a row decoder that is inactive via a word line
Memory cells are not connected to the bit lines
The main feature is that

In order to effectively utilize the present invention as described above
In the geometrical arrangement structure of the memory cell,
A bit line that is simultaneously disconnected according to the logical value of the constant bit
Another memory cell group is linked to another group.
Memory cells so that memory cells do not coexist.
It is preferable to arrange the loops centrally.

[0018]

With this structure, the bit lines can be simultaneously
At least half the number of memory cells connected to
Therefore, charging / reading associated with reading / writing is possible.
The discharge current can be reduced. Moreover, memory
If cells are arranged centrally in each group,
It is also possible to shorten the cable length and improve the operating speed.
To be

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a block diagram of an embodiment of a word line selection circuit according to the present invention. Similar to FIG. 7, FIG. 1 shows the relationship between a memory cell array corresponding to one memory column block in the memory cell array shown in FIG. 5, a column decoder, and a row decoder. Therefore, the same number of memory cells (524, 288) as in FIG.
It can be seen that the number of bits and the number of bit lines (256) are included.

As shown in FIG. 1, the memory column block is divided into a first memory column block 40 and a second memory column block 42 by dividing 256 bit lines into two. The first memory column block 40 has 2048
The second memory column block 42 has 2,048 × 128 (= 262,144) dynamic memory cells in a matrix composed of two divided word lines LWL0 to LWL2047 and 128 bit lines BL0 to BL127. Is 2048 divided word lines UWL0 to UWL
2047 and 128 bit lines BL128 to BL255
2,048 × 128 (= 26
2, 144) dynamic memory cells.

First and second memory column blocks 40,
The divided word line located at 42 is manufactured by a method of dividing one word line into two so as to have the same number of memory cells. The divided word lines LWL0 to LWL2047 of the 2048 first memory column blocks 40 and the divided word lines UWL0 to UWL2047 of the 2048 second memory column blocks 42 are divided into eight groups, respectively. Column block 42
The eight divided word line groups located in the first memory column block 40 are connected to the row decoders URD1 to URD8 at a ratio of 1: 1, and the eight divided word line groups located in the first memory column block 40 are connected to the row decoders LRD1 to LR, respectively.
It is connected 1: 1 to D8. In the following description, the row decoders LRD1 to LRD8 will be referred to as a first decoder group, and the row decoders URD1 to URD8 will be referred to as a second row decoder group.

A row decoder selector 56 is provided for controlling the first row decoder group and the second row decoder group so as to operate in a complementary manner. The row decoder selector 56 includes an address signal CA7 of the most significant bit MSB in the column address signal and a refresh control signal φRFSH for designating a refresh operation.
The control signal CARFi generated by combining
The inverted signal bar CARFi is supplied to the first row decoder group while being supplied to the row decoder group,
The first row decoder group and the second row decoder group operate so as to complement each other.

Then, the first row decoder group and the second row decoder group
The same row address signal is applied to the row decoder groups, so that the row decoders URD1 to URD8 are generated according to the block selection address signal in the row address signals.
Any one of them and the corresponding row decoder L
Any one of RD1 to LRD8 (that is,
URD1 and LRD1, URD2 and LRD2, ...) Are selected.

However, the control signal CARFi and the bar CAR
The level of Fi is simultaneously set to, for example, a logic “high”,
It is also possible to operate the row decoder group and the second row decoder group at the same time. At this time,
The divided word lines of the first memory column block 40 and the divided word lines of the second memory column block 42 work in the same manner as those connected to each other. Therefore, the word line shown in FIG. 1 is divided into two for the first memory column block 40 and the second memory column block 42 and operates as the respective divided word lines, while the word line shown in FIG. 7 is operated during the refresh operation of the memory cell. It is also possible to perform a refresh operation similar to the conventional one by operating similarly to the conventional memory column block shown.

FIG. 2 shows an embodiment of a concrete circuit of the row decoder as shown in FIG. The row decoder of this example has a power supply voltage V to a control node CN via a common channel.
Four N-channel transistors 60, 62, 6 whose channels are connected in series between the P-channel transmission gate 58 transmitting cc and the control node CN and the ground voltage Vss terminal.
4 and 66. Then, four N-channel transistors 7 each having its source terminal connected to the ground voltage Vss terminal and its gate terminal connected to the control node CN
Each of the drain terminals of 8, 80, 82, and 84 receives a signal φXi (i = 0 to 3) input from a predecoder described later to each of the drain terminals, and receives the control node CN.
Four N-channel transistors 68, 70, 72, 7 whose gate terminals receive the output of the inverter 76 connected to
The divided word lines UWL0 to UWL3 (LWL0 to LWL3) are connected in a ratio of 1: 1 to four connection nodes N0, N1, N2, and N3 whose source terminals of 4 are connected in a ratio of 1: 1.

Therefore, when the control node CN maintains the logic "low" state, the divided word lines UWL0 to UWL are divided.
3 (LWL0 to LWL3), signals φX0 to φX3 are transmitted, and conversely, when the control node CN maintains the logic "high" state, the divided word lines UWL0 to UWL3 (LWL0
~ LWL3) are all connected to the ground voltage Vss end. Further, among the four N-channel transistors 60, 62, 64 and 66 which are connected in series between the control node CN and the ground voltage Vss terminal and perform the NAND operation, the gate terminals of the N-channel transistors 60, 62 and 64. Is the DRA2 obtained by decoding the row address signal
3, the DRA 45, and DRA 67 control the gate terminal of the N-channel transistor 66 to output a control signal CARFi (bar CAR) from the row decoder selector 56.
Controlled by Fi). Therefore, the control signal CAR
This row decoder operates only if Fi (bar CARFi) maintains a logic "high". Since each row decoder shown in FIG. 1 controls 256 word lines, the practical structure of the row decoder is such that 64 row decoders shown in FIG. 2 are included, and each row decoder has a signal φXi ( 64 × 4 by sharing i = 0-3)
It can be seen that (= 256) word lines are controlled.

FIG. 3 shows the boosted signal φ shown in FIG.
The embodiment of the circuit of the row predecoder for supplying Xi is 4
One of the pieces is representatively shown. The row predecoder circuit of this example is controlled by an operation control section 96 for selecting a normal operation mode or a redundancy mode, a decoding section 98 for performing a NOR operation with a row address signal as an input, and this decoding section 98. To a predetermined level
The output unit 100 outputs the boosted signal φXi.

In the decoding unit 98, both ends of each channel are connected between the node N10 and the ground voltage Vss end, and the row address signals RA0, RA0,
N receiving RA1, RA8, RA9, RA10 one by one
It has channel transistors 86, 88, 90, 92, 94. The five N-channel transistors perform a NOR operation, and row address signals RA8 and RA are accordingly generated.
9, block selection by decoding RA10,
That is, one row decoder of each of the first row decoder group and the second row decoder group of FIG. 1 is selected, and row address signals RA0 and R0 are selected.
Four output signals φXi (i = 0 to 0 depending on the application method of A1)
One of 3) transitions to logic "high". That is,
As shown in FIG. 3, the row address signals RA0 and RA1 are
When applying the reverse RA0 and RA1,
When applying RA0 and RA1 inversion, RA0 inversion and
The signal φX is applied depending on each case of applying the inversion RA1.
0, φX1, φX2, and φX3 are output.

The row predecoder in the actual circuit is
Decoder precharge signal φDPX, redundant enable signal
No. φRRE, address signals RA0, RA1, RA8, R
A9, RA10, and boosted master clock φ
Contains eight circuits as shown in FIG.
Therefore, the row decoder shown in FIG.
A row predecoder like this example is provided correspondingly .

FIG. 4 shows the row decoder selector 5 shown in FIG.
6 shows an example of a concrete circuit of No. 6. The row decoder selector 56 of this example has a first NOR gate 102 which receives a refresh control signal φRFSH as an input to a first input terminal and a most significant bit address signal CA7 in a column address signal as an input to a second input terminal, Refresh control signal φRF
The column address signal C is input with SH as the input of the first input terminal.
A second NOR gate 106 having A7 as an input to the second input terminal via the inverter 104, and a first NOR gate 10
An inverter 108 for outputting as to invert the second output signal CARFi, an inverter 110 for outputting output is inverted first 2NOR gate 106 as the signal bar CARFi.

When the refresh control signal φRFSH maintains the logic "low", the first NOR gate 102
The output of the second NOR gate 106 is controlled by the column address signal CA7. That is, when the column address signal CA7 is applied with a logic "high", the first N
The output of the OR gate 102 becomes a logic "low", and the second N
Since the output of the 0R gate 106 is a logic "high", the control signal CARFi output from the inverter 108 is a logic "high", and the control signal bar CARFi output from the inverter 110 is a logic "low". On the other hand, when the column address signal CA7 is applied at a logic "low", the output of the first NOR gate 102 is at a logic "high" and the second N
Since the output of the OR gate 106 is logic "low", the control signal CARFi is logic "low" and the control signal bar CAR
Fi becomes a logical "high".

When the refresh control signal φRFSH is applied with a logic "high", the most significant bit address signal CA7 in the column address signal has no effect and the first Nth
Since the outputs of the OR gate 102 and the second NOR gate 106 are logic "low", the control signal CARFi and the bar CARFI are logic "high".

As can be seen from the above description, the memory column block shown in FIG. 1 is further divided into 16 blocks to perform the access operation, so that in the normal access operation, one word is used. The number of bit lines that will be charged or discharged when a line is selected is 128, which is half of the 256 bit lines. Therefore, the charging / discharging current of the bit line is reduced to half compared with the conventional one.

In such an operation, one word line is divided into at least two divided word lines so as to have the same number of memory cells, and the same decoding signal is input to each divided word line. One of the two row decoders using the most significant bit address signal of the column address signals so that only one of the divided word lines is selected. It is achieved by enabling only one.

In the embodiment shown in FIG. 1, one column address signal and 16 row decoders are used for 16
The case where the division operation is performed by the individual blocks has been described as an example. However, it is also possible to add a column address signal and a row decoder to separate into more blocks.
That is, the memory cell array can be divided into 2 ^N blocks by subdividing into 2 ^N blocks by using N column address signals and adding a row decoder for each block. By doing so, the memory cell operating current including the bit line charging / discharging current for operating the memory cell, the bit line sense amplifier driving current, the word line driving current, etc. is reduced to approximately 1/2 ^N. Therefore, the operating current of the memory cell can be significantly reduced.

[0036]

As described above, by using the memory cell selection circuit according to the present invention, the operating current can be greatly reduced, and the noise at the ground voltage end generated by the current consumption is thereby reduced. It also has an excellent effect of reducing the like. Therefore, the power consumption of the semiconductor memory device can be further reduced, which can greatly contribute to downsizing of the computer.

Claims (6)

[Claims] 1. A row address signal and a column address signal simultaneously input through respective input terminals are decoded to drive a word line and a bit line to selectively drive a specific dynamic memory cell. In the semiconductor memory device, at least two row decoders for decoding the same row address signal to enable any one of the word lines connected to each row decoder and at least one of the column address signals. A semiconductor memory device, comprising: a row decoder selector for controlling only one of the row decoders to operate corresponding to one logic level. 2. The row decoder selector is adapted to enable any one of the row decoders in response to the logical level of the address signal of the most significant bit in the column address signal. 1. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 2, wherein the row decoder selector is adapted to enable all row decoders in a refresh mode of the memory cells. 4. A non-multiplexed address memory device having dynamic memory cells, wherein at least two divided memory cells are formed, each of which divides a dynamic memory cell arranged in a row direction into at least two equal parts and drives them. At least two word line groups and one divided word line group corresponding to the divided word line groups in a one-to-one manner and decoding the same row address signal to selectively drive any one divided word line in the corresponding divided word line group. Row decoder and a row decoder selector for enabling only one of the row decoders in response to at least one logic level of the column address signal. Non-multiplexed address memory device. 5. The row decoder selector is adapted to enable any one of the row decoders in response to the logical level of the address signal of the most significant bit in the column address signal. 4. A non-multiplexed address memory device according to 4. 6. The non-multiplexed address memory device of claim 5, wherein the row decoder selector is adapted to enable all row decoders in a memory cell refresh mode.