JP2001060400A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which increment of a chip area caused by the increment of program elements for programming a defective address can be suppressed. SOLUTION: This device is provided with plural bit lines performing delivery and receipt of information with a memory cell, plural word lines WL selecting the memory cell taking out the information to the bit line, and spare word lines SWL relieving the word line connected to the memory cell which cannot take out the information normally. Further, the device is provided with a spare discriminating circuit 5 holding the relieving information for relieving the memory cell which cannot take out the information normally, and shared respectively in replacement of the word line WL by the spare word line SWL based on this relieving information and change of a refresh period of the word line WL based on this relieving information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to suppressing an increase in redundancy circuits for repairing defects.

[0002]

2. Description of the Related Art In recent years, dynamic semiconductor memory devices (DRAMs) having a one-transistor / one-capacitor type memory cell structure have been highly integrated due to improvements in memory cells, fine processing technology and circuit design technology. In addition, the miniaturization has been remarkably progressed, and this trend is expected to continue in the future.

[0003] With the increase in DRAM integration, that is, the increase in storage capacity, the number of memory cells integrated on one chip has increased significantly. For this reason, the probability of occurrence of a defective cell in the memory cell array is increasing, and a redundancy technique for replacing a defective cell with a spare cell is becoming increasingly important.

In a general redundancy technique, when a defective cell occurs, it is replaced with a spare cell. For example, when a defective memory cell connected to a certain word line is found, the word line including the defective cell is replaced with a spare word line connected to a spare cell. In general, with the progress of memory integration and miniaturization,
The number of spare word lines or spare column selection lines for replacing defective cells and the number of fuses for storing address information of defective cells and the like also tend to increase.

In order to replace a defective cell with a spare cell, it is necessary to determine whether address information input from the outside matches information programmed in a fuse. The number of spare determination circuits for this determination, or the scale thereof, also tends to increase as the number of memory cells and fuses increases.

[0006] Such a redundancy technique has been used mainly when a word line or a memory cell has a defect and reading and writing cannot be performed normally, but recently, it is also used to extend a refresh cycle. In order to reduce the power consumption of the DRAM during standby, the longer the refresh cycle, the better. The refresh cycle refers to a cycle in which data is periodically rewritten to the memory cells in order to compensate for the attenuation of the data in the memory cells. For example, if all the word lines can be refreshed in 64 msec as compared with the case where all the word lines are refreshed in 32 msec, the power consumption in the standby state is reduced to half.

However, in this case, the refresh cycle is 32 ms.
Memory cells with poor pause characteristics that work well with ec, but fail at 64 msec, must be rescued in some way. Attempts to replace these defects with spare word lines as described above have a very large effect on the chip area.

In order to solve this problem, ordinary memory cells having good pause characteristics are refreshed in a long cycle,
A method has been proposed in which power consumption is suppressed by refreshing only memory cells having poor pause characteristics in a shorter cycle.

(Reference: Y.Idei, et.al., "Dual-Peri
od Self-Refresh Scheme for Low-Power DRAM's with O
n-Chip PROM Mode Resister ", IEEE J. Solid-State Cir
cuits, vol33, No.2, Feb. 1988.: S.Takase, et.a
l., "A 1.6GB / s DRAM with Flexible Mapping Redundan
cy Technique and Additional Refresh Scheme ", IEEEI
(SSCC digest of technical papers, Feb. 1999.)

[0010]

However, even in these methods, a word line connected to a memory cell having poor pause characteristics must be specified by some method.
For example, in the latter example, programming is performed by preparing about 2,000 fuses by grouping about 8000 word lines in units of four, but this has a large effect on the chip area.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor integrated circuit device capable of suppressing an increase in chip area due to an increase in program elements for programming a defective address. It is in.

[0012]

In order to achieve the above object, a semiconductor integrated circuit device according to a first aspect of the present invention comprises a plurality of bit lines for exchanging information with a memory cell, and A plurality of word lines for selecting a memory cell from which information is to be taken out, a spare word line for repairing a word line connected to a memory cell from which information cannot be taken out normally, and the above-mentioned information cannot be taken out normally It has a function of holding rescue information for relieving a memory cell, replacing the word line with the spare word line based on the rescue information, and changing a refresh cycle of the word line based on the rescue information. And a spare determination circuit.

In order to achieve the above object, a semiconductor integrated circuit device according to a second aspect of the present invention includes a plurality of bit lines for exchanging information with a memory cell, and a column selection for selecting the bit line. A plurality of word lines for selecting a memory cell from which information is to be taken out to the bit line, a spare word line to rescue a word line connected to a memory cell from which information cannot be taken out normally, and A spare bit line for relieving a bit line connected to a memory cell from which information cannot be taken out; a spare column selection line for selecting the spare bit line; and a memory cell from which information cannot be taken out properly. Holding relief information for relief, replacing the word line with the spare word line based on the relief information, and It is characterized by comprising a spare determination circuit having a function of replacement of the spare column selection line of the column select lines based on distribution.

In order to achieve the above object, a semiconductor integrated circuit device according to a third aspect of the present invention includes a plurality of bit lines for exchanging information with a memory cell, and a column selection for selecting the bit line. A plurality of word lines for selecting a memory cell from which information is to be taken out to the bit line, a spare word line to rescue a word line connected to a memory cell from which information cannot be taken out normally, and A spare bit line for relieving a bit line connected to a memory cell from which information cannot be taken out; a spare column selection line for selecting the spare bit line; and a memory cell from which information cannot be taken out properly. Holding the relief information for relief, replacing the word line with the spare word line based on the relief information, Replacement of the spare column selection line of the column selection lines had, and is characterized by comprising a spare determination circuit having a function of changing the refresh period of the word lines based on the repair information.

In the semiconductor integrated circuit device according to the first to third aspects, replacement with a spare word line and a spare determination circuit having a function of changing a refresh cycle, or replacement with a spare word line, and A spare determination circuit having a function of replacing with a spare column selection line, or a spare determination circuit having a function of replacing with a spare word line, replacing with a spare column selection line, and changing a refresh cycle is provided.

By providing such a spare determination circuit, it is possible to make one spare determination circuit correspond to different relief modes, and to increase the number of spare determination circuits with an increase in storage capacity. It is possible to suppress the increase in the chip area.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

[First Embodiment] FIG. 1 is a block diagram of a DRAM according to a first embodiment of the present invention.

As shown in FIG. 1, a DRAM chip includes:
A memory cell array in which a plurality of dynamic memory cells (not shown) are arranged in a matrix is provided. In this example, the memory cell array is divided into four memory cell blocks 1.

A plurality of word lines WL are arranged in the memory cell block 1 and are connected to gates of a plurality of dynamic memory cells arranged in the row direction. The word line WL is selected by a row decoder (Row dec.) 2. Further, a plurality of spare word lines SWL are arranged in the memory cell block 1 and are connected to a plurality of dynamic memory cells (spare cells) arranged in the row direction. The spare word line SWL is selected by a spare row decoder (spare Row dec.) 3. In this example, two sets of spare word lines SWL are arranged for one memory cell block 1. Therefore,
The memory cell array shown in FIG. 1 has eight sets of spare word lines SWL in total.

Each of the row decoder 2 and the spare row decoder 3 is controlled by a row control circuit 4.
The row control circuit 4 outputs an address signal, a row timing signal, a control signal and the like to the row decoder 2 and the spare row decoder 3.

The spare determination circuit 5 determines whether to replace the word line WL with the spare word line SWL. 1
One spare determination circuit 5 is a unit block of a relief circuit for performing one-time defect replacement, and a plurality of sets are provided. In this example, four sets are provided. The four sets of spare determination circuits 5 select an arbitrary spare word line SWL from the eight sets of spare word lines SWL in the memory cell array. According to this method, two sets of spare word lines SWL are required for each memory cell block when the occurrence of defects is considered statistically, but only four sets of spare word lines SWL need to be replaced in the entire memory cell array. This is effective when is predicted. That is, the relationship between the spare determination circuit 5 and the spare word line SWL is one-to-one.
Therefore, an unnecessary increase in area can be suppressed.

When at least one of the four sets of spare determination circuits 5 determines that "the word line WL is replaced with the spare word line SWL", the signal line precharged by the precharge circuit 6, that is, the signal bRDHIT becomes " LOW ”
Level. When the signal bRDHIT goes to “LOW” level,
The row control circuit 4 activates the spare row decoder 3 instead of the row decoder 2. As a result, the specific word line WL is replaced with the spare word line SWL.

The spare determination circuit 5 included in the DRAM according to the first embodiment further determines whether to change the word line refresh cycle. If at least one of the four sets of spare determination circuits 5 determines that the word line refresh cycle is to be changed, the signal line precharged by the precharge circuit 6, ie, the signal bSRFON
Becomes “LOW” level. When the signal bSRFON becomes “LOW” level, the row control circuit 4 changes the refresh cycle of the specific word line WL from, for example, 64 msec to 32 msec.

Next, the D according to the first embodiment of the present invention will be described.
The spare determination circuit 5 provided in the RAM will be described in more detail.

FIG. 2 is a circuit diagram showing the whole of the spare determination circuit 5 according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing one of the spare determination circuits 5 according to the first embodiment of the present invention. FIG.

As shown in FIGS. 2 and 3, the spare determination circuit 5 includes a determination circuit 11, a latch circuit 12 for latching an output signal from the determination circuit 11, and a bRDHIT output circuit 1, respectively.
3. The bSRFON output circuit 14 and the like.

The spare determination circuit 5 is provided with a fuse circuit group as a program section. The fuse circuit group is programmed with enable information as to whether or not to use the spare determination circuit 5, defective address information, and switching information as to whether to replace the spare word line or change the refresh cycle.

4A to 4C are circuit diagrams of a fuse circuit group. FIG. 4A shows a fuse circuit for defective address information, FIG. 4B shows a fuse circuit for enable information, and FIG. C) indicates a switching information fuse circuit.

First, as shown in FIG. 4A, the fuse circuit 21 for defective address information includes a fuse (Fuse). This fuse is programmed with defective address information. The defective address information output from the fuse circuit 21 is input to the latch circuit 22 and is latched here. The output of the latch circuit 22 is
3 is input. The fuse information comparison circuit 23 compares the defective address information latched by the latch circuit 22 with the input address information, and selects one of the address signal ADD and its complementary signal (inverted signal) bADD,
Output as output signal MIS.

As shown in FIG. 4B, the enable information fuse circuit 31 includes a fuse (Fuse). The fuse is programmed with enable information. The latch circuit 32 latches the enable information output from the fuse circuit 31. The latch circuit 32
An output signal bRDENB having a level opposite to that of the output FLAT of the fuse circuit 31 is output.

Further, as shown in FIG. 4C, the switching information fuse circuit 41 includes a fuse (Fuse). Switching information is programmed in this fuse. The latch circuit 42 latches the switching information output from the fuse circuit 41. The output of the latch circuit 42 is
Connected to the input. Inverter 43 outputs an output signal SRF having the same level as output FLAT of latch circuit 42.

Next, the operation of the fuse circuit group will be described.

FIG. 5A is an operation waveform diagram showing the operation of the fuse circuit group.

The signal bFUP and the signal FDWN shown in FIG.
This signal is activated when the power is turned on. First, when the power is turned on, the power supply potential Vcc rises toward the “HIGH” level. Accordingly, the potential of the signal bFUP increases (time tON).

After a certain period of time has elapsed after the power supply potential Vcc has reached the "HIGH" level, the potential of the signal bFUP transitions to the "LOW" level. As a result, the PMOSs P1 to P3 provided in the fuse circuits 21, 31, and 41 are turned on (time t1). When the PMOSs P1 to P3 are turned on, the fuse circuits 21, 31, and 41 are turned on.
Each output node FLAT becomes "HIGH" level, and the latch circuits 22, 32 and 42 respectively latch "HIGH" level initial information. The signal bFUP is output from the latch circuit 2
Each of 2, 32, and 42 transitions to the "HIGH" level after a sufficient time has elapsed to latch the "HIGH" level of the output level (FLAT).

After the signal bFUP transits to the “HIGH” level,
The signal FDWN changes to “HIGH” level. This turns on the NMOSs N1 to N3 provided in the fuse circuits 21, 31, and 41, respectively (time t2). NMO
When SN1 to N3 are turned on, the output nodes (FLAT) of the fuse circuits 21, 31, and 41, respectively.
Transitions to the "LOW" level when the fuse is "blown", and maintains the "HIGH" level when the fuse is not blown. As a result, the latch circuits 22, 32 and 42 each latch information corresponding to the state of the fuse. Signal FDWN
Transitions to the "LOW" level after a lapse of time sufficient for each of the latch circuits 22, 32 and 42 to latch the "LOW" level of the output level (FLAT).

As described above, the latch circuits 22, 32 and 42 latch information on the state of the fuse, that is, whether the fuse is "cut" or "not cut".

Next, an example of latching according to the state of the fuse will be described focusing on the latch circuit 22.

First, it is assumed that when the output signal MIS of the fuse information comparison circuit 23 goes to the "LOW" level, "determining that the defective address information and the input address information match" is performed. In this case, when the address signal ADD = HIGH, the defective address information and the input address information are matched, so that the fuse may be blown. As a result, the latch circuit 22
, The transfer gate 24 for transferring the address signal ADD is turned off, and the transfer gate 25 for transferring the address signal bADD.
Can be turned on. Address signal ADD = HIGH
, The address signal bADD = LOW, so the output signal
MIS goes to the "LOW" level. FIG. 5B shows the relationship between the state of the fuse and the output signal MIS.

The signals MIS0 to MIS3 shown in FIGS. 2 and 3 are output signals from the fuse information comparison circuit 23 shown in FIG. Each of the signals MIS0 to MIS3 is “LO” when the input address signal matches the defective address information.
It becomes the "W" level, and if not matched, it becomes the "HIGH" level.

The signal bRDENB shown in FIG. 2 and FIG.
This is an output signal from the latch circuit 32 shown in FIG. The signal bRDENB is “LO” when the spare determination circuit 5 is used.
It goes to "W" level and goes to "HIGH" level when not used.

The signal SRF shown in FIG. 2 and FIG.
Is an output signal of the inverter 43 shown in FIG. When replacing a word line with a spare word line, it goes to “LOW” level,
It changes to “HIGH” level when the refresh cycle is changed.

The signal RACT shown in FIGS. 2 and 3 is a signal indicating a period during which the row-related circuit is activated. In this example, for example, the signal RACT becomes “HIGH” level during a period in which the spare determination circuit 5 is activated.

Next, the operation of spare determination circuit 5 will be described.

FIG. 6A is an operation waveform diagram when the defective address information does not match the input address information.
FIG. 6B is an operation waveform diagram when the defective address information matches the input address information.

[Case where Input Address Information Does Not Match Defective Address Information] First, as shown in FIG. 6A, the signal RACT goes to “HIGH” level, and the precharge of the output of the determination circuit 11 is released. You.

If the input address information and the defective address information do not match, four sets of fuse information comparison circuits 2
At least one of the outputs MIS0 to MIS3 is "HIGH"
Level. In this example, the output MIS1 is at the “HIGH” level. As a result, the output of the determination circuit 11 changes from the precharge level (“HIGH” level) to “LOW” level, and the output node CMP0 of the latch circuit 12 changes from “LOW” level to “HIGH” level.

The node CMP1, which defines the timing for the redundancy judgment, goes from the "HIGH" level to the "LOW" level after a sufficient time required for the potential of the node CMP0 to change.

The bRDHIT output circuit 13 includes a NOR gate circuit 15. This NOR gate circuit 15 includes the switching information SR
F is low level and node CMP1 is pulsed low
It is enabled during the period when the signal is at the “W” level, and during this period, its output is changed according to the level of the node CMP0.In this example, since the node CMP0 is at the “HIGH” level, the output of the NOR gate circuit 15 As a result, the potential of the signal line bRDHIT, which has been precharged to the power supply potential Vcc by the precharge circuit 6, is maintained at the precharge potential.

When the spare determination circuit 5 is not used, the signal bRDENB is at the "HIGH" level, and the potential of the signal line bRDHIT is maintained at the precharge potential by the same operation as that described above. .

[When the input address information matches the defective address information] First, as shown in FIG.
RACT becomes “HIGH” level, and the precharge of the output of the decision circuit 11 is released.

If the input address information matches the defective address information, four sets of fuse information comparison circuits 23
Output MIS0 to MIS3 are all at "LOW" level. As a result, the output of the determination circuit 11 maintains the “HIGH” level, and the output node CMP0 of the latch circuit 12 maintains the “LOW” level.

After that, similarly, the node CMP1
After a sufficient time required for the potential of P0 to change, the level changes from the “HIGH” level to the “LOW” level. NOR
The gate circuit 15 is enabled during a period when the switching information SRF is at the “LOW” level and the node CMP1 is at the “LOW” level in the form of a pulse. During this period, the output is changed according to the level of the node CMP0. In this example, since the node CMP0 is at the “LOW” level, the output of the NOR circuit 15 is
While the node CMP1 is at the “LOW” level, it goes to the “HIGH” level, turning on the NMOS N4 temporarily. As a result, the potential of the signal line bRDHIT changes from the precharge level to the “LOW” level. The NMOS N4 provided in each of the four sets of spare determination circuits 5 is wired-OR connected to one signal line bRDHIT. For this reason,
If at least one of the NMOSs N4 is temporarily turned on,
The potential of the signal line bRDHIT becomes “LOW” level. As a result, the normal cell is replaced with a spare cell, in this example, the normal word line WL is replaced with the spare word line SWL.

The spare determination circuit 5 included in the DRAM according to the first embodiment includes a bSRFON output circuit 14.

The bSRFON output circuit 14 includes a NOR gate circuit 16. This NOR gate circuit 16 has the switching information SR opposite to the NOR gate circuit 15 of the bRDHIT output circuit 13.
When F is at the “HIGH” level and during the period when the node CMP1 is in the “LOW” level in a pulsed manner, the output is changed according to the level of the node CMP0 during this period.

As a result, when the input address information matches the defective address information, that is, when the node CMP0 is “LOW”
Level, and while the node CMP1 is at the “LOW” level, the NMOS N5 is temporarily turned on. As a result, the potential of the signal line bSRFON changes from the precharge level to the “LOW” level. The NMOS N5 provided in each of the four sets of spare determination circuits 5 is wired-OR connected to one signal line bSRFON. For this reason,
If at least one of the NMOSs N5 is temporarily turned on,
The signal line bSRFON becomes “LOW” level. Signal line bSRFON
Is a wiring for transmitting a signal indicating whether to perform self-refresh.

The row control circuit 4 applies the row address strobe signal RAS during the self-refresh period and during the period of refreshing a cell having a weak pause characteristic.
A signal for controlling the refresh operation is generated using the address signal and the address signal, and is output to the row decoder 2 and the like. Signal line bS
The RFON potential is used to disable or enable a signal that controls the refresh operation. When the potential of the signal line bSRFON is at the “HIGH” level, a signal for controlling the refresh operation is enabled, and the self refresh is performed. When the potential of the signal line bSRFON is at the “LOW” level, the signal for controlling the refresh operation is disabled, and the self-refresh is stopped.

In the spare determination circuit 5, the signal line
If it is difficult to determine whether to perform self-refresh or stop after determining the state of the potential of bSRFON, the next address may be input to the spare determination circuit 5.

In the case of self-refresh, the address is sequentially incremented by using, for example, an address counter.
Alternatively, the address to be refreshed is determined by decrementing. Utilizing this, when an address signal is fetched by the signal RAS, +1 is added to the fetched address, and the + 1-added address is sent to the spare determination circuit 5. Then, the determination information may be held until the next cycle.

According to the first embodiment, one spare determination circuit 5 is shared by a plurality of repair modes. For example, in the first embodiment, the word line WL is replaced with the spare word line SWL. This can be shared both when the refresh cycle of the word line WL is changed.

By providing such a spare determination circuit 5, it is not necessary to provide an extra spare determination circuit 5.
Therefore, the manufacturing yield can be improved by increasing the number of spare sets while suppressing an increase in the chip area.

[Second Embodiment] The second embodiment is the first embodiment.
The difference from the embodiment is that the circuit that generates the signal SRF for specifying whether to use the refresh cycle is eliminated, and instead, the signal bRDENB indicating whether or not the fuse set is used is used, and the bRDHIT output is used. That is, the circuit 13 and the bSRFON output circuit 14 are controlled.

FIG. 7 is a circuit diagram of a spare determination circuit 5-2 according to the second embodiment of the present invention.

As in the case of the first embodiment, the fuse circuit 31 is programmed so that the signal bRDENB becomes "LOW" when the word line is replaced with a spare word line, as in the first embodiment. In this way bRDH
The IT output circuit 13 is enabled, and the bSRFON output circuit 14 is disabled.

When the refresh cycle of the word line is changed, the fuse circuit 31 is programmed so that the signal bRDENB becomes "HIGH" level. In this way bRDH
Disable the IT output circuit 13 and set the bSRFON output circuit 14
Enable.

According to the second embodiment, the signal
The signal S of the circuit for generating the SRF and the judgment circuit 11
An NMOS or the like that receives RF at its gate can be omitted. Therefore, according to the spare determination circuit 5-2 according to the second embodiment, the number of program elements such as fuses and the number of transistors can be reduced as compared with the first embodiment. Therefore, an increase in the chip area can be further suppressed as compared with the first embodiment.

In the second embodiment, the signal bRDENB is at "HIGH" level, that is, the refresh cycle is changed in the unused spare determination circuit 5, and the address 0 (in a state where all the fuses are not blown). Address to hit)
In this case, an extra refresh occurs.
As an effect of this, current consumption may increase slightly.
However, the slight increase in the current consumption can be suppressed to almost the error range.

[Third Embodiment] The third embodiment relates to suppression of an increase in the load capacitance of the signal line bRDHIT and the signal line bSRFON with an increase in the number of spare determination circuits 5.

In order to improve the manufacturing yield, it is necessary to increase the number of replacements with spares. As a result, the number of spare determination circuits 5 increases. However, when the number of spare determination circuits 5 increases, the number of NMOS N4 wired OR connected to the signal line bRDHIT and the signal line bSRFON
, The number of NMOSs N5 that are wired OR connected to each other also increases. Therefore, the load capacitance of the signal line bRDHIT and the load capacitance of the signal line bSRFON increase.

The increase in the load capacitance of the signal lines bRDHIT and bSRFON causes a noticeable signal delay during the signal lines bRDHIT and bSRFON.
That is, the increase in the load capacitance of the signal lines bRDHIT and bSRFON is D
This affects the operation speed of the RAM, and hinders speeding up the operation.

In the third embodiment, such a signal line bRDH
It aims to suppress the increase in the load capacity of IT and bSRFON.

FIG. 8 is a circuit diagram of a spare determination circuit according to the third embodiment of the present invention.

As shown in FIG. 8, the third embodiment is the first embodiment.
The difference from the third embodiment is that the NAND circuit 51, the NA
That is, the ND circuit 52 is provided. The NAND circuit 51
For example, a two-input type, each of which has a plurality of output circuits 13
-3 output is input. Similarly, the NAND circuit 52 includes:
For example, a two-input type, each of which has a plurality of output circuits 14
-3 output is input. The output of the NAND circuit 51 is N
The input to the gate of the MOS N4, and the output of the NAND circuit 52 are input to the gate of the NMOS N5.

According to the third embodiment, the plurality of spare determination circuits 5-3 use the NMOS N4 and the NMO
SN5 can be shared. Thereby, one signal line bRDH
NMOS N4 wired OR connected to IT and NMO wired OR connected to one signal line bSRFON
The number of SN5 can be reduced, and these signal lines bRDHI
The increase in the load capacity of T and bSRFON can be suppressed. The third embodiment is advantageous in increasing the operation speed because the increase in the load capacitance of the signal lines bRDHIT and bSRFON can be suppressed.

When the load capacitance of the signal lines bRDHIT and bSRFON increases, the current driving capability of each of the NMOSs N4 and N5 must be increased. For this, NM
It is necessary to increase the dimensions of the OSNs 4 and N5, particularly the gate width, which is disadvantageous for high integration.

Even in such a situation, in the third embodiment, an increase in the load capacitance of the signal lines bRDHIT and bSRFON can be suppressed, so that the dimensions of the NMOSs N4 and N5, particularly the gate width, can be reduced. Is possible,
This is advantageous for high integration.

Next, a modification of the third embodiment will be described.

In the third embodiment, one spare determination circuit 5 is replaced with a spare word line SWL in order to reduce the number of spare determination circuits 5 while suppressing a decrease in the relief efficiency. This is shared between the case and the case where the refresh cycle of the word line WL is changed.

However, from the viewpoint of suppressing an increase in the load capacitance of the signal lines bRDHIT and bSRFON, the following modification may be used.

FIG. 9 is a circuit diagram of a spare determination circuit according to a modification of the third embodiment of the present invention.

As shown in FIG. 9, the third embodiment may be applied to a DRAM having a spare determination circuit 5-3 'corresponding only to replacing the word line WL with a spare word line. Alternatively, although not specifically shown, the present invention may be applied to a DRAM having a spare determination circuit corresponding only to a case where the refresh cycle of the word line WL is changed.

According to such a modification of the third embodiment, the load capacity of the signal line bRDHIT is increased or the signal line bS
Since an increase in the load capacitance of RFON can be suppressed, the effect that it is advantageous for high-speed operation and high integration can be obtained.

In the third embodiment and its modification, the NAND circuits 51 and 52 are of a two-input type, and the NMOS N4 or the NMOS N5 is shared by the two spare determination circuits 5, respectively. However, it goes without saying that the number of inputs to the NAND circuits 51 and 52 is not limited. That is, NMOS N4 or NM
The OS N5 can be shared by two or more spare determination circuits 5.

Further, the third embodiment can be combined not only with the first embodiment but also with the second embodiment or all the embodiments described below.

[Fourth Embodiment] The fourth embodiment relates to the suppression of an increase in current consumption, particularly as the number of spare determination circuits 5 increases.

For example, in the determination circuit 11 described in the first and second embodiments, regardless of whether the spare determination circuit 5 is used or not, the latch circuit 12 is synchronized with the signal RACT.
Charge / discharge the input. As the number of spare determination circuits 5 increases, the current consumption due to such charging and discharging naturally increases.

The fourth embodiment aims at suppressing an increase in current consumption due to charging and discharging.

FIG. 10 is a circuit diagram of a spare determination circuit 5-4 according to the fourth embodiment of the present invention.

As shown in FIG. 10, the fourth embodiment differs from the second embodiment in that the polarity of the signal bRDENB is reversed and used as the signal RDENB. Signal RDE
NB sets “HIGH” when using the spare determination circuit 5-4.
Level, and set to “LOW” level when not used.

Further, the decision circuit 11-4 has an NMOS N6 which receives the signal RDENB at its gate. NMOS N6
Are connected in series between the NMOS group 61 and the power supply potential Vcc, which receive the signals MIS0 to MIS3 at their gates and are connected in parallel with each other. Specifically, the power supply potential Vcc and the ground potential V
between the ss and the PMOS that receives the signal RACT at the gate
P4, NMOS N6, NMOS group 61, signal to gate
NMOS N7 receiving RACT is connected in series. N
The MOS N6 turns off when the signal RDENB is at a "LOW" level, and turns on when the signal RDENB is at a "HIGH" level.

In the latch circuit 12-4, the inverter is a two-input NAND circuit 62. NA
A first input of the ND circuit 62 includes a PMOS P4 and an NM
The potential of the interconnection node 63 with the OSN 6 is input, and the signal RDENB is input to the second input. NAND
When the signal RDENB is at “LOW” level, the circuit 62
The potential of CMP0 is fixed at “HIGH” level, and the signal RDENB is set to “L”.
When the signal is at the “OW” level, the potential of the node CMP0 is determined by the determination circuit 11-4.
Set to "HIGH" level or "LOW" level according to the output of.

According to the fourth embodiment, the signal
When RDENB is at the “LOW” level, the NMOS N6 is turned off, so that when charging the signal RACT, the charging current flowing from the power supply potential Vcc through the PMOS P4 and NM
The discharge current flowing to the ground potential Vss via the OS N7 stops flowing. Therefore, when the spare determination circuit 5 is not used, the determination circuit 11-4 does not charge or discharge the input of the latch circuit 12-4, that is, the node 63, and can suppress an increase in current consumption.

Next, a modification of the fourth embodiment will be described.

In the fourth embodiment, in order to reduce the number of spare determination circuits 5 while suppressing a decrease in the relief efficiency, one spare determination circuit 5-4 is replaced with a word line WL as a spare word line. The replacement is performed and the refresh cycle of the word line WL is changed.

However, from the viewpoint of suppressing an increase in current consumption, a modification may be made as in the following modification.

FIG. 11 is a circuit diagram of a spare determination circuit according to a modification of the fourth embodiment of the present invention.

As shown in FIG. 11, in the fourth embodiment,
The present invention may be applied to a DRAM having a spare determination circuit 5-4 'corresponding to only the case where the word line WL is replaced with a spare word line. Alternatively, although not specifically shown, the present invention may be applied to a DRAM having a spare determination circuit corresponding only to a case where the refresh cycle of the word line WL is changed.

According to such a modification of the fourth embodiment, when the spare judgment circuit is not used, the judgment circuit 11
-4 does not charge / discharge the input of the latch circuit 12-4, that is, the node 63, so that an increase in current consumption can be suppressed.

[Fifth Embodiment] The fifth embodiment aims at suppressing an increase in current consumption due to an increase in the number of spare determination circuits 5, as in the fourth embodiment.

FIG. 12 is a circuit diagram of an RDENB generation circuit provided in a DRAM according to the fifth embodiment of the present invention.

The signal RDENB is a signal indicating whether or not the spare judgment circuit 5 is used. The signal RDENB indicates whether or not the fuse of the fuse circuit 31 is blown, and whether or not the spare judgment circuit 5 is used. I was able to.

On the other hand, in the fifth embodiment, FIG.
The signal RDENB is generated by the RDENB generation circuit 71 as shown in FIG. The RDENB generation circuit 71
The logic is taken between the enable information programmed in step (1) and the signal RACT to generate the signal RDENB. When the spare determination circuit is not used, the fuse of the fuse circuit 31 is not blown. As a result, the RDENB generating circuit 71 always outputs the signal RDENB at the “LOW” level.

On the other hand, when the spare determination circuit is used, the fuse of the fuse circuit 31 is blown. This allows
The RDENB generating circuit 71 outputs a signal RDENB having the same phase as the signal RACT. That is, the signal RDENB becomes “HIGH” level only when the spare determination circuit is used and the row-related circuit is activated.

FIG. 13 is a circuit diagram of a spare determination circuit used in the fifth embodiment of the present invention.

As shown in FIG. 13, P of the decision circuit 11-5
The signal RDENB generated by the RDENB generating circuit 71 is supplied to the gate of the MOS P4 and the gate of the NMOS N7, respectively.

When the spare determination circuit 5-5 is not used, that is, when the fuse of the fuse circuit 31 is not blown, the signal RDENB is always at "LOW" level,
P4 turns on, and NMOS N7 turns off. For this reason,
The potential of the input node 72 to the latch circuit 12-5 is "HIGH"
Level, and the latch circuit 12-5 fixes the potential of the node CMP0 to the "LOW" level.

When the potential of the node CMP0 is fixed at the "LOW" level, the NOR circuits 15 and 16 are enabled. For this reason, in the fifth embodiment, the signal RDENB is set to “L”.
When the level is at the “OW” level, the NAND circuit 73 further includes a NAND circuit 73 for fixing the potential of the node CMP1 to the “HIGH” level. In order for the circuit 73 to fix the potential of the node CMP1 to the “HIGH” level, the NOR circuit 1
Outputs 5 and 16 are both fixed at "LOW" level. The NAND circuit 73 is of a two-input type. A signal RDENB is input to a first input, and a redundancy determination timing signal is input to a second input. However, the fifth
The redundancy judgment timing signal in the embodiment has a phase opposite to that of the redundancy judgment timing signal in the first to fourth embodiments.

On the other hand, when the spare determination circuit 5-5 is used, that is, when the fuse of the fuse circuit 31 is blown,
The signal RDENB becomes a “LOW” level or a “HIGH” level according to the signal RACT. As a result, the signal RDENB is at the “HIGH” level while the signal RACT is at the “HIGH” level, that is, while the row-related circuit is activated. As a result, the node
The potential of CMP0 attains a "HIGH" level or a "LOW" level depending on whether all the transistors receiving the signals MIS0 to MIS3 at their gates are off or at least one of them is on.

When the signal RDENB is at the “HIGH” level, the NAND circuit 73 sets the potential of the node CMP1 to the “HIGH” level or the “LOW” level in accordance with the redundancy determination timing signal. Further, when the signal RDENB is at the “LOW” level, the potential of the node CMP1 is fixed at the “HIGH” level regardless of the redundancy determination timing signal.

According to the fifth embodiment, when the spare determination circuit 5-5 is not used, the signal RDENB is always set to "L".
OW "level. As a result, the judgment circuit 11-5
For example, the input node 72 to the latch circuit 12-4 is not discharged, and an effect of suppressing an increase in current consumption can be obtained as in the fourth embodiment.

Also, compared to the fourth embodiment, the NMOS
Since the transistor N6 is not required, the number of transistors constituting the determination circuit 11-5 can be reduced. According to this,
The advantage that the determination circuit 11-5 can be easily laid out on a chip can be obtained, which is more advantageous for high integration.

Since the signal RDENB is generated by the RDENB generation circuit 71 based on the signal RACT, the judgment circuit 11-5
The number of signals to be input to the device can be reduced. Judgment circuit 11
-5 from the decrease in the number of signals input to the determination circuit 11
This makes it possible to obtain the advantage that the operation of -5 can be speeded up easily, and it is also advantageous for speeding up the operation.

Next, a modification of the fifth embodiment will be described.

In the fifth embodiment, in order to reduce the number of spare determination circuits while suppressing a decrease in the relief efficiency,
One spare determination circuit 5-5 is shared by both replacing the word line WL with a spare word line and changing the refresh cycle of the word line WL.

However, from the viewpoint of suppressing an increase in current consumption, the following modification may be applied.

FIG. 14 is a circuit diagram of a spare determination circuit according to a modification of the fifth embodiment of the present invention.

As shown in FIG. 15, in the fifth embodiment,
The present invention may be applied to a DRAM having a spare determination circuit 5-5 'corresponding to only the case where the word line WL is replaced with a spare word line. Alternatively, although not specifically shown, the present invention may be applied to a DRAM having a spare determination circuit corresponding only to a case where the refresh cycle of the word line WL is changed.

According to such a modification of the fifth embodiment, when the spare judgment circuit is not used, the judgment circuit 11
-5 does not charge / discharge the latch circuit 12-5, thereby suppressing an increase in current consumption.

In the modification of the fifth embodiment, for example, as compared with the modification of the fourth embodiment, the judgment circuit 11
-5, the number of transistors and the number of input signals can be reduced, the layout of the decision circuit 11-5 on a chip can be easily performed, and the operation of the decision circuit 11-5 can be speeded up. Can be further obtained.

[Sixth Embodiment] In the first to fifth embodiments, one spare determination circuit 5 replaces the word line WL with a spare word line, and changes the refresh cycle of the word line WL. If shared with both.

In the sixth embodiment, one spare determination circuit 5 is shared between replacing a word line WL with a spare word line and replacing a column selection line with a spare column selection line. is there.

FIG. 15 is a circuit diagram of a spare determination circuit according to the sixth embodiment of the present invention.

As shown in FIG. 15, the difference between the spare judgment circuit 5-6 according to the sixth embodiment and the first embodiment is that the judgment circuit 11-6 uses the spare judgment circuit 5 at a low level. BRCSEL to determine whether to use in the column
Is further provided with an NMOS receiving the gate at the gate. This NMOS is connected in parallel to a group of NMOSs that are connected in parallel to each other and receive signals MIS0 to MIS3 and signal bRDENB at their gates.

FIG. 16 is a circuit diagram of a fuse circuit used in the sixth embodiment of the present invention.

As shown in FIG. 16, the row / column switching information fuse circuit 81 includes a fuse (Fuse). This fuse is programmed with information indicating whether the spare determination circuit 5-6 is used for row replacement or column replacement. The latch circuit 82 latches the row / column switching information output from the fuse circuit 81. The output of the latch circuit 82 is input to the bRCSEL generation circuit 83. The bRCSEL generation circuit 83 outputs a signal according to the row / column switching information programmed in the fuse circuit 81.
One of RACT and signal CACT is selected and output as output signal bRCSEL.

When the spare determination circuit 5-6 activates the row,
That is, when used for row replacement, the fuse of the fuse circuit 81 is not blown. Thereby, the bRCSEL generation circuit 81
Outputs a signal bRCSEL having the same phase as the signal CACT.
Therefore, when the column is activated, the signal bRCSEL is set to “HIG
The level becomes H level, the node CMP0 is set to “HIGH”, and information indicating that the address and the program information do not match is output.

On the other hand, when the spare determination circuit 5-6 is used for replacing a column, the fuse of the fuse circuit 81 is blown. As a result, the bRCSEL generation circuit 81 outputs the signal
The signal bRCSEL having the same phase as RACT is output. Therefore, at the time of column activation, signal bRCSEL is at the “LOW” level.

The signal RACT is a signal indicating a period during which a row-related circuit is activated, and the signal CACT is a signal indicating a period during which a column-related circuit is activated.

The signal RCACT shown in FIG. 15 is a signal which becomes "HIGH" level when a row or a column is activated.

According to the sixth embodiment, the row and column can share a spare determination circuit,
Any spare decision circuit can be used for both rows and columns. Therefore, the relief efficiency can be improved.

When this method is adopted, in the spare determination circuit 5, it is desirable to use the same signal line for the row address and the column address in order to simplify the circuit for taking in the address.

Next, a modification of the sixth embodiment will be described.

In the sixth embodiment, one spare determination circuit 5-6 is replaced with a spare word line in one spare determination circuit 5-6 in order to reduce the number of spare determination circuits 5 while suppressing a decrease in the relief efficiency. In this case, the word line refresh cycle is changed and the column selection line is replaced with a spare column selection line.

However, one spare determination circuit may be shared only when replacing a word line with a spare word line and replacing a column selection line with a spare column selection line. Even in this case, compared with the conventional spare determination circuit that only replaces word lines with spare word lines, or a spare determination circuit that simply replaces column selection lines with spare column selection lines, it is possible to suppress a decrease in relief efficiency. In addition, the number of spare determination circuits can be reduced.

FIG. 17 is a circuit diagram of a spare determination circuit according to a modification of the sixth embodiment of the present invention.

As shown in FIG. 17, spare determination circuit 5-
6 'is to replace the word line with a spare word line.
And when the column selection line is replaced with a spare column selection line.

[Seventh Embodiment] The seventh embodiment is obtained by applying the fifth embodiment to the sixth embodiment.

FIG. 18 is a circuit diagram of a spare determination circuit according to the seventh embodiment of the present invention. As shown in FIG. 18, the signal RCSEL is supplied to each of the gate of the PMOS P5 and the gate of the NMOS N8 of the determination circuit 11-6. The signal RCSEL is, for example, a signal obtained by inverting the level of the signal bRCSEL output from the bRCSEL generation circuit 83 described in the sixth embodiment. Therefore, the signal RCSEL
Goes high when a row or column is selected.

The NAND circuit 91 sets the signal RCSEL to "HIG
When the signal is at the “H” level, the potential of the node CMP1 is set to the “HIGH” level or the “LOW” level in accordance with the redundancy determination timing signal, and when the signal RCSEL is at the “LOW” level, Instead, the potential of the node CMP1 is fixed at the “HIGH” level.

According to the seventh embodiment, when the spare determination circuit 5-7 is used to replace a word line with a spare word line, the latch circuit 12 is activated when the column is activated.
In the case where the column selection line is used for replacement of the spare column selection line without charging / discharging the input node of -7, the input node of the latch circuit 12-7 is not charged / discharged when the row is activated. Therefore, an effect that an increase in current consumption can be suppressed can be obtained.

Further, as compared with the sixth embodiment, the determination circuit 11-7 does not need to be provided with an NMOS receiving the signal bRCSEL, and the number of transistors constituting the determination circuit 11-7 can be reduced. According to this, it is possible to obtain an advantage that the determination circuit 11-7 can be easily laid out on a chip.

Next, a modification of the seventh embodiment will be described.

In the seventh embodiment, in order to reduce the number of spare determination circuits 5 while suppressing a decrease in the relief efficiency, one spare determination circuit 5-7 is replaced with a spare word line instead of a word line. In this case, the word line refresh cycle is changed and the column selection line is replaced with a spare column selection line.

However, one spare determination circuit may be shared only when replacing a word line with a spare word line and replacing a column selection line with a spare column selection line. Even in this case, compared with the conventional spare determination circuit that only replaces word lines with spare word lines, or a spare determination circuit that simply replaces column selection lines with spare column selection lines, it is possible to suppress a decrease in relief efficiency. In addition, the number of spare determination circuits can be reduced.

FIG. 19 is a circuit diagram of a spare determination circuit according to a modification of the seventh embodiment of the present invention.

As shown in FIG. 19, spare determination circuit 5-
7 'is to replace the word line with a spare word line.
And when the column selection line is replaced with a spare column selection line.

[Eighth Embodiment] The eighth embodiment employs bR
The present invention relates to reduction of the circuit size of the DHIT output circuit 13 and the bSRFON output circuit 14.

FIG. 20 is a circuit diagram of a spare determination circuit according to the eighth embodiment of the present invention.

As shown in FIG. 20, spare determination circuit 5-8
Is the redundancy judgment timing signal (node CMP1)
And a NOR circuit 101 to which an output (node CMP0) of the latch circuit 12 is input.

The output of the NOR circuit 101 is input to the AND circuit 15 ′ of the bRDHIT output circuit 13 ′, and
The signal is input to the AND circuit 16 'of the RFON output circuit 14'.
The signal SRF is input to an AND circuit 15 ', and a signal obtained by inverting the signal SRF is input to an AND circuit 16'.

According to the eighth embodiment, the first
BRDHIT output circuit 1 while having the same function as that of the first embodiment.
3 'and the number of transistors constituting the bSRFON output circuit 14' can be reduced.

[Ninth Embodiment] The ninth embodiment relates to a reduction in the circuit scale of the bRDHIT output circuit 13 and the bSRFON output circuit 14, as in the eighth embodiment. The embodiment is modified as in the second embodiment.

FIG. 21 is a circuit diagram of a spare determination circuit according to the ninth embodiment of the present invention.

As shown in FIG. 21, the difference between the ninth embodiment and the eighth embodiment lies in the judgment circuit 11-9. The determination circuit 11-9 is similar to the determination circuit 11-2 described in the second embodiment, and is different from the determination circuit 11 in that an NMOS receiving the signal bRDENB is omitted.

The output of the NOR circuit 101 and the signal bRDENB are input to the AND circuit 15 'of the bRDHIT output circuit 13'. In addition, the output of the NOR circuit 101 and the inverted signal of the signal bRDENB are input to the AND circuit 16 'of the bSRFON output circuit 14'.

According to the ninth embodiment, the second
BRDH while having the same function and effect as the embodiment of
The number of transistors constituting the IT output circuit 13 'and the bSRFON output circuit 14' can be reduced.

Also, the ninth embodiment and the invention according to the eighth embodiment can be combined with the third to seventh embodiments as well as the first and second embodiments. is there.

As described above, the present invention will be described by taking a DRAM as an example.
As described above, when one spare determination circuit is shared by rows / columns, the present invention can be applied to memories other than DRAM.

Further, as the fuse, a laser fusing type fuse which is blown by irradiating a laser to the fuse, a current fusing type fuse which blows by applying a large current to the fuse, and data can be written electrically. A possible PROM or the like can be used.

[0161]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device capable of suppressing an increase in chip area due to an increase in the number of program elements for programming a defective address.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a DRA according to a first embodiment of the present invention;
The block diagram of M.

FIG. 2 is a diagram illustrating a DRA according to the first embodiment of the present invention;
FIG. 3 is a configuration diagram of a spare control block included in M.

FIG. 3 is a diagram showing a DRA according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in M.

FIG. 4A is a circuit diagram of a fuse information comparison circuit included in the DRAM according to the first embodiment of the present invention, and FIG. 4B is a circuit diagram of the fuse information comparing circuit according to the first embodiment of the present invention; FIG. 4C is a circuit diagram of a bRDENB generation circuit provided, and FIG. 4C is a circuit diagram of an SRF generation circuit provided in the DRAM according to the first embodiment of the present invention.

FIG. 5A is an operation waveform diagram illustrating an operation example of a fuse information comparison circuit, and FIG. 5B is a diagram illustrating a relationship between a fuse and an output.

FIGS. 6A and 6B are operation waveform diagrams of a spare determination circuit, respectively.

FIG. 7 is a diagram illustrating a DRA according to a second embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in M.

FIG. 8 is a diagram illustrating a DRA according to a third embodiment of the present invention;
FIG. 3 is a configuration diagram of a spare control block included in M.

FIG. 9 is a configuration diagram of a spare control block included in a DRAM according to a modification of the third embodiment of the present invention.

FIG. 10 is a diagram illustrating a D according to a fourth embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

FIG. 11 is a circuit diagram of a spare determination circuit included in a DRAM according to a modification of the fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating a D according to a fifth embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

FIG. 13 is a diagram illustrating a D according to a fifth embodiment of the present invention;
FIG. 2 is a circuit diagram of an RDENB generation circuit included in the RAM.

FIG. 14 is a circuit diagram of a spare determination circuit included in a DRAM according to a modification of the fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating a D according to a sixth embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

FIG. 16 is a diagram illustrating a D according to a sixth embodiment of the present invention;
FIG. 3 is a circuit diagram of a bRCSEL generation circuit included in the RAM.

FIG. 17 is a circuit diagram of a spare determination circuit included in a DRAM according to a modification of the sixth embodiment of the present invention.

FIG. 18 is a diagram illustrating a D according to a seventh embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

FIG. 19 is a circuit diagram of a spare determination circuit included in a DRAM according to a modification of the seventh embodiment of the present invention.

FIG. 20 is a diagram illustrating a D according to an eighth embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

FIG. 21 is a diagram illustrating a D-type power supply according to a ninth embodiment of the present invention;
FIG. 3 is a circuit diagram of a spare determination circuit included in the RAM.

[Explanation of Signs] 1 ... cell array, 2 ... row decoder, 3 ... spare row decoder, 4 ... row related control circuit, 5 ... spare determination circuit, 6 ... precharge circuit, 11 ... comparison circuit, 12 ... latch circuit, 13 ... determination circuit, 14 ... output circuit, 21 ... defective address designation fuse circuit, 22 ... latch circuit, 23 ... fuse information comparison circuit, 24, 25 ... transfer gate, 31 ... enable information fuse circuit, 32 ... latch circuit 41: Fuse circuit for switching information, 42: Latch circuit, 51, 52: NAND circuit, 61: Transistor group, 62: NAND circuit, 71: RDENB generation circuit, 72: Input node, 73: NAND circuit, 81: Low / Fuse circuit for column switching information, 82 latch circuit, 83 bRCSEL generation circuit, 91 NAND circuit, 10 1. NOR circuit.

Continued on the front page F term (reference) 5B024 AA15 BA20 BA21 BA29 CA07 CA11 CA16 CA17 DA10 DA14 DA18 5L106 AA01 CC04 CC13 CC17 CC22 CC32 GG07

Claims (11)

[Claims] 1. A plurality of bit lines for exchanging information with a memory cell, a plurality of word lines for selecting a memory cell from which information is taken out from the bit line, and a plurality of word lines connected to a memory cell from which information cannot be taken out normally. A spare word line for relieving a word line that has lost the spare word line, and a spare word line for the word line based on the rescue information. And a spare determination circuit having a function of changing a refresh cycle of the word line based on the relief information. 2. The rescue information includes enable information indicating whether a spare determination circuit is used, and comparison information indicating whether input address information matches address information of a word line to be remedied. 2. The semiconductor integrated circuit device according to claim 1, further comprising selection information for selecting one of replacement with the spare word line and change of the refresh cycle. 3. The rescue information includes enable information indicating whether a spare determination circuit is used and comparison information indicating whether input address information matches address information of a word line to be remedied. When the spare information indicates that the spare determination circuit is used, the spare determination circuit enables replacement with the spare word line; and when the enable information indicates that the spare determination circuit is not used, 2. The semiconductor integrated circuit device according to claim 1, wherein the change of the refresh cycle is enabled. 4. The spare determination circuit, which is controlled by the comparison information, includes a determination circuit that determines whether or not to perform relief based on whether or not a group of transistors connected in parallel to each other conducts. 4. The semiconductor integrated circuit according to claim 2, wherein a part of a current path from a power supply potential including the transistor group to a ground potential includes a transistor controlled by the enable information. Circuit device. 5. The semiconductor integrated circuit according to claim 2, wherein the enable information includes information indicating whether a row is activated. apparatus. 6. The semiconductor integrated circuit device according to claim 5, wherein said spare determination circuit is enabled based on information including said enable information and relief determination timing information indicating relief determination timing. A replacement control signal output circuit for outputting a signal for controlling replacement with the spare word line based on the repair information; and controlling a change of the refresh cycle based on the repair information. The semiconductor integrated circuit device according to claim 1, further comprising a cycle change signal output circuit that outputs a signal. 8. The spare determination circuit includes a transmission circuit that transmits the relief information to the replacement control signal output circuit and the cycle change signal output circuit in response to relief determination timing information indicating a relief determination timing. 8. The semiconductor integrated circuit device according to claim 7, wherein the transmission circuit is shared by the replacement control signal output circuit and the cycle change signal output circuit. 9. A connection portion between the replacement control signal output circuit and a replacement control signal line to which a replacement control signal is transmitted is shared by a plurality of the replacement control signal output circuits. 9. The semiconductor integrated circuit device according to claim 7, wherein a portion connected to a cycle change signal line through which a signal is transmitted is shared by a plurality of cycle change signal output circuits. 10. A plurality of bit lines for exchanging information with a memory cell, a column selection line for selecting the bit line, a plurality of word lines for selecting a memory cell from which information is taken out to the bit line, A spare word line to rescue a word line connected to a memory cell from which information cannot be taken out,
A spare bit line for relieving a bit line connected to a memory cell from which information cannot be normally taken out; a spare column selection line for selecting the spare bit line; and the information cannot be taken out normally. Relief information for relieving a memory cell is held, the word line is replaced with the spare word line based on the relief information, and the column selection line is replaced with the spare column selection line based on the relief information. And a spare determination circuit having a replacement function. 11. A plurality of bit lines for exchanging information with a memory cell, a column selection line for selecting the bit line, a plurality of word lines for selecting a memory cell from which information is taken out to the bit line, A spare word line to rescue a word line connected to a memory cell from which information cannot be taken out,
A spare bit line for relieving a bit line connected to a memory cell from which information cannot be normally extracted; a spare column selection line for selecting the spare bit line; and the information cannot be normally extracted. Relief information for relieving a memory cell is held, the word line is replaced with the spare word line based on the relief information, and the column selection line is replaced with the spare column selection line based on the relief information. And a spare determination circuit having a function of changing a refresh cycle of the word line based on the relief information.