JPH06103482B2 - I / O controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device, and more particularly, to receiving data from a channel device via a multi-byte bus and sending it to an external storage device via a multi-byte bus. The present invention relates to an input / output controller that transfers data.

[Prior Art] Conventionally, a direct memory access control method or the like is known as a technology for continuously transferring a plurality of transfer blocks (hereinafter, referred to as fields) to a lower device.
An example of this type of device is the invention described in JP-A-59-136830.

However, in the above-mentioned conventional technique, when transferring a plurality of fields using a plurality of parallel buses, a technique of recognizing each field boundary and transferring data is not considered.

[Problems to be Solved by the Invention] Generally, an input / output control device that transfers data output from an upper channel device to a lower external storage device receives and transmits the data via a plurality of parallel buses. Problems in the case of performing the above will be described with reference to FIG.

In FIG. 4, the input / output control device receives data from the channel device via the buses B1 and B2 and sends the data to the external storage device via the buses B3 and B4. In FIG. 4, 1-byte unit data D0 to D9 sent from the higher-level device of the channel device is transferred from the channel device to the bus B.
2 bytes are transferred in parallel via 1 and B2. At this time, 1
The field consists of 5 bytes of data, and data D4 and
Assuming that there is a field boundary between D5, the channel device sends data D through bus B1 and B2 as shown.
Send 0 to D9. The data D4 and the data D5 are field boundaries, and may be transmitted to the buses B1 and B2 in a state where the timings are deviated as shown in the figure, or may be transmitted at the same timing. This is determined by the content of the data transfer request sent by the input / output control device to the channel device.

The input / output control device receives the data on the buses B1 and B2 and sends the data D0 to D9 to the buses B3 and B4 connected to the external storage device. The data transfer order is shown in FIG. Must be in order. That is, the data D0 to D9 can be transferred through the buses B3 and B4 in the same order as they are received, but the data D5 to D9 must be transferred in the transmission order of the buses B1 and B2. This is because of the necessity of data processing in the external storage device. That is, if the data is not exchanged as described above, the data on the device bus of the external storage device will be D0 to D9 as shown in the figure.
This is because it does not take the form of, and becomes an obstacle to data storage.

When such a data exchange is performed by the channel device, the channel device needs to be aware of the field peculiar to the external storage device, and the channel control becomes complicated, so that there is a problem that the channel device cannot be standardized. . That is, normally, when the channel device sends data D0 to D4, D5 to D9 in field units as shown on buses B1 and B2 in FIG. 4, for example, the first buffer among the two buffers in the channel device is used. The data D0 to D4 are set in the buffer and the data D5 to D9 are set in the second buffer. This data set is performed before a data transfer request is received from the input / output control device, and the next data is set in the first and second buffers after a lapse of a certain time after the request arrives. There is. Therefore, if the data D5 to D9 are to be transmitted in the format of the buses B3 and B4 shown in FIG. 4, the data D0 to D4 is transmitted from the first buffer, and then the data between the first buffer and the second buffer is transmitted. The operation of exchanging data is required. This is because the channel device is aware of the field structure of the external storage device connected to the input / output control device. Since the external storage device has a different field structure for each model, the control of the channel device is complicated. , That makes standardization difficult. Therefore, when the channel device receives a data transfer request in field units from the input / output control device, the bus B in FIG.
Data in field units in the format shown in 1 and B2 D0 to D4, D5 to D
Sending 9 to the input / output control device is a matter described in the specification “JS type information processing device composite system input / output interface common specification” specified by Nippon Telegraph and Telephone Public Corporation. Further, in the conventional technology, the external storage device may partially request the input / output control device to send data,
There is a problem that the control of the external storage device becomes complicated.

According to the present invention, when a field boundary exists in a series of data transferred via a plurality of buses, the data can be divided at the boundary to align the data and transferred to an external storage device. An object is to provide an output control device.

[Means for Solving Problems] An input / output control device of the present invention receives field-unit data transmitted from a channel device via a plurality of buses, and receives received field-unit data via a plurality of buses. The data is transferred to an external storage device via a field, and in particular, the field is set by setting the number of data included in one field, and the channel device is sequentially requested to transmit data in the field unit set above. First
In the case where the data of the field unit according to the setting transmitted from the channel device in response to the request is sequentially received, and the data order in the received field is not suitable for the data processing in the external storage device, A second means for arranging the data in the field in an order suitable for data processing in the external storage device is provided.

[Operation] According to the input / output control device of the present invention, the number of data in the field is set by the first means, and data in field units are sequentially requested to the channel device.
Then, the second means arranges the data in the field in an order suitable for the data processing in the external storage device when the received data order in the field is not compatible with the data processing in the external storage device. This allows the channel device to simply send data out on a plurality of buses according to the data order in the memory. Further, this can simplify the data transfer control of the channel device. Further, since the channel device does not need to take in the control peculiar to the input / output control device that is aware of the field boundaries, the control performed by the channel device can be standardized regardless of the type of the external storage device. on the other hand,
Since the second means arranges the data to be transferred to the external storage device in the control device, the control can be simplified without making the external storage device aware of the field boundary.

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to the examples shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a disk control device. The disk controller shown in the figure receives data from a channel device (not shown) via the 1-byte wide bus outs 6a, 6b and transfers the data to the disk device via the 1-byte wide device buses 26a, 26b. is there.

In FIG. 1, the processor 17 determines the data transfer number for one field before the data transfer is started by the request number counter 15
Set to. After that, the processor 17 instructs the request control unit 16 to start a data transfer request by setting the request start instruction signal 28 to “1”. As a result, the request control unit 16 sends the data transfer request signal 1 at regular intervals. The request number counter 15 is decremented according to the request bus display signals 2a and 2b each time the data transfer request signal 1 is output. That is, when both the request bus display signals 2a and 2b are "1", 2 is subtracted, and when one of the request bus display signals 2a and 2b is "1", 1 is subtracted. This subtraction is performed as follows. When both the request bus display signals 2a and 2b are "1", the output value of the AND gate 11 becomes "1" and the request number counter 15 is instructed to decrement "-2". When only one of the request bus display signals 2a and 2b is "1", the output value of the AND gate 11 becomes "0" and the decrement instruction of "-1" is issued. Normally, the disk controller is 2
Since the bytes of data are transferred in parallel, the request bus display signals 2a and 2b are both "1" and the request counter 15 is decremented by -2. However, when the number of data transfers forming one field is odd, the value of the request number counter 15 finally becomes "1". The decoder 13 detects this state and outputs "1" to the OR gate 10. As a result, the request bus display signal 2b becomes "0". This means a data transmission request only to the bus out 6a, as will be described later.
No data transmission request is sent to 6b.

In FIG. 1, when the data transfer request signal 1 is output, data is output from the channel device (not shown) to the bus outs 6a and 6b together with the data transfer response signal 4. At this time, the validity of each data on the bus outs 6a and 6b is indicated by the bus validity display signals 5a and 5b, which are output from the channel device at the timings shown in FIG. That is, the channel device sends data on the bus out 6a in response to the request bus display signal 2a, and at the same time, outputs the bus valid display signal 5a.
Similarly, the channel device sends data to the bus out 6b in response to the request bus display signal 2b and sets the bus valid display signal 5b to "1". Therefore, as described above, the requested bus display signal 2a is "1" and the requested bus display signal 2a
When 2b is "0", the data transmission request is sent only to the bus out 6a.

Further, the switching timing of the data on the bus valid display signals 5a, 5b and the data on the bus outs 6a, 6b are equal as shown in FIG. 2, and both can be sampled at the rising timing of the data transfer response signal 4.

In the command to continuously write a field on the disk device, when the last transfer of the previous field is performed using only the bus out 6a, that is, the request number counter
When the value of 15 becomes "1" and the transfer request is made by setting the request bus display signal 2a to "1" and 2b to "0", the channel device outputs the first data of the next field onto the bus out 6b. . At this time, the processor 17 determines that the start data of the next field is the bus out 6b based on the value set in the request number counter 15 (even number or odd number) during the previous field processing.
The control signal 30 is determined to be present above, and the control signal 30 is set to "1" before the start of the transfer request of the next field. Control signal 30
Is set to "1", the first data transfer of the next field is performed using only the bus out 6b as described below, and the data contents are written when writing to the data buffers 24a and 24b. Change the order of the data to be exchanged and written to the disk device.

That is, at the start of transfer of the next field, the flip-flop
14 is initialized so that its output value becomes "1". Since the control signal 30 is "1", the output of the AND gate 12 becomes "1" and the request bus display signal 2a becomes "0". Here, when the data transfer request signal 1 is transmitted, the flip-flop 14 is triggered when the data transfer request signal 1 falls, and the value is set to "0". Therefore, the output value of the AND gate 12 that is output in synchronization with the data transfer request signal 1 for the second and subsequent times is "0", and the request bus display signal 2a is "1".
Becomes In addition, at the timing when the data transfer request signal 1 is first output, as described above, the request bus display signal
2b becomes "1", bus out to channel device
Request to send data to 6b. The response from the channel device to the first request is made by sending data to the bus out 6b and setting the bus valid indication signal 5a to "0" and 5b to "1". The data on the bus valid indication signal 5b and the data on the bus out 6b output from the channel device are respectively output to the buffers 18b and 19 at the output timing of the data transfer response signal 4.
Stored in b. At this time, since the control signal 30 is "1", the bus valid display signal 5b is input to the buffer control circuit 22a by the selector 20a, and the data on the bus out 6b is input to the data buffer 24a by the selector 21a. In this state, the buffer control circuit 22a causes the data buffer 2
To write 1 byte of data to 4a and update the value of the write address pointer 23a to the next write address +
Do 1 Then, from the channel device, bus out 6a, 6b
All the data transferred via the selectors 21a and 21b are switched. That is, the selector 21a is the buffer 1
The data in 9b is switched and output to the data buffer 24a, and the selector 21b outputs the data in the buffer 19a to the data buffer 24b.
Output to the address pointer 23
It is stored at the address indicated by a and 23b.

As a result of the above-mentioned operation, the data order in the data buffers 24a and 24b is as if the bus out 6a as shown in FIG.
This is the same as when the first data D5 of the next field is transferred above and the second data D6 of the next field is transferred onto bus out 6b. The data stored in this way is stored in the address pointer according to the command from the buffer output control unit 29.
By 25, the data is sent to the device buses 26a and 26b in the order arranged as shown in FIG.

According to this embodiment, the order of data transferred to the disk device is automatically arranged by the hardware in the control device. Therefore, in the channel device, it is not necessary to pay attention to the order of the data, so that the control content in the channel device can be simplified.

In the above embodiment, the case where data of 5 bytes in one field is transferred via two buses has been described as an example, but the present invention is not limited to this.
The number of data in one field and the number of parallel buses may be arbitrary.

[Effects of the Invention] As is apparent from the above description, according to the present invention, when the data in units of fields transferred via a plurality of buses is not suitable for the data processing of the external storage device, the external storage device is used. It is possible to provide an input / output control device capable of arranging data so as to be compatible with the data processing described above and transferring the data to an external storage device. Therefore, the channel device can avoid performing the control peculiar to the device, and the control content of the channel device can be standardized regardless of the device. In addition, by arranging the data to be transferred to the external storage device in order from the bus of the upper byte, the external storage device, which has been conventionally used, requests to partially send the data to the bus. Can be omitted, and the control contents of the external storage device can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1, and FIG.
FIG. 4 is an explanatory diagram showing an example of data alignment executed in the embodiment shown in FIG. 1, and FIG. 4 is an explanatory diagram showing a concrete example of data alignment performed in the present invention. 1 ... Data transfer request signal, 2a, 2b ... Request bus display signal,
4 ... Data transfer response signal, 5a, 5b ... Bus valid display signal, 6
a, 6b ... Bus out, 15 ... Request counter, 16 ... Request control unit, 22a, 22b ... Buffer input control unit, 23a, 23b ... Write address pointer, 24a, 24b ... Data buffer, 25 ... Read address pointer, 29 ... Buffer output control section.

Claims (1)

[Claims] 1. An input / output control device for receiving field-unit data transmitted from a channel device via a plurality of buses and transferring the received field-unit data to an external storage device via a plurality of buses, Field setting is performed by setting the number of data included in one field, and first means for sequentially requesting the channel device to perform data transmission in the set field unit, and the channel device according to the request. If the data order in the received field is sequentially received according to the above settings and the data order in the received field is not compatible with the data processing in the external storage device, the order is adjusted to the data processing in the external storage device. A second means for aligning data in the field. .