JP2001117891A - Inter-processor data transfer control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inter-processor data transfer control system by which a data transfer time is shortened. SOLUTION: The system is provided with at least one pair of systems for executing one data transfer by a main memory 21, a processor 20 and a data transfer controller 30 so that data is transferred between the systems via the data transfer controller 30. The system is constituted to transmit data to an opposite data transfer controller and, at the same time, to request next data to one's own processor without being affected by a response signal from the opposite data transfer controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control system between processors.

[0002]

2. Description of the Related Art An inter-processor data transfer control device (CC)
In a multiprocessor system in which A) is connected to both processors via a channel control device (CHC) and data is transferred between the processors, a buffer register (for one transfer unit) is conventionally stored in a CCA connected to each processor. BR) and data is transferred between CCAs, the data sent to the partner CCA is
The next transfer data has been requested to the own processor by receiving the response signal notifying that the data has been normally stored in the buffer register of A.

FIG. 6 is a sequence diagram showing conventional data transfer control, in which a data transfer control device (read side) and a data transfer control device (write side) are connected by an interface between CCAs. First, when the read side CCA completes preparations for data reception (S1), a data transfer start instruction is issued to the write side CCA (S2). On the light side CCA,
A data request is made to the host processor, and the buffer register (B
R) stores the data from the processor (S3).

After the write CCA issues a data transfer request (data transfer start signal) to the read CCA (S4), the write CCA prepares transmission data in the BR (S5), and transmits the data to the read CCA. Then, data transfer of 8 bits × 4 is performed (S6). Upon completion of the data reception (S7), the read side CCA transfers the contents of the BR to the main storage device MM and stores it (S8). Next, BR
Becomes empty, preparation for data reception is completed, and the process shifts to a state of waiting for data reception from the write side (S9).

On the other hand, the read-side CCA receiving the data
Then, a response signal is returned to the write-side CCA (S10). The write-side CCA receiving this response signal requests the next data from the host processor and stores the memory read data in the BR (S11). Next, the write-side CCA sends a transfer request (data transfer start signal) to the read-side CCA.
(S12), prepare transmission data stored in the BR (S13), and transfer the data to the read-side CCA (S14).

[0006] When the data reception is completed (S15), the read side CCA transfers the contents of the BR to the main memory MM and stores it (S16). Next, the BR becomes empty, preparation for data reception is completed, and the process shifts to a state of waiting for data reception from the write side (S17). On the other hand, when the data reception is completed by the read-side CCA (S15), a response signal is returned to the write-side CCA (S18). The write-side CCA receiving the response signal requests the next data from the host processor and stores the memory read data in the BR (S19). Then, after issuing a transfer request to the read side CCA (S20), transmission data is prepared in the BR (S21), and the data is transferred (S22).

When the data reception is completed, the read-side CCA stores the BR data in the main storage device MM (S2).
4). When the data reception is completed, a response signal is returned to the write-side CCA (S23), and when the last data transfer is confirmed by the contents of a register (not shown), the transfer end is returned together with the response signal (S25).

When the write-side CCA receives this transfer end, it notifies the host processor of the end (S26).
The write-side CCA transmits an end confirmation (S27). The read-side CCA reports an end to the upper-level processor (S28).

FIG. 7 is a block diagram showing a configuration example of a conventional CCA. In the figure, CCA denotes a control unit 10, buffers B1 to B5, buffers B8 to B10, and an AND gate B.
6, B7, buffer register (BR) 11, serial
It comprises a parallel conversion register 12. The serial / parallel conversion register 12 is a serial-to-parallel
Parallel-to-serial bidirectional conversion is possible. The right side of the CCA is the processor side, and the left side is the partner C
CA.

[0010] When a data reception control response signal indicating completion of reception of the partner CCA data is input from the partner CCA, the CC
A issues a data transfer request to the processor and receives a data reception control response signal. The CCA that has received the received data reception control response signal issues a data transfer request signal to the counterpart CCA. On the other hand, the received data input from the processor first enters the AND gate B6. After that, it is stored in the buffer register 11. At this time, the inside of the BR is composed of 32-bit data of 0 to 31.

The output of the BR enters the serial / parallel conversion register 12 and is converted into parallel data of 8 bits × 4. This serial / parallel conversion register 1
As shown in the figure, the output of No. 2 is converted into eight 4-bit serial data when read out, and is output serially from the buffer B9. The output of the buffer B9 is provided to the partner CCA as transmission data.

The same operation can be performed in the opposite direction. That is, the data sent from the partner CCA is:
The data is received by the buffer B10, and is converted into parallel data by the serial / parallel conversion register 12. The parallel data enters the AND gate B7 (the AND gate B6 is prohibited at this time), and is converted into 32-bit data when entering the BR11 from the B7. The converted data is provided as transmission data to the processor via the buffer B8. That is, this circuit is capable of bidirectional data transfer.

[0013]

In the above-mentioned conventional example,
A data waiting time from receiving the response signal in the CCA to storing data in the BR occurs. As a result, C
Although this hinders the speeding up of the data transfer control between CAs, the speed up of the data transfer control is accompanied by an increase in the failure rate due to an increase in the amount of hardware.

In the conventional method, the data buffer register (BR) in the CCA has only one transfer amount, and the complexity of the circuit due to the multiple buffer method is suppressed, and the high speed is sacrificed. However, due to recent demands for faster processing and reduced processor load, the data waiting time in the CCA cannot be ignored.
It has become necessary to achieve both simplification of the circuit and speeding up of the CCA.

The present invention has been made in view of such problems, and has as its object to provide an inter-processor data transfer control system capable of shortening the data transfer time.

[0016]

As means for improving the processing capacity of a system, means for increasing the processing capacity of the entire system by increasing the number of processors and dispersing the processing is adopted. In the case of electronic exchange systems, with the increase in subscribers,
The processing is distributed by increasing the number of processors so that the load on the processor does not increase and the service does not deteriorate.

A device indispensable for this processor expansion is C
In CA, as the number of processors increases, the CCA will also increase, which means that the common control processor C
The burden on CA device control also increases.

According to the present invention, the increase in the failure rate due to the increase in the amount of hardware is suppressed, the queuing related to the data transfer in the CCA is reduced as much as possible, the speed of the CCA internal processing is increased, and the processor is used efficiently. It relates to the operation of the interface between CCAs.

Conventionally, after confirming that the data sent to the counterpart CCA has been normally stored in the buffer register in the counterpart CCA by the content of the response signal, the CCA requests its own processor for the next data. In other words, there is a waiting time inside the CCA from sending data to the partner CCA until receiving the response signal, which is indispensable for preventing the buffer overflow of the own CCA.

According to the present invention, by controlling the serial / parallel conversion register to be used as an additional buffer, the buffer overflow is prevented from being prevented, and the counter CC is controlled.
A sends data to A and requests the next processor for the next data without waiting for a response signal from the partner CCA.

Then, the next data reception from the processor is executed after confirming that the reception response signal from the serial / parallel conversion register is received (data is set in the buffer register). In this case, the control waiting time is reduced, and the speed of the CCA data transfer is increased.

That is, the following configuration is employed as means for preventing overflow from occurring in a buffer for one data transfer. CCA data transfer is performed by converting parallel data into serial data and performing the conversion in units of 1 byte in accordance with a designated timing condition. The register (for one data transfer) used for this serial / parallel conversion is stored in the second data. Change the control so that it can be used as a buffer.

That is, a signal (data transfer request, response signal) for controlling the interface between the serial / parallel conversion register and the buffer register is provided to confirm the data transfer, and the serial / parallel conversion register is transmitted from the counterpart CCA. By confirming the response signal indicating the completion of data reception, the next data is controlled to be accepted.

The data transfer request to the partner CCA is:
After confirming the response signal of the previous data reception completion from the partner CCA, the serial
Data is not lost due to data transfer to the parallel conversion register.

The next data from the processor is stored in the empty buffer register. If the reception completion response signal of the previous transfer data from the partner CCA has been received, the contents of the buffer register are sent to the partner CCA (data is moved from the buffer register to the serial / parallel conversion register), and the next data is sent to the processor. Request to.

Further, the following measures for reducing the waiting time in the CCA are taken to speed up the data transfer between the CCAs. Conventionally, the next data request to the processor is
This is performed after confirming the response signal of the normal data reception in the CA, but this is performed without recognizing the reception of the response signal and at the same time as sending the data, making a data request and eliminating the waiting time until the response signal is received.

That is, the next transfer data request and transfer control between the CCA and the processor are performed in parallel with the data transfer between the CCAs, thereby saving the time required for the data transfer between the processors and increasing the speed.

(1) FIG. 1 is a block diagram showing the principle of claim 1. In the figure, 20 is a processor (CC), 21 is a main memory (MM) connected to the processor 20,
Reference numeral 30 denotes a data transfer control device (CC) for performing data transfer control.
A) and 31 are buffer registers (BR) in which data is temporarily stored in the CCA 30. Processor 20 and C
The CA 30 is connected via a common I / O bus 32. The CCAs 30 are connected to each other. Then, the processor 20 reads the data stored in the main memory 21 and transfers the data to the counterpart CCA. The connection between CCA and CCA is not limited to one set, but may be connected to a plurality of sets.

With this configuration, one of the CCs
A transfers the data stored in the BR to the other party's CCA, and then promptly requests the next processor to transfer the next data, thereby shortening the data waiting time and speeding up the data transfer time. can do.

(2) According to the second aspect of the present invention, in the case where the data transfer of the data transfer control device is performed by converting parallel data into serial data and executing the data in units of 1 byte in accordance with a designated timing, It is characterized in that it has means for using a register used for conversion as a buffer register.

With this configuration, the hardware can be simplified by using the register as a buffer register. (3) The invention according to claim 3 has means for permitting storing of data from the corresponding processor in the buffer register after confirming that a response signal from the serial / parallel conversion register has been received. It is characterized by.

According to this structure, a reliable operation can be performed by storing the data in the BR after receiving the response signal from the serial / parallel conversion register.

(4) The invention according to claim 4 is a serial communication device.
The parallel conversion register is provided with means for confirming a response signal indicating completion of data reception from the partner data transfer control device to enable reception of the next data.

With this configuration, the serial / parallel conversion register can perform a reliable operation by receiving the next data after receiving the data reception completion from the partner data transfer control device.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention. 1 are denoted by the same reference numerals. In the figure, 20 is a processor (CC), 21 is a main memory (MM) connected to the processor 20, and 22 is a channel controller (CHC) connected to the processor 20. Reference numeral 30 denotes a data transfer control device (CCA) for transferring data between processors.

The processor 20, the main memory 21, the channel controller 22, and the CCA constitute a main processor or a call processor. In the embodiment shown in the figure, an example is shown in which two sets of call processors are connected to the main processor, but the present invention is not limited to this.

When the number of CCAs connected to the I / O bus of the main processor increases, the occupation rate of the CHC by the CCA increases. Therefore, the transfer sequence of the CCA alone is shortened, and the burden on the CHC of the main processor is reduced. Then, it can be transferred to other processing.

FIG. 3 is a block diagram showing an embodiment of the CCA according to the present invention. The same components as those in FIG. 7 are denoted by the same reference numerals. In the figure, B11 is an AND gate which receives a data reception control response signal from the processor side and a data reception control response signal from the partner CCA side and outputs it as a data transfer request signal.

B12 is a data reception control response signal from the processor to one input and a response signal from the serial / parallel conversion register 12 to the other input (writing completed).
An AND gate that receives the data and outputs it to the processor as a data transfer request signal. The AND gate B12 is input to the AND gate B6 as a gate control signal.

The output of the AND gate B11 is a serial
The write request signal is input to the parallel conversion register 12. In the present invention, the serial / parallel conversion register 12 is also used as a second buffer. A mechanism for request and response processes is provided between the serial / parallel conversion register 12 and the BR, which has only passed conventionally, so that it can be used as a buffer (the usage status management of the serial / parallel conversion register is performed. ,
So that the data does not disappear prematurely).

The parallel data from the serial / parallel conversion register 12 is input to the AND gate B7. The received data is also input to the AND gate B6 via the buffer B5. One of these B6 and B7 is selected and input to the buffer register (BR) 11. Other configurations are the same as those in FIG. Hereinafter, referring to the flowchart of FIG.
The operation of the present invention will be described.

First, it is checked whether a transfer start request signal has been received from the partner CCA (S0). Upon receipt, the control unit 10 issues a data transfer request to the processor via the buffer B4 (S1 The first data transfer request is based on data transfer from a partner CCA not shown).
In response to this signal, the processor reads out the data stored in the main memory, and supplies the data as received data to the buffer B6 via the buffer B5. At this time, the gate of the buffer B7 is closed. As a result, the data from the processor is set in BR (S2). In the figure, 32
This shows how bits are expanded.

Next, the control unit 10 issues a data transfer request to transmit data to the other party's CCA (S
3). This request is output from the buffer B2 and notified to the counterpart CCA (the first data transfer request is based on the reception of a data reception control response signal from the processor). next,
The control unit 10 checks whether the serial / parallel conversion register 12 is an empty or write completion response (S4).

When the serial / parallel conversion register is empty or the writing is completed, the control unit 10
The BR data is moved to the serial / parallel conversion register 12 (S5). In this state, BR can be used.

With this configuration, a reliable operation can be performed by including a procedure of receiving a response signal from the serial / parallel conversion register and then storing data in the BR.

The control unit 10 transfers the data to the serial / parallel conversion register 12 and, at the same time, requests a data transfer request signal from the processor for reading data of the next memory address (S6). Next, the control unit 10 checks whether the next transfer data has been received from the processor (S7).

If received, data is set in BR (S8). Next, the controller 10 sends the data stored in the serial / parallel conversion register 12 to the partner CCA at substantially the same timing as in step S6.
The output of the serial / parallel conversion register 12 serially transmits 8-bit parallel data four times via a buffer B9 from a signal line having a width of 8 bits. That is, the operation of transferring the first D0 to D7 at the same timing using an 8-bit signal line, transferring the data of the next D8 to D15 after the lapse of a specific timing is repeated, and finally, the data D24 to D31 are transferred. Forward.

The control unit 10 checks whether a response signal indicating completion of data transmission / reception has been received from the counterpart CCA (S9). In the figure, the reception of the next data and the reception confirmation of the response from the counterpart CCA are performed sequentially, but are actually performed at random. In other words, the response signal reception can be chucked even if the data has not been received. Opponent CC
The response signal from A enters buffer B1. When this data transfer end signal is received, it is checked whether data transfer has been completed for all data (S1).
0). If not completed, the process returns to step S3 (the next transfer data has been set to BR in S8), and the data transfer is repeated. When the transfer of all data is completed, the control unit 1
0 notifies the processor of a data transfer end report (S1).
1).

In step S10, the next data is requested to the processor before the end of the data transfer is detected. Therefore, the data read last and preceding is not transferred (dummy transfer). With this configuration, the serial-parallel conversion register can perform a reliable operation by receiving the next data after receiving the completion of data reception from the partner CCA.

According to this configuration, any one of the CCs
After transferring the data stored in the BR to the other party's CCA, A can promptly request the next processor to transfer the next data, shorten the data waiting time, and speed up the data transfer time.

According to this configuration, the hardware can be simplified by using the serial / parallel conversion register 12 also as a buffer register. FIG. 5 is a sequence diagram showing the data transfer control operation of the present invention. When preparation for data reception is completed in the read-side CCA (S1), a data transfer start instruction is issued to the write-side CCA (S2). The write CCA requests data from the host processor and stores the data from the processor in BR (S3). When the data is stored, a transfer request is issued to the read side CCA (S4). Light side CCA
Then, after confirming that the serial / parallel conversion register 12 is empty, the contents of the BR are transferred to the serial / parallel conversion register 12 for data transfer (S6). At the same time, the next transfer data (data of the next MM address) is requested from the upper processor (S5).

In the present invention, a data transfer request is issued to the own processor simultaneously with the transfer request of the partner CCA. In response to a data transfer request from the partner CCA, a transfer request to the serial / parallel conversion register 12 is made, and data is moved from the BR to the serial / parallel conversion register 12 in response to the empty state, and at the same time, the data of the next memory address is sent to the processor (See FIG. 3). Next, when data is received from the host processor, BR is set (S11).

In the present invention, the data from the processor is:
By confirming the reception of the response signal from the serial / parallel conversion register 12, drawing on the BR is permitted. By confirming that the data of the current BR has been moved to the serial / parallel conversion register 12 and writing data from the next processor, the data is prevented from being lost halfway.

The read side CCA receives the data (S
7) The BR data is transferred to the MM (S8). As a result, the data is stored in the main storage device MM. On the other hand, when the data reception is completed, a response signal is returned to the write side (S9). On the other hand, the read side completes the transfer and enters a data reception waiting state (BR empty) (S10). When the write side receives the response signal of the completion of the previous data transfer from the partner CCA, it issues a transfer request to the read side (S12), and the previous data has already been transferred to the BR of the partner CCA to prevent the data from being lost halfway. After confirming that there is, after confirming that the serial-parallel conversion register 12 is empty, the contents of the BR are written to the serial-parallel conversion register 12 and the movement data is transferred (S14).

Further, the next transfer data is requested from the upper processor. The read side receives the data (S15), and B
Data is transferred from R to MM (S16). On the other hand, when the data is received, a response signal is returned from the read side to the write side (S18). After completing the transfer, the read side shifts to a data reception waiting state (S17).

When the write side confirms the response signal reception, it issues a transfer request (S20), and confirms that the serial / parallel conversion register 12 is empty as in the previous transfer, and confirms the contents of the BR. Is transferred to the serial / parallel conversion register 12 to perform moving data transfer (S
22). Furthermore, it requests the next data from the host processor,
Set the received data in BR. The read side receives the data (S23) and transfers the data from the BR to the MM (S23).
24).

Next, a response signal of the final data is returned from the read side to the write side (S25), and then a transfer end signal is returned (S26). Upon receiving this response, the write side reports the end to the host processor without issuing a data transfer request (S27). Next, a response signal is returned from the write side to the read side (S28), and the read side reports an end to the host processor (S29).

The next data is stored in the BR on the write side, but no data transfer is performed from the final data notification from the read side, and the BR setting data is not used. FIG.
6 and the conventional example shown in FIG. 6, it can be seen that the waiting time shown in FIG. 5 is greatly reduced.

Although it takes a long time from reception of the response signal to transmission of the transfer request (Δt shown in FIG. 5) in FIG. 5, the next data is already stored in the BR, An immediate transfer request can be issued upon reception.

According to the present invention, the number of data waiting sequence steps in the data transfer control of the inter-processor data transfer control device is reduced, so that the speed of data transfer can be increased, and the processing capacity of the entire system can be improved. .

[0061]

According to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, at the same time as sending data to the partner data transfer control device, it requests the own processor for the next data without being affected by the response signal from the partner data transfer control device and receives the data. With this configuration, one of the CCAs can transfer the data stored in the BR to the counterpart CCA and immediately request the next data transfer from its own processor. The waiting time can be reduced and the data transfer time can be increased.

(2) According to the second aspect of the present invention, when the data transfer of the data transfer control device is performed by converting parallel data into serial data and executing the data in units of one byte in accordance with the designated timing, By having means for using the register used for data conversion also as a buffer register, hardware can be simplified by using the register also as a buffer register.

(3) According to the third aspect of the present invention, storing of data from the corresponding processor in the buffer register is permitted after confirming that a response signal from the serial / parallel conversion register has been received. Means for receiving the response signal from the serial / parallel conversion register, that is, moving the contents of the BR to the serial / parallel conversion register, confirming that the BR is empty, and then transmitting the next signal to the BR. By storing the data, a reliable operation can be performed.

(4) According to the invention described in claim 4, the serial / parallel conversion register can receive the next data by confirming the response signal of the data reception completion from the partner data transfer control device. By providing the means for performing the operation, the serial / parallel conversion register receives the next data after receiving the completion of the data reception from the partner data transfer control device, and can perform a reliable operation.

[Brief description of the drawings]

FIG. 1 is a principle block diagram according to claim 1;

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing one embodiment of a CCA according to the present invention.

FIG. 4 is a flowchart showing a processing operation of the present invention.

FIG. 5 is a sequence diagram showing a data transfer control operation of the present invention.

FIG. 6 is a sequence diagram showing a conventional data transfer control operation.

FIG. 7 is a block diagram showing a configuration example of a conventional CCA.

[Explanation of symbols]

 Reference Signs List 20 processor 21 memory memory 30 data transfer control device 31 buffer register 32 common I / O bus

Claims (4)

[Claims] At least one pair of systems for performing one data transfer with a main memory, a processor, and a data transfer control device is provided, and inter-processor data for transferring data between the systems via the data transfer control device. In the transfer control system, at the same time as sending data to the partner data transfer control device,
An inter-processor data transfer control system configured to request its own processor for the next data without being affected by a response signal from a partner data transfer control device. 2. A register used for serial-parallel data conversion when data transfer of the data transfer control device is performed by converting parallel data into serial data and executing the data in units of one byte according to a specified timing. 2. The inter-processor data transfer control system according to claim 1, further comprising: means for using as a buffer register. 3. The storage of data from the corresponding processor into the buffer register includes means for permitting after confirming that a response signal from the serial / parallel conversion register has been received. 2. The data transfer control system between processors according to claim 1. 4. The serial / parallel conversion register further comprises means for confirming a response signal indicating completion of data reception from a counterpart data transfer control device, thereby enabling reception of the next data. An inter-processor data transfer control system according to claim 1.