JPH06103304A - Method and circuit for digital arithmetic - Google Patents

Abstract

PURPOSE:To eliminate deviation from the result of ideal calculation by subtracting deviation generated by a 1st rounding circuit before rounding by a 2nd rounding circuit. CONSTITUTION:Four data A, B, C, and D are inputted to a 1st arithmetic circuit (multipliers 1 and 2), and two primary inner products G=AXB and H=CXD are calculated and outputted. Then, G and H are rounded by 1st rounding circuits R11 and R12 to proper word length and then inputted to a 2nd arithmetic circuit (multipliers 3 and 4 and adder 5). Four data in total, i.e., data E and F which are newly inputted from outside and output data I and J of the 1st rounding circuits R11 and R12 are used to calculate a secondary inner products M=IXE+JXF, which is outputted. An error correcting circuit 6 consists of one subtracter and subtracts the error correction quantity S from the output M of the 2nd arithmetic circuit. This subtraction value N is rounded by the 2nd rounding circuit R2 to eliminate the deviation from the result of the ideal calculation. Then P is a calculation result which is finally obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital operation method and circuit for performing rounding calculation in digital signal processing.

[0002]

2. Description of the Related Art In digital signal processing, a plurality of arithmetic processes are commonly performed. Consider, for example, performing two arithmetic processes. When this arithmetic processing is realized by an actual circuit, two arithmetic circuits are required.
That is, the first arithmetic circuits L1 and 2 for performing the first arithmetic processing
Using a second arithmetic circuit L2 for performing the third arithmetic process, connecting them in series, inputting input data to the first arithmetic circuit L1, and extracting output data from the second arithmetic circuit L2. It is realized by.

Therefore, the circuit diagram is shown in FIG. Figure 4
In, IN is an input terminal for inputting input data, and OUT is an output terminal for outputting output data. Also, in this example, the word length of the output data is generally long due to the calculation, so it is necessary to round (round off) the lower few bits and shorten the word length before outputting. It has a rounding circuit (R in the figure).

By the way, in this circuit, only one rounding circuit is provided in the final stage, and no error due to rounding is mixed in during the calculation. That is, it is an ideal arithmetic circuit.

An example of the operation shown in FIG. 4 is, for example, a two-dimensional discrete cosine transform (Discrete Cosin).
Transform (DCT) is known. That is, the first arithmetic circuit L1 may calculate the vertical one-dimensional DCT, and then the second arithmetic circuit L2 may calculate the horizontal one-dimensional DCT.

Actually, FIG. 4 cannot be said to be a circuit having a high possibility of being realized. Because the output of the first arithmetic circuit L1 is 1
The word length is lengthened by performing the third arithmetic operation, whereby the output of the first arithmetic circuit L1 is directly input to the input of the second arithmetic circuit L2. This is because the word length of the input data of becomes too long. In other words, the circuit scale of the arithmetic circuit for the data having a short input word length can be small, but the circuit scale of the arithmetic circuit for the data having a long input word length is unrealistic like the second arithmetic circuit L2 in FIG. Since it becomes so large, the circuit configuration becomes unrealizable.

Therefore, a feasible circuit as shown in FIG. 5 is often used. In FIG. 5, the first rounding circuit R1 and the second rounding circuit R2 are used in total to make the first rounding circuit R1.
The long word length data output from the arithmetic circuit L1 is rounded by the first rounding circuit R1 to the lower few bits to make a short word length.
Is input to the arithmetic circuit L2. Therefore, the input data to the second arithmetic circuit L2 becomes relatively short, and the circuit scale of the second arithmetic circuit L2 does not become large. Since the word length of the output of the second arithmetic circuit L2 is naturally extended by performing the second arithmetic operation, the second rounding circuit R2 rounds the lower few bits to the desired word length and outputs it from the output terminal OUT.

In order to describe the drawbacks of the conventional circuit configuration (FIG. 5), a specific example will be used for the following description. That is, as shown in FIG. 6, two first-order inner product operations (multipliers 1 and 2) as the first operation circuit L1 and one second inner-product operation (multipliers 3 and 4 and adder as the second operation circuit L2). The case of 5) will be described.

As input data of the first arithmetic circuit, A
(8-bit word length), B (8-bit word length), C (8-bit word length), D (8-bit word length), and four primary inner product operations G = A × B H = C XD is calculated, and G and H are output from the first arithmetic circuit. Incidentally, the first-order inner product operation is just one multiplication. G, H
Is a multiplication result of 8 bits each, and therefore has a 16-bit word length. The word lengths used in this calculation are shown in FIGS.

The outputs G and H of the first arithmetic circuit are 16
Since the bit and the word length are long, if directly input to the second arithmetic circuit, the circuit scale of the second arithmetic circuit becomes too large. Therefore, G and H are rounded to an appropriate word length (for example, 10 bits) and then input to the second arithmetic circuit. That is, the first rounding circuits R11 and R12 input I and J to the second arithmetic circuit as I = G lower 6-bit rounding and J = H lower 6-bit rounding. The word lengths used in this calculation are shown in FIGS.

Data E (8-bit word length) and F newly input from the outside as input data of the second arithmetic circuit.
(8-bit word length) and the first rounding circuits R11 and R1
The output data I and J of 2 are used as a total of four data, and a secondary inner product operation M = I × E + J × F is calculated, and M is output from the second arithmetic circuit.

Further, K = I × E and L = J × F.
Since K and L are the multiplication results of 10 bits and 8 bits, respectively, they have an 18-bit word length. Since M = K + L is the addition result of 18 bits, the word length is 19 bits. The two multipliers 3 and 4 in the second arithmetic circuit perform the calculation of (10-bit word length) × (8-bit word length). The word lengths used in this calculation are shown in FIG.

The output M of the second arithmetic circuit is rounded to a desired word length (for example, 9 bits) and then taken out as an output result. That is, the second rounding circuit R2 rounds out the lower 10 bits of Q = M and extracts Q as an output result. The word length in this calculation is shown in FIG.

For reference, if the first rounding circuit R11,
When R12 is omitted and the outputs G and H of the first arithmetic circuit are directly input to the first arithmetic circuit, the two multipliers 3 and 4 in the second arithmetic circuit are (16-bit word length) × (8 Bit word length)
Must be calculated. This would make the circuit scale of the multiplier too large. Therefore, it is necessary to shorten the word length of the output result of the first arithmetic circuit, and therefore the first rounding circuits R11 and R12 are provided.

Now, the rounding will be described in detail. For example, a binary number with three digits after the decimal point: X. YZV (X is an integer part, Y
Is the number after the decimal point is 0 or 1, Z is the number after the decimal point is 0 or 1, and V is the number after the decimal point is 0 or 1) Consider the case of outputting only.

At this time, (X-1). 100 (X-1). 101 (X-1). 110 (X-1). 111 X. 000 X. 001 X. 010 X. The eight values of 011 are all rounded to the integer X. The same applies to other values. This state is shown in FIG.

By the way, the above eight values, (X-1). 100 (X-1). 101 (X-1). 110 (X-1). 111 X. 000 X. 001 X. 010 X. The average value of 011 is {(X-1). 100} * (1/8) + {(X-1). 101} * (1/8) + {(X-1). 110} * (1/8) + {(X-1). 111} × (1/8) + {X. 000} × (1/8) + {X. 001} x (1/8) + {X. 010} x (1/8) + {X. 011} x (1/8) = (X-1). It is 0001. In this way, there is a difference of 0.0001 minutes between the rounded value and the average value in each rounding circuit.

Therefore, in the circuit shown in FIG. 6, A, B, C,
D, E, and F are given at random, and the average value of the output result Q is looked at. The value obtained by calculating [{(A × B) × E + (C × D) × F} and then rounding to 9 bits ] Is slightly deviated from the average value.

This is the first rounding circuit (R11, R12).
This is because when G and H are rounded to I and J, respectively, they deviate from the average values of G and H as described above. That is, the difference between g and h shown in FIGS.

[0020]

The problem to be solved is that the value [average value of Q] calculated by the conventional circuit configuration (FIG. 6) is the same as that of the first arithmetic circuit and the second arithmetic circuit. No rounding is performed, the circuit scale becomes unrealistic, but the ideal calculation result [{(A × B) × E + (C × D) × F} is calculated and then rounded to 9 bits. [Average value] means that there is a deviation.

[0021]

The first means of the present invention is a digital operation method in which n (n is 2 or more) rounding operations are performed in the process of operating digital data, except the first rounding operation. This is a digital operation method characterized in that the error correction amount is subtracted before all rounding operations.

According to the second means of the present invention, the error correction amount is E × g (where E is data newly input to the operation of the previous stage, g is 1 which is the minimum value of the output of the operation of the previous stage). Is a value corresponding to / 2).

The third means according to the present invention is the first rounding operation in a digital operation circuit having rounding operation circuits (R11, R12, R2) n (n is 2 or more) times in an operation process of digital data. The digital arithmetic circuit is characterized in that an error correction circuit 6 for subtracting the error correction amount is provided in the preceding stage of all the rounding arithmetic circuits except the circuits.

In a fourth means according to the present invention, the error correction amount is E × g (where E is an arithmetic circuit (multiplier 3,
4) The data newly input to g, g is a value corresponding to ½ of the minimum value of the output of the arithmetic circuit (multipliers 1 and 2) at the previous stage before the third means. It is the described digital arithmetic circuit.

[0025]

According to this, the deviation caused by the first rounding circuit is subtracted by the error correction circuit before being rounded by the second rounding circuit, thereby eliminating the deviation from the ideal calculation result. it can.

[0026]

FIG. 1 shows an embodiment of the present invention. 1 is the same as the conventional example (FIG. 6) except that an error correction circuit 6 is added, and the description thereof will be omitted to avoid duplication. The error correction circuit 6 is composed of one subtractor and is a circuit for subtracting S = E × g + F × h from the output M of the second arithmetic circuit.

Although S will be described in detail later, S is a [deviation amount] which has been a problem in the prior art. In the present invention, this [deviation amount (S)] is subtracted by the error correction circuit 6. Since the deviation can be corrected by, 9 after calculating the ideal calculation result [{(A × B) × E + (C × D) × F}
The average value of the values rounded to bits] is eliminated.

Further details of FIG. 1 will be described. Symbols A, B, C, D, E, F, G, H, I in FIG.
J, K, L, and M are the same as those described in the conventional example (FIG. 6), and the description thereof will be omitted. That is, FIG.
There is a relationship shown to mosquitoes.

Now, as described in the conventional section, FIG.
There is a mean value of G = mean value of I−g (g is a constant), and a mean value of H = mean value of J−h (h is a constant).

Therefore, the average value of (G × E) = the average value of (I × E) − (g × E)
Average value of (H × F) average value = (J × F) average value− (h × F)
Is the average value of.

Therefore, the average value of {(A × B) × E + (C × D) × F} The average value of (G × E + H × F) = {the average value of (I × E + J × F)}-{( g × E + h ×
F) average value} = {(K + L) average value}-{(g × E + h × F) average value} = {M average value}-{(g × E + h × F) average value} .

That is, without rounding between the first arithmetic circuit and the second arithmetic circuit, the circuit scale becomes unrealistic but the ideal calculation result [{(A × B) × E + (C × D) ×
The average value of the values rounded to 9 bits after calculating F}] is
It becomes equal to [average value of values rounded to 9 bits after calculating {M− (g × E + h × F)}].

In FIG. 1, [deviation from M (S = g ×
E + h × F)] is subtracted by the error correction circuit 6 (N
= M−S), the average value of N = {(A × B) × E + (C × D) × F}.

By rounding this value N to 9 bits by the second rounding circuit R2, the ideal calculation result [{(A × B)
XE + (C × D) × F} is calculated and then the average value of values rounded to 9 bits] is eliminated. Calculations in the error correction circuit 6 and the second rounding circuit R2 in the present invention are shown in FIGS. Note that P in FIGS. 1 and 2 is the calculation result finally obtained.

The value S subtracted by the error correction circuit 6 is a value that changes depending on the data E and F input from the outside, that is, S =
It may be g × E + h × F, or S = g × (average value of E) + h × (average value of F) = constant.

Further, the adder 5 and the subtractor of the error correction circuit 6 in the subsequent stage of the second arithmetic circuit may be combined and the calculation may be performed by one 3-input adder / subtractor. That is, instead of an adder for calculating M = K + L and a subtractor for calculating N = MS, N =
A three-input adder / subtractor that calculates K + LS may be used.

Thus, according to the above-described apparatus, the error correction circuit is provided before the second rounding circuit R2 rounds the shift amount (FIG. 8-C, g, h) generated by the first rounding circuits R11 and R12. By subtracting 6 (subtracting S = E × g + F × h), the ideal calculation result [{(A × B) × E +
[C × D) × F} is calculated and then rounded to 9 bits].

Further, FIG. 3 shows a generalized circuit diagram of FIG. This is just an embodiment of the present invention corresponding to the conventional example (FIG. 5).

[0039]

According to the present invention, the deviation caused by the first rounding circuit is subtracted by the error correction circuit before being rounded by the second rounding circuit, so that the deviation from the ideal calculation result can be obtained. I can now lose it.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a digital arithmetic circuit according to the present invention.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a generalized block diagram of a digital arithmetic circuit according to the present invention.

FIG. 4 is an unrealistic but ideal circuit diagram for performing two arithmetic processes.

FIG. 5 is a conventional realistic circuit diagram.

FIG. 6 is a circuit diagram of a conventional digital arithmetic circuit.

FIG. 7 is a diagram for explaining the explanation.

FIG. 8 is a diagram for explaining the explanation.

FIG. 9 is a diagram for explaining rounding.

[Explanation of symbols]

 1, 2 Multiplier that constitutes the first arithmetic circuit 3, 4 Multiplier that constitutes the second arithmetic circuit 5 Adder that constitutes the second arithmetic circuit 6 Error correction circuit (subtractor) R11, R12 1st Rounding circuit R2 Second rounding circuit

Claims (4)

[Claims] 1. A digital calculation method for performing rounding calculation n times (n is 2 or more) in a process of calculating digital data, wherein an error correction amount is subtracted in a stage before all rounding calculations except the first rounding calculation. A digital operation method characterized by the above. 2. The error correction amount is E × g (where E is data newly input to the operation of the previous stage, and g is a value corresponding to ½ of the minimum value of the output of the operation of the previous stage). The digital operation method according to claim 1, wherein 3. A digital arithmetic circuit having a rounding arithmetic circuit n times (n is 2 or more) in a digital data arithmetic process, wherein an error correction component is provided in a preceding stage of all the rounding arithmetic circuits except the first rounding arithmetic circuit. A digital arithmetic circuit characterized in that an error correction circuit for subtracting is provided. 4. The error correction amount is E × g (where E is data newly input to the arithmetic circuit of the preceding stage, g is equivalent to ½ of the minimum value of the output of the arithmetic circuit of the preceding stage). 4. The digital arithmetic circuit according to claim 3, wherein the digital arithmetic circuit is a value.