JPH06101516B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that is resistant to α rays and external noise.

[Background of the Invention]

In a conventional semiconductor device, an n-type buried layer is provided on a P-type substrate and an epitaxial layer is grown to form a transistor therein, as described in JP-A-56-1556. Was there. However, in the transistor thus formed, when α-rays enter from the outside and electron-hole pairs are generated in the p-type substrate, electrons are sucked into the buried layer and the epitaxial layer and potential fluctuations occur. Therefore, there is a problem that information is easily destroyed in the memory cell using this transistor, and a solution has been desired.

On the other hand, one of the inventors of the present invention forms a concave portion and a convex portion surrounded by the concave portion by etching a predetermined portion of the semiconductor substrate, forms an insulating film on the concave portion, and forms the insulating film on the insulating film. At the same time, by diffusing a p-type impurity in the polycrystalline silicon layer in contact with the sidewall of the convex portion, the polycrystalline silicon layer in which the p-type impurity is diffused is formed as an external base region on the insulating film, and then the insulating film is formed. An active base region and an emitter region are sequentially formed on a convex portion surrounded by the film and the polycrystalline silicon extrinsic base region by using a self-alignment technique, so that the polycrystalline silicon extrinsic base region on the insulating film is activated. A bipolar transistor capable of high-speed operation and high integration density of a so-called SICOS structure (SIde wall contact structure) connected to a base region has been proposed (JP-A-56). -1556).

[Object of the Invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned conventional problems, is resistant to external noise, and has a very low risk of occurrence of a soft error due to resistance to α rays.

Another object of the present invention is that the so-called SI
It is an object of the present invention to provide a method for manufacturing a semiconductor device that is compatible with a method for manufacturing a COS structure transistor.

[Outline of Invention]

In order to achieve the above object, a p-type diffusion layer surrounded by silicon dioxide 7 is provided between the n-type buried layer 2 and the n-type diffusion layer 13 as shown in FIG. Prevent the intrusion of electrons. In order to realize this structure, the present invention provides
After element isolation is formed, B is ion-implanted at high energy (100 to 200 KeV), and p is added between the n-type buried layer and the n-type diffusion layer.
A type diffusion layer is provided.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS. 2 to 8 based on a semiconductor device in which an electrode is taken out from a sidewall by polycrystalline Si.

First, as shown in FIG. 2, a desired portion of the surface region of the p-type Si substrate 1 was selectively doped with Sb using a well-known vapor phase diffusion technique to form an n-type buried layer 2. . After that, an n-type epitaxial layer 3 was grown, and silicon dioxide 4, silicon nitride 5, and silicon dioxide 6 were provided on the surface thereof. Then, a convex Si region was formed as shown in FIG. 3 by using the well-known photo-etching technique and dry-etching technique. Next, a well-known selective oxidation method was used to provide a silicon dioxide region 7 for element isolation (FIG. 4). further,
After depositing polycrystalline Si, using a well-known planarization technique,
As shown in the figure, polycrystalline Si 8 was flatly embedded on the silicon dioxide 7. After that, the polycrystalline Si was doped with B and heat-treated to form a p-type diffusion layer 10.
Further, by doping P into the n-type epitaxial layer 3,
An n-type diffusion layer 11 was formed (Fig. 6).

The manufacturing process from FIG. 2 to FIG.
This is the same as the method for manufacturing a COS transistor.

Incidentally, as shown in FIG. 6, the p-type diffusion layer 10 formed by the diffusion of B from the polycrystalline Si layer 8 to the n-type epitaxial layer 3 by heat treatment is originally a portion of a transistor having a SICOS structure. And has a role of reducing the connection resistance between the polycrystalline silicon external base region and the active base region.

After that, in order to provide the p-type diffusion layer 12 which is a feature of the present invention, B was selectively doped at a high acceleration energy (for example, 200 KeV) using an ion implantation technique. Continuing,
The n-type diffusion layer 13 is doped with P by using the ion implantation technique.
Was provided (FIG. 7). Next, form contact holes,
An n-type diffusion layer 14 and a silicide layer 15 (Pt silicide in this example) were provided (FIG. 8). Further, as shown in FIG. 1, the Al electrode 16 is formed to prevent external noise and α resistance.
We have realized a semiconductor device that is strong against lines (in this example, a shutter key diode).

That is, a diode formed of a Schottky barrier is formed at the interface between the n-type diffusion layer 13 and the Pt silicide layer 15.

Particularly, the n-type diffusion layer 13 in which the Schottky diode is formed is the p-type diffusion layer 10 due to the characteristics of the SICOS structure transistor and the p-type diffusion layer formed by the high acceleration energy ion implantation technology of the present invention. 12 and p-type Si
Since it is electrically isolated from the substrate 1, the Schottky diode is resistant to external noise and α rays.

As a result of making a prototype of 1Kbit bipolar memory using this semiconductor device, the maximum noise charge amount is about 1/5 of the conventional one, and the α ray resistance is improved by about 4 digits compared with the conventional memory cell. A remarkable effect was recognized.

It is needless to say that the present invention can be applied even if all the n-type and p-type conductivity types are reversed in the above embodiment.

〔The invention's effect〕

As is apparent from the above description, as a result of trial manufacture of a highly integrated bipolar memory using the manufacturing method of the present invention, external noise,
It was possible to realize a semiconductor device that is resistant to soft errors due to and α rays.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device manufactured according to the present invention, and FIGS. 2 to 8 are process sectional views for explaining a method for manufacturing a semiconductor device according to the present invention. 1 ... p-type Si substrate, 2 ... n-type buried layer, 3 ... n-type epitaxial layer, 4,6,7,9 ... silicon dioxide, 5 ... silicon nitride, 8 ... p-type poly Crystal silicon, 10,12 …… p
Type diffusion layer, 11, 13, 14 ... N type diffusion layer, 15 ... Pt silicide layer, 16 ... Al electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tokio Kure, Inventor Tokio Higashi Koigakubo 1-280, Kokubunji City, Tokyo (72) Central Research Laboratory, Hitachi, Ltd. (72) Kiyoji Ikeda 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. (72) Inventor Noriyuki Honma Noriyuki Honma 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (56) References JP 56-1556 (JP, A) JP 59-94451 ( JP, A)

Claims (3)

[Claims] 1. A step of forming a concave portion and a convex portion surrounded by the concave portion by etching a predetermined portion of a semiconductor substrate; a step of forming an insulating film on the concave portion; Forming a crystalline Si, forming a first p-type impurity region on a sidewall of the single-crystal Si of the convex portion by diffusing a p-type impurity into the polycrystalline Si; Forming a second p-type impurity region below the single-crystal Si of the convex portion by ion-implanting p-type impurities into the single-crystal Si with high acceleration energy. Production method. 2. The single crystal Si of the convex portion surrounded by the first p-type impurity region and above the second p-type impurity region is electrically isolated from the other part of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 1, wherein the second p-type impurity region is formed by the ion implantation to a depth as described above. 3. The manufacturing of a semiconductor device according to claim 2, wherein a Schottky diode is formed in the single crystal Si of the convex portion above the second p-type impurity region. Method.