JPH06101476B2 - Method for manufacturing field effect semiconductor device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a field effect semiconductor device formed on a semiconductor substrate having a structure in which a silicon thin film is formed on a single crystal silicon substrate partially covered with an insulating film. And the manufacturing method thereof.

[Conventional technology]

A field effect semiconductor device (MOSFET) having a source region and a drain region on an insulating film has a high density due to its structure.
In terms of speeding up, it is more advantageous than that using a single crystal silicon substrate. A concrete structure of such a conventional field effect semiconductor device is shown in FIG. Part of the surface of the single crystal silicon substrate 1 is covered with a relatively thick insulating film 6 made of a silicon dioxide film (first region), and silicon is formed on the first region and the uncovered portion (second region). A thin film 19 is formed, most of the source region 7 and the drain region 8 are formed in the silicon thin film 19 on the first region, and the gate oxide film 10 is formed on the surface of the silicon thin film 19 on the second region. A polysilicon gate 13 is formed, and a channel 9 is formed at the interface between the silicon thin film 19 and the gate oxide film 10. The insulating film 6 is thicker than the gate oxide film 10. In this FET, since the depletion layer regions 11 and 12 generated between the silicon substrate 1 and the source region 7 and the drain region 8 that are in direct contact with the substrate 1 are limited to very small portions, the source region 7 and the drain region 8 and the silicon substrate 1 can be significantly reduced in parasitic capacitance, and high-speed operation can be expected. Further, since the contact between the diffusion layer (source region 7 and drain region 8) and the metal electrode wiring 16 is made on the insulating film 6, the diffusion layer is bonded to the silicon substrate 1 due to the reaction between the metal and the diffusion layer. (Depletion layer regions 11 and 12 are formed at the junction)
Will not be destroyed. Furthermore, since there is no wiring area existing on the chip in the form of a diffusion layer region,
It becomes possible to arrange elements in high density. Furthermore, if a CMOS is constructed using this FET, the emitter area of the parasitic bipolar becomes extremely small, so that the injection efficiency is reduced and the latch-up resistance is improved. In addition to the above four advantages, in this FET, since the silicon thin film 19 and the silicon substrate 1 are electrically conducted under the channel region (because of the same conductivity type), the element region is completely insulated from the substrate. There is no fluctuation of the threshold voltage caused by the fluctuation of the substrate potential, which is a problem in the FET manufactured using the SOI substrate. However, in spite of having such an advantage, when the fine semiconductor device having the structure as shown in FIG. 7 is manufactured by the conventional technique, the gate electrode pattern is formed by using photolithography, so There is a drawback that it is not possible to make a fine structure.

[Object of the Invention]

An object of the present invention is to reduce the parasitic capacitance because most of the source region and the drain region are present on the entire surface or part of the surface layer on a thick insulating film made of a silicon nitride film or an insulating film containing silicon nitride as a main component. , The reliability of the contact between the diffusion layer and the electrode wiring is improved, the latch-up resistance in CMOS is improved, and the channel region is formed in good quality single crystal silicon, resulting in carrier mobility. It is to provide a manufacturing method capable of forming a fine gate electrode of the field-effect semiconductor device in a self-aligned manner, and promoting miniaturization and speeding up of the field-effect semiconductor device.

[Structure of Invention]

(A) A first feature of the present invention is that, in a MOSFET structure in which a main source region and a drain region are present on a thick insulating film, the silicon dioxide film on the insulating film is used instead of the silicon dioxide film which is conventionally used as the insulating film. All or part of the surface in contact with the thin silicon film formed on the
It is characterized in that a film which is any one of insulating films containing silicon nitride as a main component is used. Due to this feature, the surface of the thin silicon film on the insulating film becomes smooth, and the field effect semiconductor device can be made fine.

(B) The second feature of the present invention is that the surface of the thin silicon film formed on the thick insulating film becomes smooth,
At the time of forming the gate polysilicon film, a groove is formed on the gate polysilicon film on the second region where the thick insulating film does not exist thereunder, the surface of the groove becomes smooth, and a mask material such as a resist is formed in the groove. Apply so that the surface is flat,
By etching back, the edge of the mask material embedded in the groove becomes smooth. Therefore, a fine gate electrode can be formed by etching the gate polysilicon film using the mask material embedded in the groove as an etching mask.

〔Example〕

A field effect type semiconductor device according to the present invention is shown in FIG. The manufacturing method leading to it will be described in detail with reference to FIGS. In addition, the examples are some examples,
It goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.

A relatively thick insulating film (0.2 to 0.8μ) on the single crystal silicon substrate 1.
As m), a silicon nitride film 2 is formed by a chemical vapor deposition method (hereinafter referred to as a CVD method) or the like (FIG. 2 (a)). A resist 3 patterned by photolithography is formed thereon (FIG. 2 (b)). Next, using the resist as a mask, the reactive ion etching method (hereinafter referred to as RIE
Etching the silicon nitride film 2 to expose the silicon substrate 1 (FIG. 2 (c)). Here, the exposed region of the surface of the silicon substrate 1 is the second region, and the other region covered with the insulating film 2 is the first region.
After that, a thin silicon thin film 19 (0.02 to 0.3 μm) is formed by a silicon epitaxial growth method such as a CVD method using a high temperature of 700 ° C. or higher and a molecular beam epitaxy method (hereinafter referred to as MBE method).
Are formed (FIG. 2 (d)). Of the silicon thin film 19,
Since a high temperature of 700 ° C. or higher is used, a single crystal silicon thin film 4 of good quality is formed on the silicon substrate (second region). Further, since the silicon nitride film 2 whose initial nucleus density (the point at which nuclei start crystal growth) becomes large when a silicon thin film is formed is used as a relatively thick insulating film, even though a high temperature of 700 ° C. or higher is used, The surface of the single crystal silicon film 5 formed on the insulating film 2 (on the first region) becomes smooth.

The insulating film 2 has a high nucleus density in the initial stage of the formation of the silicon thin film, and other thin films containing silicon nitride as a main component (for example, Si-N system) as long as they satisfy the condition that a silicon thin film having a smooth surface can be obtained. , Si-N-O type insulating film)
It doesn't matter. Further, as shown in FIG. 3, a two-layer film (film thickness 0.2 with a silicon nitride thin film or a thin film containing silicon nitride as a main component as an insulating film is used as an upper layer 2 and a film having a low dielectric constant such as silicon dioxide is used as a lower layer 6. .About.0.8 .mu.m), the parasitic capacitance between the polycrystalline silicon film 5 and the silicon substrate 1 can be reduced, which is advantageous for speeding up the operation of the field effect semiconductor device formed on the silicon thin film 19. . Further, since the difference in the coefficient of thermal expansion between silicon dioxide and silicon is smaller than that of the silicon nitride film, the use of the above-mentioned two-layer film causes a large difference in coefficient of thermal expansion between the silicon nitride film 2 and the silicon substrate 1 to cause slippage in the silicon substrate. It is possible to mitigate various obstacles such as lattice defects such as, defects such as cracks generated in the insulating film.

However, if the film thickness of the silicon dioxide film 6 is increased in order to further reduce the parasitic capacitance in the structure of FIG. 3, the nucleus density in the initial process of the silicon thin film formation on the sidewalls of the silicon dioxide film 6 will decrease and the silicon thin film will slip. There is a problem that it is not formed. FIG. 4 shows a structure for solving this problem. First, an insulating film having a thin silicon nitride film 2 as an upper layer and a thick film 6 having a low dielectric constant such as silicon dioxide as a lower layer is formed by photolithography and RIE as in the case of FIG.
Then, the silicon substrate 1 is exposed by the method (FIG. 4 (a)). After that, the exposed silicon substrate 1 is slightly oxidized to form a thin oxide film (not shown) on the surface of the silicon substrate 1. Next, a thin silicon nitride film 2'is formed again (FIG. 4 (b)), and the silicon nitride film 2, 2'is formed by the RIE method or the like.
Anisotropic etching is performed on the silicon substrate 1 to remove the thin oxide film (which prevents the surface of the silicon substrate from being etched during the anisotropic etching) to expose the silicon substrate 1 and the insulating film 6 such as silicon dioxide. A structure with a frame of silicon nitride 2'is formed on the side wall of (Fig. 4 (c)), and then a silicon thin film 19 is formed by the CVD method or MBE method using a high temperature of 700 ° C or higher. The structure of d) is obtained. Here, in the silicon thin film 19, 5 is on the first region and 4 is on the second region. In the structure of FIG. 4, the surface of the formed silicon thin film is sufficiently smooth even on the side wall of the insulating film.

Subsequently, the surface of the silicon thin film 19 is oxidized and a mask material (for example, a silicon oxide film or a silicon nitride film) for determining a region to be an element is deposited on the entire surface. Silicon thin film 19
For processing, the mask material is first processed by using lithography and dry etching to determine the element region.
At this time, the device region (that is, the channel region 61 and the source
Drain diffusion layer region 62) and other element isolation regions 63
The relationship between the gate electrode lead-out region 64 and the plane is shown in FIG. The thick insulating film 6 is under most of the source / drain diffusion layer region 62 and under the element isolation region 63. The region with the thick insulating film is the first region, and the region without the thick insulating film is the second region. A boundary 65 between the first area and the second area is shown by a broken line in FIG. Then, the silicon thin film 19 is etched by dry etching to leave only the element regions (61, 62) and separate the different element regions from each other. At this time, the silicon thin film 19 has no surface roughness due to grain growth and has a smooth surface. Next, a gate electrode polysilicon film 13 and a silicon substrate 1 to be formed later.
The gate electrode lead-out region 64 is oxidized to insulate the electrodes. Here, the gate electrode lead-out region 64 and the channel region 61 are all in the second region. Alternatively, selective oxidation is performed using the mask material formed on the element region as a mask (in this case, a silicon nitride film having oxidation resistance can be used as the mask material) to separate the element region and the gate electrode lead-out region 64. Oxidize. After that, the mask material is removed and gate oxidation is performed to form a thin gate oxide film 10 on the surface of the silicon thin film 19, and then a polysilicon film 13 'for a gate electrode is deposited. After depositing the polysilicon film 13 'for the gate electrode, a thick resist is applied, the surface is flattened, and then etch back is performed, so that as shown in FIG. A resist is buried in the groove 21 existing in the region 2 to form the gate electrode pattern 3 made of the resist. These electrode patterns 3 are evenly spaced from the boundary of the second region 65 (polysilicon film 1
The pattern becomes smaller by about 1 by the film thickness of 3 '+ the film thickness of the silicon thin film 19). Then, the polysilicon 13 'is etched with high precision by using the ECR plasma etching method to form the gate electrode 13 made of polysilicon (Fig. 6 (b)), and the resist 3 is removed (Fig. 6 (c). )). Since the surface of the silicon thin film 19 is smooth, the end portion of the gate electrode 13 becomes linear due to the formation of this self-aligned gate electrode, and a fine gate electrode having no variation in the channel length within the gate is formed. it can.

After that, the surface of the gate polysilicon electrode 13 is oxidized.
At this time, at the same time, the thick insulating film 6 that should become the diffusion layers 7 and 8 is formed.
The surface of the upper polysilicon is also oxidized (the oxide film is not shown). However, polysilicon (source,
The thickness of the oxide film on the drain regions 7 and 8) is the gate polysilicon that is heavily doped with impurities that causes accelerated oxidation.
13 is thinner than the oxide film 14 on the surface. Subsequently, ion implantation and annealing for source / drain formation are performed. Thereafter, the oxide film on the source / drain regions 7 and 8 (diffusion layers) is removed by etching to expose the silicon on the surfaces of the diffusion layers 7 and 8. At this time, the oxide film 14 remains on the surface of the gate electrode polysilicon 13. Next, tungsten is selectively grown on the exposed silicon or the exposed silicon layer is silicidized to form a tungsten or silicide film 18 to reduce the resistance of the diffusion layer. Thereafter, the trenches 21 'existing on both sides of the gate polysilicon 13 are filled by depositing an interlayer film or a passivation film 15, and the surface after depositing the interlayer film or the passivation film 15 is flattened. Next, a contact hole is formed in the interlayer film or the passivation film 15, and a metal for electrode wiring is formed.
Forming 16. The shape of the final cross section is shown in FIG.

[Explanation of effects]

As described above, in the present method, a silicon nitride film or a film containing silicon nitride as a main component is used as a thick insulating film or a thick insulating film because the nucleus density in the initial process of forming a silicon thin film is large and thus a silicon film having a smooth surface can be obtained. Since it is used as a layer on the surface of the film, the silicon thin film is grown on the entire surface under the condition that a good-quality epitaxial single crystal thin film is grown on the second region not covered with the thick insulating film. A smooth polycrystalline silicon film can be formed on the thick insulating film in the region (3) and can be linearly formed in the end portion of the gate electrode in a self-aligning manner in the subsequent process. As a result, it is possible to form a fine gate electrode (gate electrode having a channel length of submicron or less) without variation in channel length within the gate.

Furthermore, after processing the gate polysilicon, the trenches present on both sides of the gate can be filled by depositing an interlayer film or a passivation film, and the surface after depositing the interlayer film or the passivation film can be flattened.

Since the main source and drain regions of the MOSFET thus manufactured are separated from the silicon substrate by a thick insulating film, the parasitic capacitance of the source and drain is small.
High reliability of contact between diffusion layer and metal wiring,
In addition to the general feature of high latch-up resistance in CMOS, the channel region is made of single-crystal silicon with good quality, so the carrier mobility is high and the thin silicon film covering the thick insulating film is used. Since the surface is smooth,
It has an advantage that a fine gate electrode can be formed in a self-aligned manner with high processing accuracy, and can achieve further miniaturization and higher speed than conventional MOSFETs.

[Brief description of drawings]

FIG. 1 is a field effect semiconductor device according to the present invention, FIGS. 2 to 4 are process drawings for explaining a manufacturing method according to the present invention, and FIG. 5 is a layout for explaining an element region and a gate electrode according to the present invention. FIG. 6 is an embodiment relating to the manufacturing method following FIG. 2 of the present invention, and FIG. 7 is an example of prior art. 1: Single crystal silicon substrate, 2, 2 ′: Silicon nitride film or insulating film containing silicon nitride as a main component, 3: Resist, 4:
Single crystal silicon thin film, 5: Silicon thin film, 6: Silicon dioxide film, 7: Silicon thin film (source region), 8: Silicon thin film (drain region), 9: Single crystal silicon thin film (channel region), 10: Gate oxide film , 11: source depletion layer, 12: drain depletion layer, 13: polysilicon gate, 13 ': polysilicon thin film, 14: silicon oxide, 15: interlayer film or passivation film, 16: metal for electrode wiring, 18: tungsten or Silicide film, 19: Silicon thin film, 21, 21 ': Groove, 2
2: contact hole, 61: channel region, 62: source / drain region, 63: element isolation region, 64: gate electrode lead-out region, 65: boundary between the first region and the second region.

Claims (1)

[Claims] 1. A first region, which is entirely or partially covered by a thick insulating film made of a silicon nitride film or an insulating film containing silicon nitride as a main component, on a semiconductor substrate, and a first region which is not covered. Forming a second region, and epitaxially growing a single crystal thin film having the same crystal orientation as the substrate on the second region, and at the same time forming a thin semiconductor layer on the entire surface to form a thin semiconductor layer on the first region. Most of the source region and the drain region are formed in the semiconductor layer, and subsequently, a polysilicon film for a gate electrode is deposited, and then a mask material is filled in the groove existing on the surface of the second region. Forming a channel region on the surface of the thin semiconductor layer on the second region by etching using the buried mask material as an etching mask. Method for producing effect semiconductor device.