JPH0595056A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0595056A JPH0595056A JP25375891A JP25375891A JPH0595056A JP H0595056 A JPH0595056 A JP H0595056A JP 25375891 A JP25375891 A JP 25375891A JP 25375891 A JP25375891 A JP 25375891A JP H0595056 A JPH0595056 A JP H0595056A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- resin
- chip
- outer lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のパッケージ
構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package structure.
【０００２】[0002]
【従来の技術】従来の半導体装置は、図２に示すよう
に、ダイパッド４上に搭載されたＩＣチップ５は、各リ
ード端子２にボンテ゛ィングワイヤー３で電気的接続を
とり、樹脂１でモールドしていた。その後ハンダメッキ
を行い、リードをフォーミングしていた。図３は従来の
半導体装置の電気特性試験時の説明である。半導体装置
の上部より負荷をかけることにより、プローバーの外部
端子１２と半導体装置の外部端子リード２を接触させ電
気特性試験を行っていた。2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 2, an IC chip 5 mounted on a die pad 4 is electrically connected to each lead terminal 2 with a bonding wire 3 and molded with a resin 1. Was there. After that, solder plating was performed to form the leads. FIG. 3 is an explanation at the time of the electrical characteristic test of the conventional semiconductor device. By applying a load from the upper part of the semiconductor device, the external terminal 12 of the prober and the external terminal lead 2 of the semiconductor device are brought into contact with each other to perform an electrical characteristic test.
【０００３】[0003]
【発明が解決しようとする課題】しかし、前述の従来技
術では、外部リードを加工した後わずかな外部力で容易
に変形し、ハンダ付性が低下するという問題点があっ
た。すなわち、電気特性試験時において半導体装置の外
部端子リード２とプローバーの外部端子１２とが接触
し、このとき上部から負荷がかかりリード２が変形しや
すい。また、収納容器への搬送時も、電気特性試験時と
同様にリード変形やハンダ付性の低下があった。However, the above-mentioned conventional technique has a problem in that after the external leads are processed, they are easily deformed by a slight external force and the solderability is deteriorated. That is, during the electrical characteristic test, the external terminal lead 2 of the semiconductor device and the external terminal 12 of the prober come into contact with each other. In addition, during transportation to a storage container, lead deformation and solderability were reduced as in the electrical characteristic test.
【０００４】また、半導体装置の熱抵抗が非常に高いと
いう問題点があった。すなわち、ＩＣチップから発生し
た熱は、外部端子リード２及び樹脂１を通じ外部に放散
される。しかし、従来の半導体装置では樹脂１の熱伝達
性が悪く、熱抵抗は非常に高かった。There is also a problem that the thermal resistance of the semiconductor device is very high. That is, the heat generated from the IC chip is dissipated to the outside through the external terminal lead 2 and the resin 1. However, in the conventional semiconductor device, the heat transfer property of the resin 1 was poor, and the thermal resistance was very high.
【０００５】本発明は、このような問題点を解決するも
ので、その目的とするところは、半導体装置の電気特性
試験時及び、収納容器への搬送時におけるリードの変形
とハンダ付性の低下を防ぎ、さらに半導体装置の熱抵抗
を下げることを目的とする。The present invention solves such a problem, and its object is to reduce the deformation of the leads and the solderability during the electrical characteristic test of the semiconductor device and during the transportation to the storage container. It is an object of the present invention to prevent the above and further reduce the thermal resistance of the semiconductor device.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体素子をリードフレームに搭載し、前記半導体素子
と各リード端子をワイヤーボンテ゛ィングにて接続し、
樹脂でモールドした半導体素子において、リードフレー
ムの半導体素子側、及びリードフレームの半導体素子部
の裏側を、リードの一部が露出するような溝をもつ形状
に、樹脂でモールドしたことを特徴とする。The semiconductor device of the present invention comprises:
The semiconductor element is mounted on a lead frame, and the semiconductor element and each lead terminal are connected by wire bonding,
The semiconductor element molded with resin is characterized in that the semiconductor element side of the lead frame and the back side of the semiconductor element portion of the lead frame are molded with resin into a shape having a groove so that a part of the lead is exposed. .
【０００７】[0007]
【作用】本発明によれば、リードフレームの半導体素子
搭載側、及びその裏側をリードの一部が露出するような
溝をもつ形状に、樹脂でモールドしたことにより、半導
体装置の熱抵抗を下げる。According to the present invention, the semiconductor element mounting side of the lead frame and the back side thereof are molded with resin into a shape having a groove so that a part of the lead is exposed, thereby reducing the thermal resistance of the semiconductor device. .
【０００８】半導体装置収納時においては外部端子リー
ドはトレーに接触しない。また、電特性試験時も同様
に、外部端子リードにプローバーの外部端子が接触する
ことはないので変形やハンダのはがれを防ぐことができ
る。The external terminal leads do not come into contact with the tray when the semiconductor device is stored. Similarly, during the electrical characteristic test, since the external terminal of the prober does not come into contact with the external terminal lead, deformation and peeling of solder can be prevented.
【０００９】[0009]
【実施例】図１は本発明の実施における断面図である。
ＩＣチップ５はダイパッド４上に搭載されており外部リ
ード２とボンテ゛ィングワイヤー３で接続されている。
樹脂１は、ＩＣチップ５とダイッパッド４、及び外部リ
ード２のＩＣチップ搭載側と裏側を、リードの一部が露
出するような溝１４をもつ形状に、樹脂でモールドして
いる。このような構成においてＩＣチップ５から発生し
た熱は樹脂１や外部リード２を熱伝導して外気に拡散さ
れるので熱抵抗は低下する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view in the practice of the present invention.
The IC chip 5 is mounted on the die pad 4 and is connected to the external leads 2 by the bonding wire 3.
The resin 1 is formed by molding the IC chip 5, the die pad 4, and the IC chip mounting side and the back side of the external lead 2 into a shape having a groove 14 such that a part of the lead is exposed. In such a structure, the heat generated from the IC chip 5 is conducted to the resin 1 and the external leads 2 and diffused to the outside air, so that the thermal resistance is lowered.
【００１０】図４は本発明の半導体装置の電気特性試験
時の説明である。ダイパッド４上に搭載されたＩＣチッ
プ５と外部リード２をボンテ゛ィングワイヤー３で接続
し、樹脂１で部分的にモールドする。そして、電気特性
試験をするためモールドしない部分の外部リード２にピ
ン１０に押し当てる。このときバネ１１により、押し圧
が調整されリード部のハンダのはがれや変形を防ぐ。FIG. 4 is an explanation of the semiconductor device of the present invention during the electrical characteristic test. The IC chip 5 mounted on the die pad 4 and the external lead 2 are connected by the bonding wire 3, and the resin 1 is partially molded. Then, in order to perform an electrical characteristic test, the pin 10 is pressed against the external lead 2 which is not molded. At this time, the pressing force is adjusted by the spring 11 to prevent peeling or deformation of the solder of the lead portion.
【００１１】図５は本発明の半導体装置のモールド時の
説明である。７は上型、８は下型で、上型、下型ともに
突起が付いている。樹脂はゲート９を通過してモールド
されるが、このとき、モールド用金型（上部）と（下
部）には凸部があるため、外部リード端子２が外部に突
出される。FIG. 5 is an illustration of the semiconductor device of the present invention during molding. 7 is an upper mold, 8 is a lower mold, and both the upper mold and the lower mold have projections. The resin passes through the gate 9 and is molded. At this time, since the molding dies (upper part) and (lower part) have convex portions, the external lead terminals 2 are projected to the outside.
【００１２】図６は本発明の半導体装置の収納時を示し
たものである。半導体装置の上部と下部の凹部のうち下
部の凹部をトレイ６の凸部分で固定する。このときトレ
イ６の凸部分が半導体装置の全体の負荷を指示する。こ
のため、トレイ６の収納時に、半導体装置がトレイ内で
振動しても外部リード端子２が、トレイ６にぶつかり変
形することはない。FIG. 6 shows the semiconductor device of the present invention when stored. The lower recess of the upper and lower recesses of the semiconductor device is fixed by the protruding portion of the tray 6. At this time, the convex portion of the tray 6 indicates the entire load of the semiconductor device. Therefore, when the tray 6 is stored, even if the semiconductor device vibrates in the tray, the external lead terminals 2 do not hit the tray 6 and deform.
【００１３】[0013]
【発明の効果】以上に述べたように、本発明によれば、
リードフレームの半導体素子搭載側、及びその裏側を部
分的に樹脂でモールドしたことにより、半導体装置の熱
抵抗を下げる。As described above, according to the present invention,
The semiconductor element mounting side of the lead frame and the back side thereof are partially molded with resin to reduce the thermal resistance of the semiconductor device.
【００１４】半導体装置収納時においては外部端子リー
ドはトレー接触しない。また、電気特性試験時も同様
に、外部端子リードにプローバーの外部端子が接触する
ことはないので変形やハンダのはがれを防ぐことができ
る。The external terminal leads do not come into contact with the tray when the semiconductor device is stored. Similarly, during the electrical characteristic test, since the external terminal of the prober does not come into contact with the external terminal lead, deformation and peeling of solder can be prevented.
【図面の簡単な説明】[Brief description of drawings]
【図１】 本発明の半導体装置のー実施例を示す図。FIG. 1 is a diagram showing an embodiment of a semiconductor device of the present invention.
【図２】 従来の半導体装置を示す図。FIG. 2 is a diagram showing a conventional semiconductor device.
【図３】 従来の電気特性試験時を示す図。FIG. 3 is a diagram showing a conventional electrical characteristic test.
【図４】 本発明の電気特性試験時を示す図。FIG. 4 is a diagram showing an electric characteristic test of the present invention.
【図５】 本発明のモールド時を示す図。FIG. 5 is a diagram showing a molding time of the present invention.
【図６】 本発明の半導体装置の収納時を示す図。FIG. 6 is a diagram showing a state in which the semiconductor device of the present invention is stored.
１． 樹 脂 ２． 外部端子リード ３． ボンテ゛ィングワイヤー ４． ダイパッド ５． ＩＣチップ ６． トレイ ７． モールド用金型（上部） ８． モールド用金型（下部） ９． ゲート １０． ピ ン １１． バ ネ １２． プローバーの外部端子 １３． 基 板 １４． 溝 1. Resin 2. External terminal lead 3. Bonding wire 4. Die pad 5. IC chip 6. Tray 7. Mold for molding (top) 8. Mold for molding (bottom) 9. Gate 10. Pin 11. Panel 12. External terminal of prober 13. Base plate 14. groove
Claims (1)
記半導体素子と各リード端子をワイヤーボンテ゛ィング
にて接続し、樹脂でモールドした半導体素子において、
リードフレームの半導体素子側、及びリードフレームの
半導体素子部の裏側を、リードの一部が露出するような
溝をもつ形状に、樹脂でモールドしたことを特徴とする
半導体装置。1. A semiconductor element in which a semiconductor element is mounted on a lead frame, the semiconductor element and each lead terminal are connected by wire bonding, and which is molded with resin,
A semiconductor device, wherein the semiconductor element side of the lead frame and the back side of the semiconductor element portion of the lead frame are molded with resin into a shape having a groove so that a part of the lead is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25375891A JPH0595056A (en) | 1991-10-01 | 1991-10-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25375891A JPH0595056A (en) | 1991-10-01 | 1991-10-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0595056A true JPH0595056A (en) | 1993-04-16 |
Family
ID=17255736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25375891A Pending JPH0595056A (en) | 1991-10-01 | 1991-10-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0595056A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
-
1991
- 1991-10-01 JP JP25375891A patent/JPH0595056A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
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