JPH0594496A - Wiring processing system - Google Patents

Abstract

PURPOSE:To obtain a wiring result of the small skew of a clock network by wiring to a terminal on the side of load in a position which is the fartest from a terminal on the side of a source within the clock network based on connection information of the clock network and a terminal position within the clock network on a wiring area. CONSTITUTION:First of all, a clock network detecting means 103 detects the clock network logical connection information 108. Next a main wiring means 104 wires to one of the terminals 206 on the side of the load in the position which is phisically the farthest on a branch line area means 110 from the terminal NO1 on the side of the source of a clock driver 201 within the clock network based on the each terminal position within the clock network obtained from the branch line area means 110. Thus, a main route 211 is obtained and written into the branch line area means 110. Similarly, a relay point detecting means 105 and a branch wiring means 106 repeat branch-line wiring to the remaining terminal on the side of the load as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring processing method for LSI, PWB and the like.

[0002]

2. Description of the Related Art Conventionally, in this type of wiring processing method, it is common to carry out wiring processing based on only logical connection information indicating a connection relationship between terminals without paying attention to clock skew of a clock net. there were. When it is necessary to reduce (be aware of) clock skew, the wiring pattern of the clock net is manually created prior to the wiring of other nets (reference: CAD Information Processing Society of Japan, Showa 56). Issued March 20, 2012).

[0003]

However, in the above-described conventional wiring processing method, since wiring is performed only according to the logical connection information, the clock skew of the clock net with the skew limitation becomes large and the constraint is not satisfied. Has the drawback that it may not work properly.

Further, even when the wiring pattern of the clock net for which the clock skew needs to be reduced is manually created, there is a disadvantage in that the work requires a great number of man-hours, and particularly with the increase in the scale of the circuit. Since those clock nets also tend to increase, the number of man-hours is also rapidly increasing accordingly.

Therefore, in view of the above-mentioned drawbacks, a technical object of the present invention is to provide a wiring processing method for obtaining a wiring result with a small skew of the clock net.

[0006]

According to the present invention, a clock is a net connection of a clock system in which the skew specified by at least one of the designation of the name of the clock driver and the designation of the net name must be reduced. Main line wiring means for performing wiring from the source side terminal in the clock net to the load side terminal located farthest based on the connection information of the net and the position of the terminal in the clock net on the wiring area; At least one point on the wiring path of the branch line where wiring is already completed, the path length of one stroke from the terminal on the source side to that point and the distance from the terminal on the load side where wiring is not completed to that point And a relay point detecting means for determining a point whose sum is equal to the main line length as a relay point of the wiring, and the relay point and a target for determining the relay point. Wire processing method characterized in that it has a branch line means for interconnection between the de-side terminals can be obtained.

Further, according to the present invention, a clock net which is a net connection of a clock system for which the skew specified by at least one of the designation of the name of the clock driver and the designation of the net name is required to be detected is detected. Based on the clock net detection means, the connection information of the clock net, and the position of the terminal in the clock net on the wiring area, the position farthest from the output terminal of the clock driver which is the terminal on the source side in the clock net. At a point on a wiring path of a trunk line that is a wire other than the trunk line and a trunk line that has already been wired, and a trunk line wiring means that performs a trunk line that is a wire to a clock input terminal that is a load side terminal. The length of the stroke from the terminal on the source side to that point in one stroke and the distance from the terminal on the load side where wiring is not completed to that point A relay point detecting means for obtaining a relay point of the wiring between the terminal on the load side and the routed trunk line and the branch line which are already wired in the net and the point where the sum of the tongue length becomes equal to the trunk line length, A wiring processing method is provided, which comprises branch line wiring means for wiring between the relay point obtained by the relay point detection means and the load side terminal from which the relay point is obtained.

Further, according to the present invention, at least one of input means for inputting connection information between blocks and a wiring area reflecting the placement result of the blocks, and designation of a clock driver name and a net name. Based on the connection information of the clock net and the terminal position in the clock net on the wiring area, which detects the clock net which is the clock net connection that needs to reduce the skew specified by A trunk line wiring means for wiring a trunk line which is a wire from an output terminal of a clock driver, which is a terminal on the source side in the clock net, to a clock input terminal, which is a terminal on the load side, which is the farthest position; Also, from the terminal on the source side at a point on the wiring path of a branch line that is a wiring other than the main line that has already been wired And the terminal on the load side for which the sum of the path length of one stroke and the Manhattan length which is the distance from the terminal on the load side where wiring is not completed to the point is equal to the main line length. A relay point detecting means to be obtained as a relay point of the wiring with the already-routed main line and branch line which are already wired in the net, the relay point obtained by the relay point detecting means, and the load side which is the object to obtain the relay point. It is possible to obtain a wiring processing method characterized by having branch line wiring means for wiring between terminals.

That is, according to the wiring processing method of the present invention, the input means for inputting the wiring area reflecting the connection information between the blocks and the layout result of the blocks so that the wiring pattern of the clock net with a small clock skew can be obtained. And a clock net detecting means for detecting a clock net for which the skew specified by the designation of the clock driver or the designation of the net name needs to be reduced, and the connection information of the clock net detected by the clock net detecting means. Based on the terminal position in the clock net in the wiring area and the terminal on the load side (clock input such as F / F) farthest from the source side terminal (clock driver output terminal) in the clock net. Main line wiring means for wiring up to terminals) (hereinafter referred to as main line) At the point on the wiring path of the branch line (wiring other than the main line) where wiring has already ended, the path length of one stroke from the terminal on the source side to that point and the terminal on the load side from which wiring has not ended to that point Relay point detection means that finds a point at which the sum of distances (Manhattan length) is equal to the trunk length as a relay point for the wiring between the target load side terminal and the existing wiring in the net (routed trunk and branch lines) A branch line wiring means for wiring between the relay point obtained by the relay point detection means and the load side terminal for which the relay point is obtained, an output means for outputting a wiring result, and And control means for controlling the means.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a wiring processing system according to an embodiment of the present invention, which obtains a wiring result with a small skew of a clock net.

In the logical connection relationship as shown in FIG.
A block 201 in which the net 209 is a clock driver
From the source side terminal N01 (clock terminal) to block 2
No. 02-208 load side terminals H02-H08
A case will be described below as an example where the clock net has a strict skew limitation that requires a small difference in the wiring lengths.

Block 2 by an automatic placement program or the like
It is assumed that 02 to 208 are arranged as shown in FIG. Here, for simplification, it is assumed that the blocks have the same physical size.

In the conventional method, the wiring path 210 as shown in FIG. 4 is obtained by wiring each terminal in the clock net 209 in the shortest path without paying attention to the source and the load. The vertical and horizontal lengths of 1 square in the figure are both 1.
In this wiring result, the source side terminal N0
The path length of the shortest path from 1 to the load side terminal H08 of the block 208 is 10, and the path length of the longest path from the source side terminal N01 to the load side terminal H04 of the block 204 or the load side terminal H06 of 206 is 24.

The approximate values of the delay time are 10α,
The difference is 24α (α is a constant), and the difference is the clock skew, which is 14α. If the clock skew limit is tight, this skew value is not always satisfactory.

In the wiring processing system of the present invention, first, the input means 102 shown in FIG. 1 designates the logical connection information 108 of the target circuit of this embodiment, the name and designation of the clock driver, or the designation of the lock net name. The lock net designation information 109 and the wiring area information 110, which is information on physical positions of respective terminals in a logical connection state and obstacles, are received.

Next, based on the clock net designation information 108 that needs to reduce the clock skew by designating the name of the clock driver or the designation of the net name, the clock net detecting means shown in FIG. The clock net 209 shown in FIG. 2 is detected from the logical connection information 108 by 103, and then, based on the position of each terminal in the clock net obtained from the wiring area information 110, the main wiring shown in FIG. The means 104 is the source side terminal N01 of the clock driver 201 in the clock net.
From the wiring area information 110, the wiring is physically performed to one of the load side terminals 206 located at the most distant position, and the main route 211 as shown in FIG. Written.

Next, assuming that H05 of the block 205 is selected as the load side terminal to be wired, as shown in FIG.
By the relay point detection means 105 shown in FIG.
0 on the main route path 211 from the terminal N01 on the source side to the point (18 in the figure) and the Manhattan length from the terminal H05 on the load side to the point ( A point at which the sum of 6) in the figure becomes equal to the trunk wiring path length (24 in the figure) is obtained as the relay point 212 shown in FIG.

Next, the branch line wiring means 106 shown in FIG. 1 performs wiring between the terminal H05 on the load side and the relay point 212 to obtain the branch line path 213 shown in FIG.

Next, assuming that H04 of the block 204 is selected as the load side terminal to be wired, the relay point detecting means 105 shown in FIG. 1 similarly determines the points on the trunk route 211 and the branch route 213. Source side terminal N
The sum of the one-stroke path length from 01 to the point and the Manhattan length from the load-side terminal H04 to be wired to that point is equal to the trunk wiring path length (24 in the figure). The relay point 214 is obtained as shown in FIG. 7, and the branch line wiring means 106 shown in FIG. 1 performs wiring between the terminal H04 on the load side and the relay point 214 to obtain the branch line path 215 shown in FIG. Be done.

Similarly, for the remaining terminals H02, H03, H07, H08 on the load side in the clock net 209, the relay point detection means 105 and the branch line wiring means 106 relay points shown in FIG. -By repeating branch line wiring between the terminals on the load side, the relay point 21 shown in FIG.
7, 219, 218, 216 and branch line paths 221, 22
3,222,220 is required.

As described above, when all the trunk lines and branch lines in the clock net are obtained, a wiring route 224 with a small clock skew of the target clock net is obtained as shown in FIG.

In this wiring result, the path lengths of the paths from the source side terminal N01 to all the load side terminals H02 to H08 of all the load side blocks 202 to 208 are equal to 24, and the delay time is approximated. Since all the values are 24α, the clock skew is 0. Output means 10
Reference numeral 7 is a means for externally outputting the wiring results of these clock nets in order to pass them to the layout design phase. In addition, the control means 101 is the above-mentioned means 102-1.
It is a means for controlling the execution procedure of 07.

[0024]

As described above, the present invention has an effect that the wiring result of the clock net which satisfies the circuit constraint of small clock skew can be automatically obtained. That is, it is effective in reducing the clock skew, which is indispensable for shortening the clock cycle as the circuit speed increases in the future.

Further, there is an effect of eliminating man-hours in manually creating a wiring pattern of a clock net which needs to reduce clock skew which tends to increase with the increase in scale of the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a wiring processing method for obtaining a wiring result with a small skew of a clock net according to an embodiment of the present invention.

2] Blocks 201 to 208 and their load-side terminals H
01-H08, source-side terminals N01-N08, and net 209, the block 201 represents a clock driver.
Represents a constrained clock net that requires a small skew.

FIG. 3 is a block 202 of an automatic placement program or the like.
This is an example in which ~ 208 are arranged. Here, for simplification, it is assumed that the blocks have the same physical size.

FIG. 4 is an example 210 of a wiring route obtained by using the conventional method to route each terminal in the clock net 209 in the shortest route without being aware of the source and the load.

FIG. 5 is a wiring processing method of the present invention, in which the main wiring means 104 shown in FIG.
2 is an example 211 of a main route obtained by wiring from one source side terminal N01 to one of the load side terminals 206 located at the farthest position.

FIG. 6 is a wiring processing method of the present invention, in which the load side terminal H05
In contrast, the relay point 212 obtained by the relay point detecting means 105 shown in FIG. 1 and the branch line wiring means 106 shown in FIG.
This is an example 213 of a branch line path obtained by wiring between the load-side terminal H05 and the relay point 212.

FIG. 7 is a wiring processing method of the present invention, in which the load side terminal H04
In contrast, the relay point 214 obtained by the relay point detection means 105 shown in FIG. 1 and the branch line wiring means 106 shown in FIG.
This is an example of a branch line path 215 obtained by performing wiring between the terminal H04 on the load side and the relay point 214 by.

FIG. 8 is a wiring processing method of the present invention, in which the load side terminal H0
2, H03, H07, H08, the relay points 217, 21 obtained by the relay point detecting means 105 shown in FIG.
9, 218, 216 and branch line wiring means 106 shown in FIG.
Load side terminals H02, H03, H07, H08
And branch points 217, 219, 218, and 216, and examples of branch line paths 221 and 22 obtained by each wiring
3,222,220.

FIG. 9 is an example 224 of a wiring path having a small clock skew of a target clock net obtained by the wiring processing method of the present invention. In this wiring result, the clock skew is 0.

Claims (3)

[Claims] 1. Connection information of a clock net which is a net connection of a clock system for which a skew specified by at least one of designation of a name of a clock driver and designation of a net name is required to be small and a wiring area in a wiring area. Based on the terminal position in the clock net, a trunk wiring means for wiring from the source-side terminal in the clock net to the load-side terminal in the farthest position, and at least the trunk line and the branch line that has already been wired. At either point on the wiring path, the sum of the length of the path from the source side terminal to that point in a single stroke and the distance from the unfinished wiring side load side terminal to that point becomes equal to the main line length. A relay point detecting means for obtaining such a point as a relay point of the wiring, and a branch line for wiring between the relay point and the load side terminal for which the relay point is obtained. Wire processing method characterized in that it has a line unit. 2. A clock net detecting means for detecting a clock net which is a net connection of a clock system for which the skew specified by at least one of the designation of the name of the clock driver and the designation of the net name is required, Based on the connection information of the clock net and the terminal position in the clock net on the wiring area, the terminal on the load side located farthest from the output terminal of the clock driver which is the terminal on the source side in the clock net. At a point on the wiring path of a trunk line that is a wire other than the trunk line and a trunk line that has already been wired, from the source side terminal The sum of the one-stroke path length to the point and the Manhattan length, which is the distance from the terminal on the load side where wiring is not completed to that point, is the front. A relay point detecting means for determining a point that is equal to the length of the main line and a relay point of the wiring between the terminal on the load side and the main line and branch line already wired in the net, and the relay point detecting means. A wiring processing method, characterized in that it has a branch line wiring means for wiring between the relay point and the terminal on the load side which is the target of the relay point. 3. The skew specified by at least one of the input information for inputting the connection information between the blocks and the wiring area reflecting the placement result of the block, and the designation of the clock driver name and the net name is provided. A clock net detection unit that detects a clock net that is a clock-system net connection that needs to be made small, and a clock net detection unit that detects a clock net in the clock net based on the connection information of the clock net and the position of the terminal in the clock net on the wiring area. A trunk line wiring means for wiring a trunk line which is a wire from the output terminal of the clock driver which is the terminal on the source side to the clock input terminal which is the terminal on the load side which is the farthest position, and the trunk line and the wiring already completed. A point on the wiring path of a branch line that is a wire other than the main line from the terminal on the source side to that point Is the terminal on the load side and the existing wiring in the net for the point where the sum of the path length of the above and the Manhattan length, which is the distance from the terminal on the unfinished wiring side to the point, is equal to the main line length. A relay point detecting means to be obtained as a relay point of the wiring to the main line and the branch line already wired, and wiring between the relay point obtained by the relay point detecting means and the load side terminal from which the relay point is obtained Wiring processing method characterized by having branch line wiring means for carrying out.