JP2685566B2 - Wiring design method for semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a method for designing a semiconductor integrated circuit device,
For example, the present invention relates to a technology effectively used for a method of designing a full custom LSI (large scale integrated circuit) for a specific application.

[Conventional technology]

For LSI characteristic verification, see Shii Shii Shii (1987), pages 133 to 136 (1987, CICC pp133
~ P136). In this document, after a detailed wiring pattern is created, the wiring resistance / capacitance is obtained from the wiring pattern to verify the characteristics.

Also, as a method of determining the arrangement of elements in the LSI,
There is JP-A-62-39042. In this method, first,
After tentatively determining the arrangement of elements, a virtual wiring route is determined. The signal delay is evaluated based on the theoretical line length based on this virtual wiring path, and the evaluation result is reflected in the element layout. It is disclosed that a technique such as the Steiner tree method is used in the method of assuming the virtual wiring route.

As for the detour method of the wiring route, the detour method based on the setting of the detour point is described.

[Problems to be solved by the invention]

By the way, in order to create a wiring pattern in an LSI, it is necessary to finally create a detailed wiring pattern (including consideration of through holes, etc.) and verify the characteristics of this wiring pattern. In creating a detailed wiring pattern, a wiring pattern satisfying all the required electrical and physical conditions such as a layout rule is required, and a large number of man-hours are required for the creation. Therefore, since the detailed wiring pattern is created every time the target characteristic is not obtained in the characteristic verification as described above, there is a problem that the number of LSI design steps is increased.

Therefore, it is necessary to predict the characteristics of this wiring pattern before creating a detailed wiring pattern. In order to predict the characteristics, it is necessary to create a temporary wiring pattern for verifying the characteristics. The provisional wiring pattern cannot accurately predict the characteristics unless it is close to the detailed wiring pattern to be finally created. On the contrary, if the temporary wiring pattern is approximated to the final detailed pattern, the man-hours for designing the temporary wiring pattern increase, and the man-hours for designing the LSI cannot be reduced.

The present invention has been made as a result of the discovery and analysis of the above problems of the prior art by the present inventor.

It is an object of the present invention to provide a method for designing a semiconductor integrated circuit device, which predicts characteristics of a wiring pattern with high accuracy and realizes a significant reduction in design man-hours.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
After the cell layout design process, assign a signal name to each wiring, specify the image of the rough route, and automatically estimate the wiring between cells based on the specified wiring route and verify its characteristics. Try to do it.

[Action]

According to the above-mentioned means, the wiring pattern for the characteristic verification need only be specified as a rough route, and all electrical and physical requirements such as layout rules after the target characteristic is achieved are achieved. Since it is only necessary to create a wiring pattern that satisfies the conditions, it is possible to significantly reduce the design man-hours.
Also, by specifying a rough route, it is possible to perform highly accurate characteristic prediction that approximates the final wiring pattern.

〔Example〕

FIG. 1 (A) is a block diagram showing a schematic embodiment of data input by a person in the designing method according to the present invention.

The cells C1 to C7 to be created are arranged on the semiconductor chip 4. Here, a cell is a group of circuits (unit block circuits) that perform a certain function. Therefore, the cell may be a unit circuit such as an inverter, AND or OR, or an input buffer, an output buffer, and a block circuit such as a memory array. Normally, the cells are standardized, and the cell to be used is specified from among the prepared cells. In addition, in this step, a cell design for a specific purpose may be included. Each cell has
A terminal name or signal name is added to the input or output terminal. For example, cells C1, C3 and C6 have terminals T5, T1 respectively.
And T2 are provided, and the cell C7 is provided with terminals T3 and T4.

When the placement of the cells is completed, rough wiring routes (rough wiring routes) RW1 and RW2 are designated. The rough wiring routes RW1 and RW2 are added with signal names to be transmitted to the respective wirings passing therethrough.

The drawing as shown in FIG. 1 (A) is displayed on the screen of the graphic terminal (display device), and in the case of the straight route RW1, the wiring route simply specifies the starting point and the ending point. Just a good, bent route RW2,
All you have to do is specify each point connected by a straight line. Corresponding to the designation of such a route, a signal name to be passed therethrough is added.

FIG. 1 (B) is a block diagram of a schematic embodiment showing the characteristic verification by the computer system in the design method according to the present invention.

In the computer system, the wiring route is first estimated automatically based on the data input as described above. For example, from the terminal name (signal name) of each cell and the signal name of the wiring route corresponding to it, the estimated wiring shapes W1 to W5 as shown by the dotted lines in the figure are determined. Techniques such as the Steiner tree method and the minimum spanning tree method are used to estimate the wiring shape. In addition,
This estimated wiring shape does not satisfy all required electrical and physical conditions such as layout rules in the semiconductor integrated circuit. Therefore, in estimating the wiring shape, the wiring route between the cells is simply estimated.

When the wirings W1 to W5 as described above are estimated, the characteristic verification is started. That is, since each wiring route is determined by the rough wiring route and the estimated wiring shape, the wiring resistance value and the parasitic capacitance are estimated based on the wiring route. That is, as shown in the equivalent circuit diagram of FIG. 2, since the wiring route is determined as described above, each length is calculated. Using this wiring length and the separately given wiring pattern resistance value and capacitance value per unit length, the resistance value R and the capacitance value Cp in each wiring pattern are obtained.

The data thus created is passed to the characteristic verification device or the characteristic verification program in the computer system for characteristic verification.

If, as a result of the above characteristic verification, it is determined that the target characteristic cannot be obtained, returning to FIG. 1 (A),
The same operation is repeated by changing the arrangement of cells and the rough wiring route. If it is determined by the characteristic verification that the target characteristic is obtained, detailed wiring design is performed so as to satisfy all required electrical and physical conditions such as the layout rule in the semiconductor integrated circuit device.

FIG. 3 is a flowchart of the design process as described above.

That is, when the cell circuit design (step S1) and the cell layout design (step S2) are finished, only a rough wiring image is created (step S3), and thereafter, the estimation of the wiring shape and the characteristic evaluation using the computer system are performed. The characteristic prediction (step S4) is performed after calculating the resistance value and the capacitance value for. If it is determined that the target characteristics cannot be obtained (step S5), only a relatively simple process of re-designing the cell, changing the cell layout, or roughly changing the wiring route is added. Then, after it is determined that the target characteristics can be obtained, all the required electrical and physical conditions such as layout rules (through-hole examination, etc.) in the actual semiconductor integrated circuit are considered and the details are satisfied. Wiring design (step S6) is performed. After that, although not shown, if necessary, the detailed wiring design is performed and then the characteristic verification for confirmation is performed again.

By the way, if the man-hours spent in the process of creating the above-mentioned cell design, cell layout design, and rough wiring image are 5 and the man-hours spent in detailed wiring design are 5,
If the target characteristic is not achieved twice in the characteristic verification, the cell design, the cell layout design and the step of creating a rough wiring image are each performed three times in the design method according to the present invention. Therefore, a semiconductor integrated circuit can be designed with 5 × 3 + 5 = 20 man-hours.

On the other hand, in the conventional technique, if the target characteristic is not achieved twice in the characteristic verification as described above, the detailed wiring design needs to be performed each time, and therefore the total man-hour is 3 × (5 + 5) = It will be as large as 30 man-hours.

FIG. 4 is a flow chart showing another embodiment of the design method according to the present invention. In addition, FIG. 5 (A), (B),
(C) and (D) are process steps S11, S11 shown in FIG.
It is drawing explaining the processing content by S14, S17, and S18.

In step S11, as shown in FIG. 5 (A), the cells C11 to C21 are arranged, and the input or output terminals of each cell, for example, the coordinate positions of the terminals T11, T12, and T13 are determined. It Further, the positions on the coordinates of the rough wirings RW11 and RW12 of the wirings that connect the terminals T11, T12, and T13 to each other are determined.

In step S12, the interconnection state of the rough wirings RW11 and RW12 is checked. If it is determined in step S13 that the rough wirings RW11 and RW12 are not connected to each other, the process branches to step S14, and if it is determined that they are connected to each other, the process proceeds to step S15.

In step S14, as shown in FIG. 5B, an L-shaped connection wiring RCW, which is the shortest wiring connecting the wirings RW11 and RW12, is added.

In step S15, the wiring RW11, RCW and RW12 and the terminal T
11, the interconnection status with T12 and T13 is checked. In step S16, if it is determined that the wiring is not connected to the terminals T11, T12 and T13, the process is branched to step S17, and if it is determined that they are connected, step S1
Move to 8.

In step S17, as shown in FIG. 5 (C), the straight wiring CW11 and the terminal T connecting the terminal T11 and the wiring RCW are connected.
L-shaped wiring CW12 and terminal T13 connecting 12 and wiring RW11
And an L-shaped wiring CW13 that connects the wiring to the wiring RW12.

In step S18, as shown in FIG. 5D, the wiring resistances R1 to R3 and the wiring capacitances Cp1 to Cp6 are calculated, and the characteristic of the wiring is predicted. In step S19, it is determined whether or not the processing has been completed for all the signal wirings to be predicted, and if not completed, the processing returns to step S11.

According to the present invention, the rough wirings RW11 and RW12 can be set first when setting the temporary wiring route for the characteristic prediction, so that the temporary wiring extremely close to the final detailed wiring can be set. Therefore, highly accurate characteristic prediction is possible. Furthermore, the above rough wiring route is
Since the person who sets the wiring route can artificially set it while looking at the screen of the graphic terminal, there is a high degree of freedom in setting the wiring route. Therefore, it is possible to intentionally detour the wiring route and artificially adjust the signal delay.

FIGS. 6A to 6C show an embodiment showing the relationship between the rough wiring RW and the final detailed wirings DW1 to DW4. FIG. 6A shows a state in which cells C1 and C2 and a rough wiring RW are set on the semiconductor chip. Cell C1 has a terminal
Ta, Tb, Tc and Td are set, and the above-mentioned terminals Ta, T are set in the cell C2.
Terminals T to be connected corresponding to b, Tc and Td respectively
a ', Tb', Tc 'and Td' are set. FIG. 6 (B)
Is the above-mentioned rough wiring RW and terminals Ta, Tb, Tc, Td, Ta ′, Tb ′,
The estimated wirings CW1 to CW8 between Tc ′ and Td ′ are set. FIG. 6C shows the shapes of the finally formed detailed wirings DW1 to DW4. As described above, by performing the characteristic prediction of the plurality of wirings DW1 to DW4 based on one rough wiring RW, the characteristic prediction can be efficiently performed.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, any technique other than the Steiner tree method or the minimum spanning tree method may be used as a technique for estimating the wiring shape between the cells from the cell arrangement and the rough wiring image. Further, the method of inputting the cell layout and the rough wiring image can take various modes according to the computer system used.

The present invention can be widely used as a method for designing a semiconductor integrated circuit device.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, after the cell layout design process, each wiring is given a signal name, an image of its rough route is specified, and the wiring between cells is automatically estimated based on the specified wiring route and its characteristics are determined. By performing the verification,
To create a wiring pattern for characteristic verification, all you have to do is specify a rough route, and after the target characteristics are achieved, a wiring pattern that satisfies all required electrical and physical conditions such as layout rules will be created. Since it can be created, the number of design man-hours can be greatly reduced.

[Brief description of the drawings]

FIG. 1 (A) is a block diagram of a schematic embodiment in which manual data input in the design method according to the present invention is illustrated, and FIG. 1 (B) is a characteristic of a computer system in the design method according to the present invention. FIG. 2 is a block diagram of a schematic embodiment in which verification is made a drawing, FIG. 2 is an equivalent circuit diagram thereof, and FIGS. 3 and 4 are flowcharts for explaining a design method according to the present invention. FIGS. 6A to 6C are drawings for explaining the processing contents of main steps of the flowcharts shown in FIGS. 6A to 6D, and FIGS. 6A to 6C are drawings for explaining another embodiment of the designing method according to the present invention. It is a drawing. W1 to W5: wiring, R: resistance, Cp, Cp1 to Cp6: capacitance

Claims (6)

(57) [Claims] 1. A step of arranging a plurality of cells on a semiconductor chip, designating a coordinate position of an input or output terminal of each cell, and adding a terminal name or a signal name to the input or output terminal of each cell. And a step of designating the position on the coordinates of the rough wiring route of the wiring connecting between the terminals and adding a signal name to each of the wirings passing through the wiring route. A step of inspecting a connection state, a step of inspecting a connection state between the wiring and the terminal when it is determined that the wirings passing through the rough wiring route are connected to each other, and a wiring passing through the rough wiring route And a terminal are connected, a step of performing characteristic prediction on the wiring route is included, and a wiring design method for a semiconductor integrated circuit device. 2. In the step of inspecting the connection state of the wirings passing through the rough wiring route, when it is determined that the wirings passing through the rough wiring route are not connected to each other, the wiring is set to the shortest wiring. 2. The wiring design method for a semiconductor integrated circuit device according to claim 1, further comprising the step of connecting by wiring. 3. In the step of inspecting the connection state between the wiring and the terminal passing through the rough wiring route, the wiring is closest to the terminal when it is determined that the wiring and the terminal are not connected to each other. The wiring design method for a semiconductor integrated circuit device according to claim 1, further comprising: a step of adding a straight wiring to a point on the wiring. 4. After the step of predicting the characteristics of the wiring route is completed, it is judged whether or not the processing for all the wiring to be predicted is completed, and when the processing is not completed, the wiring for connecting the terminals is determined. The wiring of the semiconductor integrated circuit device according to claim 1, wherein the process returns to the step of designating a rough coordinate position of the wiring route and adding a signal name to each of the wirings passing through the wiring route. Design method. 5. A step of arranging a plurality of cells having a plurality of input or output terminals on a semiconductor chip and adding a terminal name or a signal name to the input or output terminal of each cell; Specifying a rough wiring route commonly to the plurality of terminals in each cell connected between the two, and adding a signal name to each of the wirings passing through the wiring route, and the designated wiring route. Automatically estimating a common wiring that interconnects the terminals of each cell on the basis of the data, and predicting the characteristics from the data, a wiring design method for a semiconductor integrated circuit device. 6. The wiring design method for a semiconductor integrated circuit device according to claim 5, wherein the same number of terminals are designated for each of the cells connected to each other.