JP2910104B2 - Circuit delay information analysis system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit delay information analysis system.

[Conventional technology]

2. Description of the Related Art Conventionally, input of circuit diagram data using a circuit diagram input device and automatic layout of an LSI using circuit connection information generated from the circuit diagram data and an existing layout cell library have been actively performed. . In this type of design method, it is common to analyze circuit delay information before and after automatic layout. As specific contents of the circuit delay information analysis, a design rule check, a delay simulation, a delay analysis, and the like are performed in combination.

FIG. 5 is a block diagram for explaining a transmission delay time between cells to be laid out, which is a processing target of the conventional circuit delay information analysis system.

In FIG. 5, the output of cell 51a is connected to the input terminals of cells 51b and 51c. Input capacitors Cb and Cc exist at the input terminals of the cells 51b and 51c, and have the sizes represented by CGb and CGc, respectively.

 Generally, the transmission delay time is obtained by the following equation (1).

Tpd = TpdO + (Cw + Cin) × Dc (1) (TpdO = no-load delay time) (Tpd = transmission delay time) (Cw = wiring capacitance) (Cin = sum of input capacitance of next stage) (Dc = delay coefficient = Transmission delay time around capacity) Therefore, the transmission delay time Tpda of the cell 51a is expressed by the following equation (2).

Tpda = TdpOa + {Cw + (CGb + CGc)} × Dca (2) (Dca = delay coefficient of cell 51a) (TpdOa = delay time of cell 51a under no load) In the circuit delay information analysis of LSI, Cw and Cw are calculated for each cell. C
The main focus is to verify whether the circuit operates properly when in is considered. However, until Cw and Cin for a certain cell are finally determined, various studies are performed on the layout area and circuit delay. In actual LSI design, circuit delay information analysis is usually performed many times step by step.

Hereinafter, the case of the gate array design using the circuit delay information analysis system will be described.

FIG. 6 illustrates the flow of the circuit delay information analysis work in the actual LSI design.

First, after inputting circuit diagram data (S61), a design rule check (S63) is performed, and a fan-out check is performed on each cell. The fan-out is a concept for expressing a restriction on the load of each layout cell using a standardized load capacitance value. In practice, the input capacitance value of the inverter is set to 1, and the load capacitance value is often expressed.

This is because the rise time and fall time of the signal increase as the number of fan-outs increases, and the estimation accuracy of the propagation delay time deteriorates. This is because when the value becomes larger, data through occurs in the flip-flop, and a normal logical operation cannot be maintained. It is necessary to design each cell so as not to exceed the number of fan-outs, and a check for this is a design rule check. In this check, a check is performed on the input capacity of the cell having the load value. At the stage of design rule check (1)
Cw in the expression is not considered, and only the restriction of Cin is verified.

Subsequently, a delay simulation before the automatic layout is performed (S64). At this point, since the load due to the wiring in the actual layout is unknown, a delay simulation based on the temporary wiring length is performed. This is a simulation in which a load due to a virtual wiring length is uniformly applied to each layout cell. At this stage of the delay simulation, the virtual wiring length is expressed as Cw in the equation (1),
The actual value is considered for Cin. When it is confirmed that there is no problem in the delay simulation, the layout is automatically performed (S66).

As a result of the automatic layout, the actual wiring length is determined. Then, a delay simulation based on the actual wiring length is performed (S68). In the delay simulation at this stage, in equation (1)
The actual wiring length is used as Cw, and the actual value is used as Cin.

The automatic layout (S66) in FIG. 6 is usually performed several times, and an optimum result with respect to a chip size and a delay operation is selected. That is, the delay simulation under the load condition based on the actual wiring length is usually performed a plurality of times.

As a premise of the above-described design method, in an actual circuit, the load Cw due to the wiring is sufficiently smaller than the load Cin due to the input capacitance in the next stage. Based on this premise, verification is performed without considering Cw in the design rule check, and basic errors related to delay are eliminated.

Next, delay simulation considering Cw is performed.
Since the actual wiring length is unknown until automatic layout is performed, a virtual wiring length is considered. Conventionally, the provisional wiring length used in the field of gate arrays is about 3 mm. As the basis for this wiring length, there is statistical data indicating that most wirings have a wiring length of 3 mm or less when a distribution of wiring lengths is examined in a certain chip size range.

Therefore, since the actual wiring length after performing the automatic layout is almost the same as the tentative wiring length, there is a low probability that a serious delay-related error is found at this stage. Even if the wiring lengths are different, Cw is sufficiently smaller than Cin, so that it is unlikely to cause a large delay error.

[Problems to be solved by the invention]

The above-described conventional circuit delay information analysis system is configured to take steps of analysis without considering the wiring capacitance Cw, analysis considering the wiring capacitance Cw of the temporary wiring length, and analysis considering the wiring capacitance Cw of the actual wiring length. Therefore, it is effective for a gate array or the like that satisfies the condition of Cw << Cin, but has a drawback that it is not effective for a standard cell type LSI, particularly an LSI including a CPU core.

The reason is that an LSI such as a microcomputer including a CPU core always includes a bus wiring, and the wiring length is usually very long. As a practical example, if the bus wiring length is 20
It is not unusual to reach ~ 30mm.

In LSIs such as microcomputers, bus wiring and clock signal lines different from gate arrays and the like have very large wiring capacities, and delay simulation is performed by associating these wirings with an average temporary wiring length. It is useless.

As described above, in the standard cell LSI design including the CPU core, it is important to check the design rules and delay simulation considering the specially long wiring length, and there is no design environment for this. Is LSI
It was a major obstacle to development.

An object of the present invention is to provide a circuit delay information analysis system capable of performing effective and efficient analysis even for the design of a standard cell type LSI including a CPU core having an exceptionally long wiring length. It is in.

[Means for solving the problem]

A circuit delay information analysis system according to the present invention comprises: circuit diagram data input means for inputting circuit diagram data of a target circuit and first circuit connection information corresponding thereto; the first circuit connection information and the first circuit connection information; Display means for displaying second circuit connection information generated based on the connection information;
Cell name designating means for designating a cell included in the circuit connection information, wiring length input means for inputting a wiring length serving as a load on the cell designated by the cell name designating means, and inputting the designated cell to the designated cell. Circuit delay calculating means for calculating a delay time of the cell by adding a load having the determined wiring length, circuit connection information storing means for storing the first and second circuit connection information, and circuit connection information storing means Output means for outputting circuit connection information stored in the intermediate result including the delay time before layout calculated using the circuit delay calculation means, and the final result including the delay time after layout, There is provided circuit connection information writing means for updating the second circuit connection information generated by being added to the first circuit connection information.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a circuit diagram data input means 1 for inputting circuit diagram data of a target circuit and first circuit connection information corresponding thereto, the first circuit connection information and the first circuit connection information are used as an intermediate result. And display means 2 for displaying the second circuit connection information updated based on the final result, and cell name specification means 3 for specifying a cell name included in the first and second circuit connection information.
A wiring length input means 4 for inputting a wiring length serving as a load of the cell designated by the cell name designating means 3; and a delay time of the cell by adding a load of the wiring length inputted to the designated cell. And a circuit delay information writing means 6 for updating the first and second circuit connection information with an intermediate result and a final result including the delay time calculated by the circuit delay calculation means 5. , Circuit connection information storage means 7 for storing the first and second circuit connection information, and output means 8 for outputting the circuit connection information stored in the circuit connection information storage means 7. .

Next, a specific operation of this embodiment will be described.
Each means of this embodiment is specifically configured as follows, for example.

Circuit diagram data input means 1: Mouse, floppy disk device and circuit diagram editor program Display means 2: CRT display Cell name designation means 3: Keyboard Wiring length input means 4: Keyboard Circuit delay calculation means 5: Circuit delay calculation program Circuit delay book Means 6: circuit delay information writing program circuit connection information storage means 7: magnetic disk device output means 8: floppy disk deviceThe circuit connection information is roughly divided into connection information, display information, and input capacity. There are information, fan-out limit value, information about display, information about hierarchical path names, load capacity, and information about delay.

The information on the connection indicates a connection relationship between the cells. The information on display indicates information on coordinates, colors, sizes, and the like for displaying each cell. The information on the hierarchical path indicates the position in the hierarchical structure where each cell exists using a path name. The load capacitance has the load side from the output terminal of the cell to the load side, and represents the load capacitance due to the wiring and the input capacitance at the next stage. The information on the delay indicates the delay time under no load of each cell, the delay coefficient, and the delay time under load conditions based on the wiring length.

Consider the circuit diagram data of the circuit diagram shown in FIG. 2 as input data of the present system. The circuit connection information corresponding to the circuit diagram data has a list structure linked by the pointer P shown in FIG. The tags shown in bold lines in FIG. 3 represent leaf cells (actual data) LC. Table 1 shows the format of the data structure of this property.

As apparent from Table 1, by referring to the property information of each cell, the function name and unique name (unique name) of the cell can be found. The output signal of another cell to be connected to the cell and the output signal of the cell can be known by referring to the input signal name and the output signal connection destination. By referring to the input capacitance section, the input capacitance of the cell can be determined. This input capacitance value is used in the circuit delay calculation program of the circuit delay calculation means 5. By referring to the fan-out limit, the fan-out limit of the output terminal of the cell can be determined. This fan-out limit value is used in a design rule check described later. Further, using the circuit diagram editor program display of the circuit diagram data means 1 and the CRT display of the means 2, the vertex coordinates and display color of the cell symbol when displaying the cell, and the dimensions at the time of display can be known. In addition, the reference name (hierarchical path name) of the cell in a specific hierarchical structure is known. The load capacitance indicates a load capacitance value based on the wiring viewed from the output terminal of the cell and the input capacitance at the next stage. This load capacitance value is used in a circuit delay calculation program of the circuit delay calculation means 5.

There are roughly three types of information regarding delay. The delay time 0 (when no load is applied), the delay coefficient, and the delay time (when load is applied) correspond to TpdO, Dc, and Tpd described in the section of the related art.

Hereinafter, the operation of the circuit diagram shown in FIG. 2 when performing the delay analysis according to this embodiment will be described.

FIG. 4 is a flowchart for explaining the operation of this embodiment.

2 is input using the mouse of the circuit diagram data input means 1 and the circuit diagram editor program, and stored in the circuit connection information storage means 7. The data structure of the circuit connection information at this time is shown in FIG. In the circuit diagram of FIG. 2, it is assumed that the wiring 402 is a bus wiring. The property information of the cell 40 in FIG. 3 at this time is shown in Table 2.

Next, a design rule check is performed. At this time, the load is estimated after the load due to the bus wiring is predicted. The length of the bus wiring connected to the wiring 402 in FIG. 2 can be roughly obtained by designing the initial layout of the chip. The load based on the wiring length obtained in this way is incorporated into the circuit connection information already stored in the circuit connection information storage means 7,
This is output to the outside of the circuit delay information analysis system by the output means 8, and a design rule check is performed with reference to the circuit connection information.

Hereinafter, the process of incorporating the load of the above-described wiring length into the circuit connection information will be described with reference to the flowchart of FIG.

First, the cell 40 is designated by the keyboard which is the cell name designating means 3 in FIG. In this method, the circuit connection information having the list structure shown in FIG. 3 is searched, a pointer P of a directory 40 is found, and the property information of the leaf cell LC indicated by the pointer P is referred to.

Next, the cell 40 is input using the keyboard of the wiring length input means 4.
Is input.

Next, referring to the property information in Table 2, the names 41, 42, 43, and 44 of the cells to which the output of the cell 40 is connected are referred to.

Next, the input capacity of each cell is referred from the property information of the cells 41, 42, 43, and 44.

The following equation described in the circuit delay calculation program of the circuit delay calculation means 5 is calculated using the value of the wiring length W and the input capacitance value.

Cw40 = W × Lc + CG41 + CG42 + CG43 + CG44 = 2.0 [pf] (Lc = wiring capacitance coefficient [pf / mm]) (W × Lc = 1.2 [pf]) (CG41 = input capacitance of cell 41 = 0.2 [pf] (CG42 = cell 42) (CG43 = input capacitance of cell 43 = 0.2 [pf] (CG44 = input capacitance of cell 44 = 0.2 [pf]) Next, the value of Cw40 obtained by the circuit delay calculating means 5 is Circuit connection information storage means 7 by circuit delay information writing means 6
In the already written circuit connection information. Table 3 shows the latest property information of the cell 40 stored in the circuit connection information storage means 7 at this time.

The property information in Table 3 is read from the circuit connection information storage means 7 and output to the outside of the circuit delay information analysis system by the output means 8.

Refer to the property information of cell 40 output to the outside,
The fan-out limit value and the value of the load capacity Cw obtained earlier can be determined. For example, the capacity value per fan-out
Assuming 0.15pf, the fanout limit of 10 in Table 3 indicates that the load capacity must be less than 1.5pf.
In Table 3, it is clear that the load capacity is 2pf, which violates the fan-out limit. Since this design rule check program is a program that simply compares two numerical values, it can be configured very easily. At the stage of design rule check
Since the value of Tpd is unnecessary, the process of calculating the transmission delay time (S45) in FIG. 4 is omitted.

Next, when a delay simulation is performed using this embodiment, first, as in the case of the above-described design rule check, the cell name 40 is specified and the wiring length is input.

Next, the transmission delay time Tpd40 of the cell 40 is obtained using the load capacity Cw40 of the cell 40. At this time, the transmission delay time and the delay coefficient under no load are obtained from the property information of the cell 40, and are calculated by the following equation described as a program in the circuit delay calculation means 5.

Tpd40 = TpdO40 + Cw40 × Dc40 = 0.8 + 2 × 0.12 = 1.04 [ns] Next, the value of Tpd40 obtained by the circuit delay calculation means 5 is already written in the circuit connection information storage means 7 by the circuit delay writing means 6. In the existing circuit connection information. The latest property information of the cell 40 stored in the circuit connection information storage means 7 at this time is shown in Table 4.

The property information in Table 4 is read from the circuit connection information storage means 7 and output to the outside of the circuit delay information analysis system by the output means 8.

Delay time of property information of cell 40 output to outside
Perform delay simulation with reference to Tpd40. Tpd is a value that is extremely commonly used in delay simulation.

Although the delay simulation is performed before and after the layout as shown in FIG. 6, in the case of the delay simulation before the layout, the value obtained in the initial layout design as described above may be input as the wiring length. . In the delay simulation after the layout, the wiring length extracted from the actual layout result may be input.

In the above description, the cell 40 connected to the bus wiring is discussed, but a plurality of cells may be specified. Therefore, by repeatedly using this embodiment, a load with an arbitrary wiring length can be applied to an arbitrary cell included in the circuit connection information.

As the wiring length, before the layout, a wiring length close to the actual value obtained by the initial layout design or the like can be used. It is possible to perform the design rule check and the delay simulation as described above using the load due to the wiring length.

As another embodiment of the present invention, a circuit diagram data input means 1
An image scanner or tablet, a liquid crystal display or a plasma display as the display means 2, a mouse as the cell name designation means 3 and the wiring length input means 4, an optical disk device as the circuit connection information storage means 7, and an output means. A magnetic tape device can be used as 8. These hardware may be those widely used in the past, and no special specifications are required.

Further, the circuit connection information processed by the circuit delay calculation means 5 and the circuit delay information writing means 6 may not have a list structure.

〔The invention's effect〕

As described above, the present invention provides a configuration in which a wiring having a specific wiring length is added to a load of a specified cell to calculate a delay time, thereby providing a CPU core having a specific long wiring length. Also, there is an effect that an effective and efficient analysis can be performed for an LSI design including

[Brief description of the drawings]

1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram of a circuit processed by the embodiment shown in FIG. 1, and FIG. 3 is an embodiment shown in FIG. FIG. 4 is a flowchart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 5 is a diagram for explaining the operation of a conventional circuit delay information analysis system. FIG. 6 is a block diagram of a circuit to be processed, and FIG. 6 is a flowchart for explaining the operation of a conventional circuit delay information analysis system. DESCRIPTION OF SYMBOLS 1 ... Circuit diagram data input means, 2 ... Display means, 3 ... Cell name designation means, 4 ... Wiring length input means, 5 ... Circuit delay calculation means, 6 ... Circuit delay information writing means, 7 ... Circuit connection information storage means , 8 ... output means, 40-44, 51a-51c ... cell, 52,402
... wiring, LC ... leaf cells, P ... pointers, S41-S45, S61
~ S69 ... Procedure.

Claims (1)

(57) [Claims] 1. Circuit diagram data input means for inputting first circuit connection information corresponding to circuit diagram data of a target circuit, and based on the first circuit connection information and the first circuit connection information. Display means for displaying the generated second circuit connection information, cell name designation means for designating cells included in the first and second circuit connection information, and cell name designation means designated by the cell name designation means. Wiring length input means for inputting a wiring length serving as a load of a cell; circuit delay calculating means for adding a load of the input wiring length to the designated cell to calculate a delay time of the cell; Circuit connection information storage means for storing the first and second circuit connection information; and output means for outputting the circuit connection information stored in the circuit connection information storage means. Delay before layout Circuit connection information writing means for updating the second circuit connection information generated by adding the intermediate result including the delay time and the final result including the delay time after layout to the first circuit connection information; A circuit delay information analysis system, comprising: