JPH0594421A - Information transmitting apparatus - Google Patents

Abstract

PURPOSE: To obtain a high-performance information transmission device for exchanging messages between the processors of an MP system by including control means to enable reading of the messages from local register in these processors. CONSTITUTION: A control unit 202 has the local register 208 for transmitting data to a data route/bus controller 212 through a local bus 210. The data is communicated between the controller 212 and a system bus 118 by a bus 214. Further, the data is communicated between an MPUx 204 and the data route/bus controller 212 through the MPU bus 216. During the operation of a PC, the controller 212 monitors the control signal from the system bus 118 which is on the bus 214 and monitors the address states in the system bus 118 through the bus 214 and an internal address decoding logic circuit. Further, the local register 208 is controlled via control 222 and the interruption output the MPUx 204 through interrupt control 224 is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer systems, and more particularly to multiple processors (M).
P) Computer configuration (architecture) for high-performance message transfer between processors of computer system
Regarding

[0002]

BACKGROUND OF THE INVENTION In operation, programs operating in a processor often have to exchange messages that may contain data or instructions. When a message has to be sent from one processor to another, the message is sent from the originating processor to a memory location in memory. A pointer to that storage location is placed in the message queue in storage. In addition, the interrupt is delivered to the target (destination) processor.

The program of the target processor then accesses the storage at a known location in the message queue and sorts through the message queue for pointers to that message. Finally, as soon as the target processor program finds the pointer, it reads the message from the memory location specified by that pointer. Generally, the message consists of a destination identifier that specifies the destination processor, a mission identifier, and the priority of the interrupt.

Therefore, the destination processor must arbitrate for the bus and must make a number of different reads from storage to retrieve the message. The above process is time consuming. Moreover, as more processors are added to the MP system, the amount of communication on the bus increases, which increases the time delay and thus defeats the purpose of simultaneous processing by multiple processors.

In addition, the prior art on message transfer has created a special and complex interrupt routine for each processor to be executed by the processor of the MP system to handle various types of interrupts, interrupt priorities, and messages. It is necessary to provide a proper algorithm. In order to convey a message to one processor and another message to another processor, each processor must sort through that message and determine which message belongs to that processor.

Each message comprises a destination identifier that aids the processor in the process described above. The destination identifier is an indicator of the intended destination of the interrupt, which may be a particular processor, a processor, or a subset of all processors. Therefore,
In order to sort through the previous information contained in each message, the need interrupt routine must be quite complex.

[0007]

OBJECTS OF THE INVENTION It is an object of the present invention to provide a high performance message exchange between processors in an MP system that reduces traffic on the system bus, processor time delay, and complexity of interrupt routines associated with message transfer. It is to provide a configuration and a method.

[0008]

SUMMARY OF THE INVENTION The present invention comprises local registers associated with each processor of a multiprocessing (MP) system. Each local register stores messages destined for its corresponding processor from other processors in the MP system.

A data path / bus controller associated with each local register monitors control signals from the corresponding processor and bus network of the MP system. Moreover, the data path / bus controller not only controls access to the local registers by the corresponding processor and by the bus network, but also controls access to the bus network by the corresponding processor.

In operation, the data path / bus controller causes the register to read a message from the bus network as soon as the bus network detects a write cycle to the address space assigned to the local register. Then, the data path /
The bus controller informs its corresponding processor that a message has been received, for example by means of an interrupt. Finally, the data path / bus controller allows the processor to read messages from its local registers.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a schematic representation of n respective central processing units (C
PU) 112-116 microprocessor (M
1 illustrates a traditional personal computer (PC) configuration with a PU) 102-106. n MPUs 102
-106 can be homogenous or heterogeneous. For example, MPU (manufactured by Intel Corporation in the United States) from "INTEL" and "MOTOROL"
It can be mixed with MPU from company "A" (manufactured by Motorola, USA). n MPUs 102 ~
106 communicates via system bus 118. Moreover, the n MPUs 102 to 106 share the storage space of the main storage device 120 in whole or in part.

The n MPUs 102-106 can also be installed along structurally separated busbars having various protocols. Therefore, the system bus 118 as shown in FIG. 1 may be a combination of non-homogeneous buses. Furthermore, n
Any of the MPUs 102-106 may be equipped with a local bus and directly or indirectly the system bus 118.
It can also be installed on a traditional input / output (I / O) card (not shown) that is connected to the.

Traditionally, when n MPUs 102-106 exchange messages with each other, system storage 120 is used to store messages from the originating MPU. Besides, the subsequent interruption is the destination MP
It is communicated to U so that its destination MPU will retrieve the message from system storage 120.

In order for the destination MPU to access the system storage 120 for that message, the destination MPU must arbitrate the system bus 118, which can consist of a combination of buses as described above. And must make several different reads from system storage 120. The traditional process described above is time consuming. Moreover, more processors are available in Figure 1.
System Bus 1 as it is added to the MP system of
The 18 congestion increases, which increases the time delay and thus defeats the purpose of simultaneous processing by n MPUs 102-106.

Further, traditional techniques for message transfer include n MPUs 102-10 to accommodate different types of interrupts, interrupt priorities, and messages.
An interrupt routine executed at 6 must be specially made for each MPU and a complex algorithm must be provided. In particular, each MPU has a system storage device 1 in order to carry some messages, one message to one MPU, another message to another message.
You must sort through the messages in 20 and determine the destination of the message.

Each message has n M
A destination identifier is provided to assist the PUs 102-106. The destination identifier is an indicator of the intended destination of the interrupt, which is a specific MPU, some individual MPU,
Or it may be a subset of all n MPUs 102-106. Therefore, in order to sort through the previous information contained in each message, the interrupt routine by necessity must be quite complex when using the traditional message transfer process.

FIG. 2 shows a high level block diagram of the arrangement of the present invention. The control unit 202 is the n MPUs of FIG.
Associated with each of 102-106. Control unit 2
02 may be implemented by an application specific integrated circuit (ASIC), discrete component, or other device that has the functionality described herein. Further, an MPU _x 204 having a CPU _x 206 is shown connected to the control unit 202. MPU _x 204 is n individual MPUs
It represents any of 102 to 106.

As shown, the control unit 202 comprises a local register 208 which conveys data to a data path and bus (data path / bus) controller 212 via a local bus 210. The data path / bus controller 212 is a simple state machine in combination with a bus transceiver and may comprise any of a number of devices well known to those skilled in the art having the functionality described in detail below. it can.

The data is, as indicated by bus 214,
Data path / busbar controller 212 and system busbar 1
Communicates with 18. The bus bar 214 is composed of a data line, a control line, and an address line. In addition, data is communicated between MPU _x 204 and data path / bus controller 212 via MPU bus 216.
In a sense, the data path / bus controller 212 is
It acts as a type of switch that switches local bus 210 to communicate with MPU bus 216 or system bus 118.

During PC operation, the data path / bus controller 212 monitors the control signals from the system bus 118 on bus 214. The control signals include data read / write (W / R) and storage / input / output (MEM / IO).
There is. In addition, the data path / bus controller 212
Monitors the addresses on system bus 118 via bus 214 and internal address decoding logic (not shown). In addition, the data path / bus controller 212 can control the local register 208 via control 222 and also interrupt the MPU _x 204 via interrupt control 224.

In the present invention, the message is written to the local register corresponding to each CPU, rather than to system memory 120 as is conventional. The method of the present invention is illustrated by the flow chart shown in FIG.

FIG. 3 illustrates the sequence of events in accordance with the present invention corresponding to the transfer of a message from a source CPU _z (not shown) to a CPU _x 206 of FIG. 2 which acts as a destination CPU.
At block 304 of the flowchart, the bus cycle is the originating CP.
Started at system bus 118 by U _Z. This bus cycle is CPU _x 206 as shown in block 306.
Are recognized by the data path / bus controller 212.

In the preferred embodiment, each local register is assigned the same address space within a given address range. The address space can be an I / O address space or a storage address space. Moreover, the data path / bus controller 212 listens for writes on the system bus 118 in I / O space or storage space within a given address range. Also, in the default state, the data path / bus controller associated with each CPU is the system bus 118.
It is worth noting that it has its respective local bus (data) in contact with.

Thus, when a bus cycle is initiated by CPU _Z , the bus cycle is recognized by all n CPUs in the MP system unless some sort of selection mechanism is implemented. Such a mechanism is outside the scope of the invention and will not be described here. The message is written from CPU _Z to a local register 208 associated with CPU _x 206, as indicated by block 308. When the message is written to the local register 208, the data path / bus controller 212 interrupts the local CPU _x 206 through the interrupt control 224 and the local CPU _x 206
To start and execute the interrupt routine.

Thus, an interrupt is automatically triggered in the destination CPU _x 206 as soon as the message transfer is complete. If the message is more than one write, the interrupt at the destination CPU will be initiated after the last write cycle.

Next, at block 312, the data path / bus controller 212 waits for an interrupt acknowledge from CPU _x 206. Upon receipt of this interrupt response, the data path / bus controller disconnects local bus 210 from system bus 118 and disconnects MPU bus 216 from local bus 21.
Connect to 0.

Finally, as indicated by block 314, C
PU _x 206 reads the message from a local register 208 in control unit 202. The message includes the normal destination identifier that specifies the destination processor, the normal mission identifier, and the normal interrupt priority, as well as the state information and identity of the originating MPU _Z.

CPU _x 206 has its local registers 208
CPU _x 206 reads the system bus 11 when reading from
Note that it is not necessary to generate a read cycle at 8. As a result, system bus 118 traffic and congestion is substantially reduced by the present invention. Furthermore, CP
U _x 206 and CPU _Z do not need to arbitrate system bus 118.

As a further result of the present invention, all of the n CPUs in FIG. 1 can execute the same interrupt routine, and the interrupt routine need not be as complicated as in the prior art. Destination CP during execution of interrupt routine
The U _x 206 is read by the path / bus controller 212 in the associated local register 208. The interrupt routine need only comprise instructions that direct the executing CPU to read the address space assigned to the local registers.

The interrupt routine need not have the complex algorithms needed to sort through multiple messages. In other words, the interrupt routine need not make a determination as to whether the message belongs to that CPU or some other CPU. As a result, the present invention reduces software overhead for interrupt routines and makes the program uniform.

FIG. 4 is a low level block diagram of the configuration (architecture) of the preferred embodiment. As shown, the control unit 202 comprises the local register 208 of the present invention. In addition, the data path / bus controller 21 of FIG.
2 is collectively implemented in FIG. 4 by control logic 406 having bidirectional MPU bus transceiver 402, bidirectional system bus transceiver 404, and address decode 408. The control logic 406 also substantially comprises a simple state machine that selectively controls the bus transceivers 402 and 404 and the local registers 208 of the control unit 202. MPU direction control 410 and system direction control 4
12 are both output from the control logic 406, but control the orientation of the MPU bus transceiver 402 and the system bus transceiver 404, respectively.

The control logic 406 controls from the system bus 118, among other things, W / R, M, as indicated by the double-headed arrow 414.
Monitor EM / IO and control signals including address lines. Moreover, control logic 406 monitors the control signals from MPU _x 206, as indicated by double-headed arrow 416.

Initially, or at default in operation, M
The PU bus transceiver 402 connects the local bus 210 to the MP bus via the MPU direction control 410 by the control logic 406.
It is set so as not to be connected to the U bus 216. In addition, the system bus transceiver 404 is set by the control logic 406 via the system direction control 412 to read from the system bus 118 and the data to the local register 2.
Set to tell 08. Moreover, control logic 4
06 may enable writing to local register 208 by control 414.

In operation, the MPU _x 204 is moving the MPU bus 21
When issuing a read instruction to 6, control logic 406 decodes the cycle to determine where the read request is indicated. In accordance with the present invention, the read can be done from the local register 208 or elsewhere in the MP system, where M
Request PU _x 204 to access system bus 118. An example of the latter scenario is when the MPU _x 204 needs to read from system storage 120 (FIG. 1).

Further, if access to system bus 118 is required, control logic 406 causes system bus 118 to
Arbitrate. Upon receiving permission to access the system bus 118, the control logic 406 causes the bidirectional transceiver 40 to
2 and 404 are adjusted to allow MPU _x 204 to communicate with system bus 118 and generate bus cycles at system bus 118.

When an MPU _Z somewhere in the MP system wants to write a message to MPU _x 206 of FIG. 4, MPU _Z writes the message to system bus 118 and signals system bus 118 a store write cycle. This memory write cycle is performed by the local register 20.
8 address space. Upon recognizing a store / write cycle, control logic 406 causes (via control 414) local register 208 to system bus transceiver 4
04 and local bus 210 through system bus 118
Read the message from.

When the message has been written to local register 208, control logic 406 issues an interrupt to MPU _x 2
Send to 04. Then, in the preferred embodiment, the control logic 406.
Substantially isolates the control unit 202 from the system bus 118 by specifying the orientation of the system bus transceiver 404 so that it does not read from the system bus 118. At the same time, the MPU bus transceiver 402
Direction is specified by the control logic 406 and the MPU _x 20
4 from the local bus 210 and thus the local register 208
Can be read from.

Control logic 406 then causes control 419 to allow local register 208 to write data to local bus 210, and ultimately to MPU _x 204. Therefore, the MPU _x 204 is the system bus 1
Messages can be easily retrieved without arbitrating 18 or waiting for its control.

[0039]

As described above, the present invention overcomes the drawbacks of the prior art, and further has the following other features and advantages. First, the invention reduces traffic on the bus of the MP system, including addressing and data transmission. As a result, the number of processors that can be connected to the MP system increases.

Secondly, the present invention minimizes the time delay of the processor. Therefore, the overall response and speed of the MP system is enhanced.

Third, the present invention reduces the complexity of the interrupt routines executed by the MP system processor. In a similar respect, the present invention is uniform among processors because each processor is directed to its corresponding local register when retrieving a message, rather than having to sort through the messages as they exist in system storage. Various interrupt routines are possible.

Fourth, the present invention enables a versatile processor and bus configuration. In other words, the present invention can be implemented with homogeneous or heterogeneous MPUs. For example, MPU from "INTEL" MPU (manufactured by Intel Corporation of the United States) is "MOT
It can be mixed with MPU of "OROLA" (manufactured by Motorola, USA). Further, the present invention can be implemented in MPU systems with a variety of interconnected busbars without redefining the various busbar protocols and / or suitability models.

[Brief description of drawings]

FIG. 1 is a block diagram of a general electronic computer configuration to which the present invention can be applied.

FIG. 2 is a block diagram of an information transmission device according to the present invention.

FIG. 3 is a flowchart showing the operation of the information transfer device according to the present invention.

FIG. 4 is a detailed block diagram of an information transfer device according to the present invention.

Claims (1)

[Claims] 1. One or more processors communicating with each other via a bus network, a local register provided in association with each processor for storing a message to the corresponding processor, and associated with each local register. And the local register reads and stores the message from the bus network, interrupts the corresponding processor after the storage, and causes the processor to read the message from the local register. Information transmission equipment.