JPH0594415A - Bus fight preventing circuit - Google Patents

Abstract

PURPOSE:To prevent a bus fight without deteriorating a bus performance by adjusting the delay time of the output control signal of each driver. CONSTITUTION:Each buffer G0-G8 is cascade connected. Each selector S1-S3 is provided between G0-G8, and one of inputted two kinds of waveforms whose gate delay is different is selected according to outside selecting signals SS1-SS3. A NAND gate G9 performs the NAND of both the outside output control signal from the buffer G0, and one of the eight kinds of outside output control signals delayed so that each delay time can be different by the buffers G1-G8, and the selectors S1-S3, and outputs the obtained data to the output control part of a driver G10. Thus, the time when the active state of the output state of the driver can be started can be adjusted by the outside selecting signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus fight prevention circuit, and more particularly to a bus fight prevention of a bus driver connected to a bus.

[0002]

2. Description of the Related Art Conventionally, in a bus fight prevention circuit,
To reduce the skew between the output control signals of each driver by equalizing the number of gate stages and the number of loads for distributing the output control signals of each driver connected to the bus,
Alternatively, an empty cycle is inserted every one cycle.

In such a conventional bus fight prevention circuit, when the number of gate stages and the number of loads are made equal in order to reduce the skew between the output control signals of the respective drivers, the output control signals between the output control signals are varied due to variations in gate delay time. There is a problem that the skew cannot be reduced to zero. Also,
When an empty cycle is inserted every one cycle, there is a problem that the bus performance is deteriorated.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned problems of the conventional one, and enables adjustment of the delay time of the output control signal of each driver, and the bus fight without degrading the bus performance. An object of the present invention is to provide a bus fight prevention circuit capable of preventing the above.

[0005]

The bus fight prevention circuit according to the present invention comprises:
A driver connected to the bus, a plurality of gates connected in cascade, and a plurality of gates provided between the plurality of gates, respectively, and an output of the preceding stage gate and at least one of the preceding stage gates according to an external signal. One or more selection means for selecting one of the output of the previous gate and outputting it to the gate of the subsequent stage, and a control signal from the outside and the control signal from the outside are delayed by the plurality of gates and the selection means. And a logic gate that outputs an active signal when both the generated signal and the signal are activated at the same time, and the output control of the driver is performed by the active signal from the logic gate.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. In the figure, G0 to G8 are buffers with one input and one output, G9 is a NAND gate with two inputs, and
Reference numeral 10 is a driver connected to a bus (not shown), and S
1 to S3 are 2-input 1-output selectors.

An external output control signal (ENB) for controlling the output state of the driver G10 is applied to the input part of the buffer G0.
Is input and the waveform output from the output section of the buffer G0 is input to one input section of the NAND gate G9 and the input section of the buffer G1.

The waveform input to the input section of the buffer G1 is delayed by the gate delay of the buffer G1 and is delayed by the buffer G1.
Is input to the input section of the buffer G2 and one input section of the selector S1. The waveform input to the input section of the buffer G2 is delayed by the gate delay of the buffer G2 and input from the output section of the buffer G2 to the other input section of the selector S1.

Compared to the waveform from the output section of the buffer G1 input to one input section of the selector S1, the selector S
The waveform from the output of the buffer G2 input to the other input of 1 is delayed by the gate delay of the buffer G2. Two kinds of waveforms from the output parts of the buffer G1 and the buffer G2 are selected by the selector S1 in accordance with the external selection signal SS1. The waveform selected by the selector S1 is input from the output section of the selector S1 to the input section of the buffer G3 and one input section of the selector S2.

The waveform input to the input section of the buffer G3 is delayed by the gate delay of the buffer G3,
Is input to the input section of the buffer G4. The waveform input to the input section of the buffer G4 is delayed by the gate delay of the buffer G4 and input from the output section of the buffer G4 to the other input section of the selector S2.

Compared to the waveform from the output section of the selector S1 input to one input section of the selector S2, the selector S
The waveform from the output of the buffer G4 input to the other input of 1 is delayed by the gate delay of the buffers G3 and G4. Two types of waveforms from the output parts of the selector S1 and the buffer G4 are selected by the selector S2 in accordance with the external selection signal SS2. The waveform selected by the selector S2 is input from the output section of the selector S2 to the input section of the buffer G5 and one input section of the selector S3.

The waveform input to the input section of the buffer G5 is delayed by the gate delay of the buffer G5,
Is input to the input section of the buffer G6. The waveform input to the input section of the buffer G6 is delayed by the gate delay of the buffer G6 and input from the output section of the buffer G6 to the input section of the buffer G7. The waveform input to the input section of the buffer G7 is delayed by the gate delay of the buffer G7 and then input from the output section of the buffer G7 to the input section of the buffer G8. The waveform input to the input section of the buffer G8 is delayed by the gate delay of the buffer G8,
It is input from the output section of 8 to the other input section of the selector S3.

Compared to the waveform from the output section of the selector S2 input to one input section of the selector S3, the selector S
The waveform from the output part of the buffer G8 input to the other input part of 3 is delayed by the gate delay of the buffers G5 to G8. Two types of waveforms from the output parts of the selector S2 and the buffer G8 are selected by the selector S3 in accordance with the external selection signal SS3. The waveform selected by the selector S3 is input from the output section of the selector S3 to the other input section of the NAND gate G9.

Compared to the waveform from the output of the buffer G0 input to one input of the NAND gate G9, the waveform from the output of the selector S3 input to the other input of the NAND gate G9 is buffers G1 to G8. It is delayed by the gate delay of at least one of the gates. The waveforms from the output sections of the buffer G0 and the selector S3 are NANDed by the NAND gate G9, and the results are input from the output section of the NAND gate G9 to the output control section of the driver G10.

2 to 5 are time charts showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS. Here, it is assumed that the gate delays of the buffers G1 to G8 are all equal,
Assuming that these gate delays are ΔtG, selectors S1 to S1
3 Let all delays be equal, and let them be Δt
Suppose S.

First, there are two types of waveforms input from the output section of the selector S1 to the input section of the buffer G3, as shown in b and c of FIG. The waveform shown in FIG. 2b is the waveform input from the output section of the buffer G1 through the selector S1. The waveform shown in FIG. 2c is the waveform input from the output section of the buffer G2 through the selector S1.

Comparing these waveforms with the waveform input from the output of the buffer G0 to one input of the NAND gate G9 (see FIG. 2a), the delay of the waveform input via the buffer G1 and the selector S1. Is Δt G + Δt
S '. The delay of the waveform input via the buffers G1 and G2 and the selector S1 is "2ΔtG + Δt.
S '.

Next, there are four types of waveforms input from the output section of the selector S2 to the input section of the buffer G5, as shown in b to e of FIG. The waveform shown in b of FIG. 3 is a waveform input through the buffer G1 and the selectors S1 and S2.
The waveform shown in FIG. 3c has buffers G1 and G2 and a selector S.
It is a waveform input via 1 and S2. The waveform shown in d of FIG. 3 has buffers G1, G3, G4 and a selector S1,
This is a waveform input via S2. The waveform indicated by e in FIG. 3 is a waveform input through the buffers G1 to G4 and the selectors S1 and S2.

Comparing these waveforms with the waveform input from the output of the buffer G0 to one input of the NAND gate G9 (see FIG. 3a), the waveform input via the buffer G1 and the selectors S1 and S2. Delay is "ΔtG
+ 2.DELTA.tS ". The delay of the waveform input through the buffers G1 and G2 and the selectors S1 and S2 is "2.DELTA.tG + 2.DELTA.tS", and the buffers G1 and G3,
The delay of the waveform input via G4 and the selectors S1 and S2 is "3.DELTA.tG + 2.DELTA.tS". Further, the delay of the waveform input via the buffers G1 to G4 and the selectors S1 and S2 is "4.DELTA.tG + 2.DELTA.tS".

On the other hand, the waveform input from the output of the selector S3 to the other input of the NAND gate G9 is shown in FIG.
There are eight types as shown in i. The waveform shown in FIG. 4b is a waveform input via the buffer G1 and the selectors S1 to S3. The waveform shown in FIG. 4c is the waveform input through the buffers G1 and G2 and the selectors S1 to S3.
The waveform shown in d of FIG. 4 is a waveform input through the buffers G1, G3, G4 and the selectors S1 to S3.

The waveform shown in FIG. 4e has buffers G1 to G4.
And the waveforms input via the selectors S1 to S3. The waveform shown in FIG. 4f is the waveform input through the buffers G1, G5 to G8 and the selectors S1 to S3.
The waveform indicated by g in FIG. 4 is the buffers G1, G2, G5 to G8.
And the waveforms input via the selectors S1 to S3. The waveform indicated by h in FIG. 4 is a waveform input through the buffers G1, G3 to G8 and the selectors S1 to S3.
The waveform shown in i of FIG. 4 is the buffers G1 to G8 and the selector S.
This is a waveform input via 1 to S3.

Comparing these waveforms with the waveform input from the output of the buffer G0 to one input of the NAND gate G9 (see FIG. 4a), the waveform input via the buffer G1 and selectors S1 to S3. Delay is "ΔtG
+ 3.DELTA.tS ", and the delay of the waveform input via the buffers G1 and G2 and the selectors S1 to S3 is" 2.DELTA.t.
G + 3ΔtS ". Also, the buffers G1, G3, G4
The delay of the waveform input via the selectors S1 to S3 is "3.DELTA.tG + 3.DELTA.tS", and the buffers G1 to G are
The delay of the waveform input via 4 and the selectors S1 to S3 is "4.DELTA.tG + 3.DELTA.tS".

Further, the delay of the waveform input through the buffers G1, G5 to G8 and the selectors S1 to S3 is "5.DELTA.tG + 3.DELTA.tS", and the buffers G1, G2,
The delay of the waveform input via G5 to G8 and the selectors S1 to S3 is "6ΔtG + 3ΔtS", and the delay of the waveform input via the buffers G1, G3 to G8 and the selectors S1 to S3 is "7ΔtG + 3ΔtS". , The delay of the waveform input through the buffers G1 to G8 and the selectors S1 and S2 is "8.DELTA.tG + 3.DELTA.tS".

Therefore, by controlling the selection operation in the selectors S1 to S3 by the external selection signals SS1 to SS3, eight kinds of output waveforms are obtained from the output part of the NAND gate G9 as shown in a to h of FIG.

The waveform shown in FIG. 5a is the waveform from the output of the buffer G0, the buffer G1 and the selectors S1 to S3.
It is an output waveform obtained from the NAND with the waveform input via. The waveform shown in FIG. 5b is the waveform from the output of the buffer G0, the buffers G1 and G2, and the selectors S1 ...
It is an output waveform obtained from the NAND with the waveform input through S3.

The waveform shown in FIG. 5c is an output waveform obtained from the NAND of the waveform from the output section of the buffer G0 and the waveform input through the buffers G1, G3, G4 and the selectors S1 to S3. The waveform shown in FIG. 5d is an output waveform obtained from the NAND of the waveform from the output section of the buffer G0 and the waveform input through the buffers G1 to G4 and the selectors S1 to S3.

The waveform shown in FIG. 5e is an output waveform obtained from the NAND of the waveform from the output part of the buffer G0 and the waveform input through the buffers G1, G5 to G8 and the selectors S1 to S3. The waveform shown in FIG. 5f is the waveform from the output of the buffer G0 and the buffers G1, G2, G5 ...
It is an output waveform obtained from the NAND with the waveform input via G8 and the selectors S1 to S3.

The waveform indicated by g in FIG. 5 is an output waveform obtained from the NAND of the waveform from the output part of the buffer G0 and the waveform input through the buffers G1, G3 to G8 and the selectors S1 to S3. The waveform indicated by h in FIG. 5 is an output waveform obtained from the NAND of the waveform from the output section of the buffer G0 and the waveform input through the buffers G1 to G8 and the selectors S1 and S2.

Comparing each of these output waveforms, FIG.
The output waveforms shown in b to h are “ΔtG”, “2ΔtG”, “3ΔtG”, and “4” respectively than the output waveforms shown in FIG.
ΔtG ”,“ 5ΔtG ”,“ 6ΔtG ”,“ 7ΔtG ”
It will be delayed only.

In the driver G10, the output state becomes the high impedance state when the signal input to the output control section is at the high level, and the output state becomes the active state when the signal input to the output control section is at the low level. Therefore, the selection operation of the selectors S1 to S3 is controlled by the external selection signals SS1 to SS3.
By controlling with, the NAND gate G9 as described above
It is possible to delay the waveform input from the output part of the above to the input part of the driver G10. That is, the time when the output state of the driver G10 starts to become the high impedance state cannot be changed, but the time when the output state starts to become the active state can be changed in eight steps.

As a result, the driver G connected to the bus
Even if a skew occurs between the 10 output control signals, the time when the output state of the driver G10 starts to be activated can be adjusted by the external selection signals SS1 to SS3, so that the bus fight can be prevented.

In this way, the buffer G0 having one input and one output
To G8 are connected in cascade, and one of the output of the gate of the previous stage and the output of the gate at least one stage before the gate of the previous stage is provided between these buffers G0 to G8 according to the external selection signals SS1 to SS3. Selectors S1 to S3 for selecting and outputting to the gate of the subsequent stage are provided, and the external output control signal and the external output control signal are stored in the buffers G1 to G8 and the selector S1
By taking the NAND with the signal delayed by .about.S3 by the NAND gate G9 and controlling the output of the driver G10 by the output of this NAND gate G9,
Since the delay time of the output control signal of the driver G10 can be adjusted, bus fight can be prevented without degrading the bus performance.

In the embodiment of the present invention, the output control of the driver G10 is performed by the output of the NAND gate G9, but the output control of the driver G10 may be performed by using the output of the AND gate. Not done.

[0035]

As described above, according to the present invention, the output of the preceding stage gate and at least one preceding the preceding stage gate are provided between a plurality of vertically connected gates in accordance with an external signal. Selector is provided for selecting one of the output of the gate of the above and outputting to the gate of the subsequent stage, and the control signal from the outside and the signal delayed from the control signal from the outside by the plurality of gates and the selecting means are simultaneously provided. By controlling the output of the driver by the active signal output from the logic gate when it becomes active, it is possible to adjust the delay time of the output control signal of each driver, without degrading the bus performance. This has the effect of preventing bath fights.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 G0-G8 1-input 1-output buffer G9 2-input NAND gate G10 driver S1-S3 2-input 1-output selector

Claims (1)

[Claims] 1. A driver connected to a bus, a plurality of gates each connected in cascade, and an output of a previous stage gate and a previous stage gate provided between each of the plurality of gates according to an external signal. One or more selection means for selecting one of the output of at least one previous gate and outputting it to the subsequent gate, a control signal from the outside and a control signal from the outside, And a logic gate that outputs an active signal when the signal delayed by the selection means and the signals become active at the same time, and the output control of the driver is performed by the active signal from the logic gate. Bus fight prevention circuit.