JPH07249976A - Noise reducing circuit by simultaneous change output - Google Patents

Abstract

PURPOSE:To obtain a noise reducing circuit capable of suppressing a noise generated due to the drift of reference potential generated by a simultaneous change output from an output circuit in an LSI constituted of MOS transistors(TRs). CONSTITUTION:A processing circuit 10 for delaying data and a delay means 20 for controlling the operation timing of the circuit 10 are connected to the post stage of an output buffer 15. The operation timing of the circuit 10 is switched to normal timing or delay timing based upon control from the means 20 operated from the external.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to suppression of noise caused by simultaneous changes in output buffers of a plurality of MOS LSIs used in transmission equipment.

With the increase in the degree of integration and the increase in the number of pins of LSIs, the number of circuits in which a large number of signals are turned on / off at the same time is increasing.
Due to the simultaneous change of the output signals, an excessive current flows to cause a voltage drop, which causes fluctuation of the reference potential “0V”, so-called noise due to ground bounce. When the reference potential of the ground changes, the margin of the input level of the input terminal near the output terminal disappears, and further, the standard breaks and the internal transistor malfunctions. In order to prevent this, the limit of simultaneous change output is ruled at the time of designing, and the terminal arrangement is consciously decided, but such a phenomenon of noise generation due to LSI ground bounce There is a demand for a circuit that suppresses this.

[0003]

2. Description of the Related Art A conventional technique will be described with reference to FIG. FIG. 7 shows a conventional method for solving such a problem by controlling the rise and fall times of a clock supplied to a D-type flip-flop (hereinafter referred to as D-FF) provided in front of an output buffer and outputting the clock. The simultaneous operation of the buffers is distributed to deal with the ground bounce, or the number of output buffers that change at the same time is limited.

In the case of the example of FIG. 7, 16 data DI0
After fetching the data at the rising edge of the clock supplied to the D-FFs 11 and 12 provided in front of the output buffers 15 and 16 corresponding to 15 to 15, respectively, the clock is further changed for the eight data DI0 to DI7 in the first half. Inverter 2
At the rising edge of the clock obtained by reversing in 7, the D-FF13
Recapture again. The number of output buffers that change at the same time is limited by delaying the phase of data change of the output buffer 15 by 1/2 clock with respect to the data change of the output buffer 16.

[0005]

However, in the case of the circuit as shown in the conventional example, the phase of the data change of the output buffer 15 is delayed by 1/2 clock with respect to the data change of the output buffer 16. Therefore, the output buffer 15
If a large number of output buffers change data in the same phase as at the same time, it will be improved compared to before this measure was taken,
A ground bounce may occur when the output of the output buffer changes, that is, every ½ clock.

Then, the D-FF of the posterior circuit for inputting the data of the output buffer has an intermediate time region (1/2 clock) until the output data of the output buffer is determined and the next output data is transmitted. The clock pulse is started at the time (minute delay) and the rising edge is used to capture the data, but at the time of the data capture, the input should be made at the timing that should have been fixed due to the effect of ground bounce. The data reference level “0V” becomes unstable and rises, and the voltage value (Vil standard) that guarantees the reference level of the received data is divided and the data cannot be taken in, which causes a malfunction. Sometimes.

Similarly, the FF of the latter stage circuit which inputs the output data of the output buffer whose phase is delayed by 1/2 clock is also affected by the ground bounce of the output buffer which does not delay the phase of the output data. Become.

The present invention solves such a problem by M
An object of the present invention is to provide a noise reduction circuit by simultaneous change output that suppresses noise due to ground bounce that occurs due to simultaneous output change of an output buffer of an OS-configured LSI.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 10 is a processing circuit, 15 is an output buffer, and 20 is a delay means.

The present invention is a noise reduction circuit by simultaneous change output that suppresses noise generated due to simultaneous output change of output buffers of a plurality of MOS transistor configuration LSIs, and delays data before the output buffer 15. A processing circuit 10 and a delay means 20 for controlling an operating terminal of the processing circuit 10 are provided.

The object can be achieved by switching the operation timing of the processing circuit 10 under the control of the delay means 20 by an external operation. Here, the processing circuit 10 is composed of a D-type flip-flop 12, a delay circuit 22 for delaying the clock signal by the delay means 20, and a signal supplied to the processing circuit 10 are clock signals, or The delay circuit 22 is composed of a switching device 21 for switching to any of the output signals.

As another method, the processing circuit 10 includes two transfer gates TG1 and TG2, and the delay means 20 controls the operation of one of the transfer gates TG1 and TG2.
You may comprise with.

Further, when a plurality of the output buffers 15 are provided, the plurality of the output buffers 15 are divided into groups that share the ground. Then, the output timing may be changed within the group.

[0014]

According to the present invention, the delay means 20 is provided by externally applying the "H" (or "L") signal to the delay means 20 to the processing circuit 10 for delaying the data in the preceding stage of the output buffer 15. The control signal delayed by a certain amount is sent to the processing circuit 10, and the processing circuit 10 operates at the delayed timing according to the control signal.

Further, the delay means 20 is "L" by an external operation.
When the signal (or “H”) is given, the control signal which is not delayed is sent from the delay means 20 to the processing circuit 10, so that the processing circuit 10 operates at the timing without delay.

As described above, the operation timing of the processing circuit 10 can be switched by applying the "H" (or "L") signal to the delay means 20 by the external operation. Here, in the processing circuit 10, a D-type flip-flop (hereinafter,
D-FF) 12 is used. Also, the delay means 20
Is composed of a delay circuit 22 for delaying the clock signal and a switch 21 for switching the signal supplied to the processing circuit 10 to either the clock signal or the output signal of the delay circuit 22.

With this configuration, the switching device 2
D-FF by switching the switching signal
Since the clock signal supplied to 12 can be switched to a clock delayed by the delay circuit 22 or a clock that is not delayed by the delay circuit 22, the operation timing of the data output from the D-FF 12 can be changed. You can switch.

As another method, the processing circuit 10 may be replaced by two.
Each of the transfer gates TG1 and TG2 is constituted, and the delay means 20 is constituted by a delay addition circuit 40 for controlling one operation of the transfer gates TG1 and TG2 and an inverter 41. By doing so, the transfer gate T is switched between the external control signals "H" and "L".
When either G1 or the transfer gate TG2 is turned on and the transfer gate TG2 for inputting data via the delay adding circuit 40 is turned on, the operation delays by the delay amount in the delay adding circuit 40, so that the output data The output timing can be controlled.

Further, in the case of configuring a plurality of these circuit configurations, the plurality of circuit configurations are divided into groups, for example, for each unit forming 16 bits or for each ground wiring system at the time of LSI design, By changing the output timing for each group to several kinds of output timings, it is possible to suppress noise generation due to simultaneous output changes.

[0020]

EXAMPLE An example will be described with reference to FIGS. 2 is a first embodiment, FIG. 3 is a time chart of the first embodiment, FIG. 4 is a second embodiment of the present invention, FIG. 5 is a time chart of the second embodiment, and FIG. LS as an example
It is a figure which shows the output timing division example of I chip.

In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same elements, and reference numerals 11 and 12 denote D-type flip-flops (DF).
F), 15, 16 and 26 are output buffers (O-BUF).
F), 21 is a 2-to-1 switch (2: 1 SEL), 22 is a delay circuit, 23 is a clock buffer (CK BUFF),
Reference numerals 24 and 25 are input buffers (I-BUFF).

In FIG. 4, 31 and 33 are P-channel transistors, 32 and 34 are N-channel transistors, 40 is a delay adding circuit, and 41 is an inverter. Note that the ∘ symbol shown in FIG. 2 matches the ∘ symbol shown in FIG. The same applies to the relationship between FIG. 4 and FIG.

In FIG. 2, data DI0 to DI7, which are parallel data, are input to the respective D-FFs 11, shot out at the same clock timing, and output. Here, the clock is supplied to the 2: 1 SEL 21. , Is sent to the delay circuit 22 via the output buffer 26, is delayed by a certain amount here, and is supplied to the 2: 1 SEL 21 via the input buffer 25.

The input data DI8 to 15 are input to the D-FF12 in the same manner as DI0 to 7, shot out at the same clock timing and output, or controlled by an external clock selection signal CKSEL.
In the 2: 1 SEL 21, either the delayed clock output from the delay circuit 22 is supplied, and the delayed clock is shot out and output.

The example shown in FIG. 3 shows the latter case,
Since “H” is supplied to the 2: 1 SEL 21 as CKSEL, the 2: 1 SEL 21 selects the clock delayed by the delay circuit 22 and supplies it to the D-FF 12.

Since the D-FF 12 shoots out the data with the delayed clock, the delay circuit 22 for the data of
Of the delay amount of (output buffer 26 and input buffer 2
Delayed amount in 5 is ignored.) Delayed, timing data shown in (5) is sent from the output Q of the D-FF 12.

Here, if the fluctuation of the reference potential "0V" does not occur even if the output data DO8 to 15 are not delayed, "L" (from the HIGH side shown by the solid line to the LOW side shown by the dotted line) as the signal of CKSEL. 2: 1)
By supplying to SEL21, output data DO8-
15 is output at the same timing as DO0 to 7.

FIG. 2 shows an example in which the same operation is performed on the input data DI8 to 15. However, if necessary, the delay circuits 22 having different delay amounts may be used. If you don't need to
It goes without saying that "L" may be supplied as the signal of.

The number of data is not limited to 0 to 15 and may be any number. Next, a second embodiment will be described with reference to FIGS. In FIG. 4, P
Channel transistor 31 and N-channel transistor 3
2 forms a transfer gate TG1 and P
Channel transistor 33 and N-channel transistor 3
And 4 form a transfer gate TG2.

The control signal is the P-channel transistor 31.
, The gate of the N-channel transistor 34, and the gate of the N-channel transistor 32 and the P-channel transistor 33 via the inverter 41.

When "H" is supplied as the control signal, the transfer gate TG1 is turned on and the transfer gate TG2 is turned off. As a result, the input data is transferred to the transfer gate TG as shown in FIG.
The delay amount within 1 is sent as output data.

When "H" is supplied as the control signal,
The transfer gate TG1 is turned off and the transfer gate TG2 is turned on. As a result, the input data undergoes a data delay in the delay adding circuit 40, and as shown in FIG. 5, the output data of the transfer gate TG2 is delayed by the delay adding circuit 40 in comparison with the output data of and is transmitted. To be done.

The circuit configuration may be provided for each data, and the timing may be adjusted as necessary. FIG. 6 shows, as a specific example, for an LSI chip, the output timing is divided into two groups, a normal timing and a delay timing, for each ground group such as a plurality of ground wiring units provided inside the LSI at the time of design, The noise generation due to the change output is suppressed.

Of course, the delay timing group can be further divided into a plurality of groups for use. In any case, the delay amount of the delay circuit in the delay addition circuit does not coincide with the timing of the falling edge of the clock, and the setup / hold time of the D-FF of the subsequent circuit for fetching the output of the output buffer is set. Care must be taken to be satisfied.

[0035]

As described above, by using the technique of the present invention, it is possible to prevent the test failure due to the simultaneous change, which is a problem during the shipping test of the LSI.
We can expect an improvement in SI shipping quality assurance.

Also, in terms of use, even if a problem of ground dounce occurs on the actual board, the number of simultaneous changes can be reduced within the range permitted by the timing.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a first embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of the first embodiment.

FIG. 4 is a second embodiment of the present invention.

FIG. 5 is a diagram showing a time chart of the second embodiment.

FIG. 6 is a diagram showing an example of output timing division of an LSI chip.

FIG. 7 is a diagram showing a conventional example.

[Explanation of symbols]

10 Processing circuit 11, 12, 13 D-type flip-flop (DF
F) 15, 16, 26 Output buffer (O-BUFF) 20 Delay means 21 Two-to-one switch (2: 1SEL) 22 Delay circuit 23 Clock buffer (CK-BUFF) 24, 25 Input buffer (I-BUFF) 27 , 41 Inverter (INV) 31, 33 P-channel transistor 32, 34 N-channel transistor 40 Delay addition circuit TG1, TG2 Transfer gate

Claims (4)

[Claims] 1. A noise reduction circuit for suppressing noise generated by simultaneous output changes of output buffers of a plurality of MOS transistor configuration LSIs, wherein a processing circuit (10) delays data before the output buffer (15). And a delay means (20) for controlling the operation timing of the processing circuit (10), and by the control from the delay means (20) by an external operation,
A circuit for reducing noise by simultaneous change output, characterized in that the operation timing of the processing circuit (10) is switched. 2. The processing circuit (10) according to claim 1, wherein the processing circuit (10) is a D-type flip-flop (1).
2), a delay circuit (22) for delaying a clock signal by the delay means (20), and a signal supplied to the processing circuit (10) is either a clock signal or an output signal of the delay circuit (22). A circuit for reducing noise by simultaneous change output, comprising a switching device (21) for switching between 3. The processing circuit (10) according to claim 1, comprising two transfer gates (T).
G1, TG2), and the delay means (20) is provided in the transfer gate (TG).
1, TG2) is a circuit for reducing noise due to simultaneous change output, which is composed of a delay addition circuit (40) for controlling one operation delay of TG2) and an inverter (41). 4. The claim 1, claim 2, and claim 3, when the output buffer (15) has a plurality, it is divided into groups that share a ground, the change of the output timing in the group. A circuit for reducing noise by simultaneous change output, which is characterized by making possible.