JPH0591984A - Wave generating circuit for mri system - Google Patents

Abstract

PURPOSE:To decrease the amt. of data on wave shapes to be memorized in advance by controlling a counting means by count control bits when each address of a memorizing means 4 is read out and designating the address of the memorizing means by the count output. CONSTITUTION:Bits for wave shape data and count control bits are stored in each address of a memory device 4 and, when each address is read out, a count device 3 is controlled by the count control bits. Count output of the count device 3 is used as an address designating signal of the memory device 4. Successively, advancing count output is generated from the count device 3 and the wave shape data are successively read out and when the procedure reaches an address wherein a count control bit expressing impossibility of count is stored, the output is kept const. As the result, a condition wherein the wave shape data stored in the address of the memory device 4 are outputted is kept.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a waveform generating circuit for generating an envelope waveform of a high frequency signal for excitation and a waveform of a gradient magnetic field pulse in an MRI apparatus (nuclear magnetic resonance tomography apparatus).

[0002]

2. Description of the Related Art In an MRI apparatus, a gradient magnetic field pulse is applied together with a high-frequency signal to selectively excite a predetermined slice plane, or a gradient magnetic field pulse for frequency encoding or phase encoding for position information is encoded in frequency or phase. It is necessary to apply a gradient magnetic field pulse. The envelope waveform of these high-frequency signals and the waveform of the gradient magnetic field pulse are waveforms of relatively low frequency, and for example, the waveform of the gradient magnetic field pulse is as shown in FIG.

As a circuit for generating such a waveform, conventionally, a circuit configured as shown in FIG. 4 may be used. The voltage waveform as shown in FIG. 3 is sampled at a predetermined sampling period to obtain digital data representing the magnitude of the waveform at each time point and stored in the ROM 4 in advance. Then, data is sent to the counter 3 to set an initial value, and then the counter clock signal is counted and counting is performed from the initial value. The output of the counter 3 is sent to the ROM 4 as an address signal, the addresses are sequentially designated, the waveform data is read from the ROM 4 one after another, and the D / A converter 5 converts the waveform data into an analog voltage. Output to a power supply device, etc., to obtain the current to be supplied to. In other words, the counter 3 advances the count to advance the address one by one, and sequentially reads out the data at each time point stored in each address. The data as the initial value sent to the counter 3 designates the first address of the storage address of the waveform data as shown in FIG. 3, and the data as the initial value allows various stored waveform data to be stored. You can specify any of them.

[0004]

However, if all the waveform data from the beginning to the end is written in the ROM and the data is sequentially read out in time as in the prior art, the amount of data to be written in the ROM is enormous. However, there is a problem in that a very large capacity ROM is required.

In particular, the start-up like a gradient magnetic field waveform,
The falling waveforms (waveforms at the t1 and t3 portions in FIG. 3) are the same, and even in the case of a waveform in which the interval t2 between them is simply changed arbitrarily, different waveform data having different t2 portions are different from each other. It is stored as a waveform and has a huge amount of stored data.

In view of the above, an object of the present invention is to provide a waveform generation circuit of an MRI apparatus improved so that the amount of waveform data stored in advance can be reduced.

[0007]

In order to achieve the above object, in the waveform generating circuit of the MRI apparatus according to the present invention, the bits of the waveform data and the count control bits are stored in each address of the storage means, and each address is stored. When is read out, the count means is controlled by the count control bit. The count output of the counting means is used as the address designation signal of the storage means. The count means is given an initial value from the outside, and counts the count clock signal from the initial value. Therefore,
A certain initial value is given, the waveform data and the count control bit are read from the corresponding address of the storage means, and the count control bit controls the counting means to a countable state. Then, since the count output that sequentially advances is generated from the counting means, the waveform data is sequentially read. When the count control bit indicating that counting is not possible reaches the stored address, the counting means does not count, and its output is kept constant. As a result, the state in which the waveform data stored at that address in the storage means is being output is retained. When an arbitrary time has elapsed, give another initial value to the counting means again, read the next address, and write the count control bit that enables counting to that address. Waveform data is sequentially output up to the address where the control bit is stored. Therefore, it is not necessary to spend a large number of addresses to store the same waveform data of a portion where the waveform has a constant value, and the storage capacity can be reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, the present invention is applied to a gradient magnetic field waveform generator. In FIG. 1, each address of the ROM 4 stores a bit of waveform data and a count control bit. That is,
As shown in FIG. 2, the most significant bit of each address is the count control bit, and the H or L count control bit is written therein.
The bits other than the most significant digit are the bits of the waveform data.

When a certain address is designated and the waveform data bit and the count control bit are read out, the count control bit is sent to the counter 3, which controls the counter 3. That is, when the count control bit is H, the counter 3 is in a countable state of the count clock signal, and when it is L, it is in a countable state.

Data (for example, 0) is output from the CPU 1, and the data is latched by the latch circuit 2 by the write signal from the CPU 1 and sent to the counter 3. CP
When a load signal is generated from U1, the output of the latch circuit 2 is loaded into the counter 3. As a result, the initial value of the counter 3 is set so that the count value corresponds to the first address (0 as shown in FIG. 2) of the rising waveform of FIG. Since the count control bit of H is written in this 0 address, the counter 3 counts the count clock signal and sequentially advances the count value from the initial value 0 to 1, 2, .... Address 1,
Since the count control bits of 2, ... Are H,
Counting is performed sequentially.

The sequentially read waveform data is converted into an analog voltage value by the D / A converter 5, and the CPU 1
The gain is adjusted through the gain control amplifier 6 controlled by the above, and then sent to the gradient power supply device.

It is assumed that the address n is read in this way. At this address n, the count control bit is L. Therefore, when this address is read, the counter 3 is in the count disabled state and stops counting the count clock signal. Therefore, after that, the same count value output continues, and the waveform data output from the ROM 4 continues to be stored in the address n. Therefore, the analog voltage value sent to the gradient power supply device also maintains the same value.

Here, assuming that the data of the rising waveform of the period t1 of FIG. 3 is stored from address 0 to n, the value at the end time of t1 is maintained after this waveform is sequentially generated. Become. Next, after an arbitrary period t2 has elapsed, when data for designating the first address n + 1 of the falling waveform is sent from the CPU 1 to the counter 3 via the latch circuit 2 at a desired timing, the count control bit of this address is sent. And waveform data are read. Since the count control bit is H at the address after this address n + 1, the counter 3
And the waveform data of the falling waveform (period t3) is sequentially read. At the last address m of this falling waveform, the count control bit becomes L
Therefore, the counting operation is stopped, and the output voltage is
It is kept in the last state of 3.

Therefore, it is not necessary to store the waveform data of the period t2 having the same voltage value, and the amount of data to be written in the ROM 4 is greatly reduced. Further, the period t2 can be lengthened or shortened by arbitrarily setting the timing at which the CPU 1 sends the data corresponding to the address number n + 1 to the counter 3 and loads the data. Therefore, by storing some data groups of the rising waveform and the falling waveform, it is possible to easily create waveforms having different widths (the period t2 is arbitrarily determined) having different rising and falling waveforms. ..

In the above, as shown in FIG. 3, there is a period t2 in which the same voltage value is maintained after the start-up period t1 ends,
Although the case where the waveform has a falling waveform in the period t3 has been described, the present invention is applicable to not only such a waveform but also a waveform that maintains a constant value for a certain period of time.

[0016]

As described above with reference to the embodiments,
According to the waveform generating circuit of the MRI apparatus of the present invention, it is possible to easily create a waveform having a constant value output of an arbitrary length while reducing the amount of data written in the storage means.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating storage in a ROM.

FIG. 3 is a time chart showing waveforms.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 1 CPU 2 Latch circuit 3 Counter 4 ROM 5 D / A converter 6 Gain control amplifier

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Claims (1)

[Claims] 1. A storage unit in which a data bit representing waveform data and a count control bit are stored for each address, and a count clock signal controlled by the count control bit to count the count clock signal, thereby providing an external signal. A waveform generating circuit for an MRI apparatus, which comprises: counting means for counting from a given initial value and outputting the count output as an address designation signal of the storage means.