JPH0590494A - Semiconductor device - Google Patents

Abstract

PURPOSE:To secure the enough capacity of a capacitor regardless of the reduction of occupied area by constituting at least one side of a first electrode and a second electrode out of p-type silicon. CONSTITUTION:A capacitor is constituted by stacking a p+-polycrystalline silicon film 108 as a lower electrode (storage node) directly on the source and drain region 105 consisting of the p-diffusion layer of a p-channel MOSFET, and stacking a tantalum film 109 as a capacitor insulating film, and a tantalum film 110 as an upper electrode in order, thus a stacked memory cell structure of DRAM is made. P-type silicon can take the height of the energy barrier to an insulating film larger than n-type silicon, so it becomes possible to suppress the lead current. Accordingly, a capacitor, which has high capacitor capacity and high charge tenacity, can bed obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a capacitor structure in a DRAM or the like.

[0002]

2. Description of the Related Art One of semiconductor devices is a DRA which combines a capacitor and a transistor to store information.
There is M (Dynamic Random Access read write Memory).

In such a device, a capacitor is formed by sandwiching a capacitor insulating film between a semiconductor substrate and a capacitor electrode. Conventionally, a silicon oxide film is used as this capacitor insulating film, but in order to compensate for the decrease in capacitor capacitance due to miniaturization with the rapid progress of high integration and large capacity in recent years, a dielectric oxide film is used. A material having a high rate has been studied, and improvements such as using a laminated film of a silicon nitride film and a silicon oxide film have been attempted.

However, it is necessary to use a material having a larger dielectric constant in order to cope with the future increase in the capacity of the capacitor due to the further miniaturization of the area occupied by the capacitor. From these requirements, it has been considered to use a tantalum oxide film, which is a material having a dielectric constant about 7 times larger than that of a silicon oxide film, as an insulating film.

In particular, the dielectric constant of tantalum oxide is about 7 times as large as that of silicon oxide, so that it is an expected material.

However, since the band gap of tantalum oxide is as small as about 4.7 eV, there is a problem that the leak current is large. In order to suppress such leakage current, for example, at the interface between the underlying silicon and tantalum oxide,
A method of providing a silicon oxide film or a silicon nitride film having a larger band gap has been proposed.

However, in the limit of film thickness,
The interposition of silicon oxide or silicon nitride having a small dielectric constant leads to a reduction in the capacitance of the capacitor.

As described above, in general, since such a high dielectric material is a compound containing a metal, there is a problem that the forbidden band width is small in spite of having a high dielectric constant and the leak current is essentially large. is there. Therefore, the performance as an original insulating film is remarkably deteriorated, the charge holding ability of the capacitor is lowered, and the reliability of the DRAM or the like is impaired.

As described above, in the conventional capacitor structure,
It was extremely difficult to suppress the leak current while securing a sufficient capacitor capacity.

[0010]

As described above, in the conventional capacitor, it is extremely difficult to suppress the leak current while securing a sufficient capacitor capacity.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable capacitor that can secure a sufficient capacitor capacity in spite of a reduction in occupied area. To do.

[0012]

Therefore, in the first aspect of the present invention, there is provided a capacitor having a first electrode, a second electrode, and a capacitor insulating film made of a metal oxide film formed between these electrodes. In the semiconductor device provided, at least one of the first electrode and the second electrode is made of p-type silicon.

According to a second aspect of the present invention, a switching transistor formed of a p-channel type MOSFET having a p-type region formed on an n-type silicon substrate as a source / drain region, and a p-type transistor connected to one of the source / drain regions. A capacitor having a first electrode made of a silicon layer, a second electrode, and a capacitor insulating film made of a metal oxide film formed between these electrodes is provided.

[0014]

According to the above structure, the leak current can be suppressed in the capacitor using the metal oxide film as the capacitor insulating film.

Therefore, it is possible to provide a capacitor having an excellent charge retention ability with a sufficient capacitance and a small leak current.

This is due to the following action.

In general, a material having a higher dielectric constant has a smaller band gap. And the smaller the forbidden band,
A large leak current flows when a voltage is applied, and the performance as an insulator deteriorates.

This is because the height of the energy barrier between the electrode, that is, the conductor and the insulating film becomes small.

Therefore, in order to have a high dielectric constant and a large energy barrier height between the electrode and the insulating film,
It is necessary to use a material having a high work function as the electrode material.

Therefore, when silicon is used as at least one electrode, the p-type has a deeper Fermi level than the n-type, so that the work function is substantially large.

In other words, the p-type can have a larger energy barrier height with the insulating film than the n-type.

This is shown in FIGS. 4 (a) and 4 (b) for the case where a tantalum oxide film is used as an insulating film. Here, tungsten is used as the upper electrode.

However, when a metal oxide film such as tantalum, which has an oxygen affinity lower than that of silicon, is in direct contact with silicon, the silicon is oxidized after a high temperature process and, on the contrary, the metal oxide film is reduced. In this case, it is effective to dispose a thin silicon nitride film or the like at the metal oxide film / silicon interface as a barrier layer for preventing the reaction.

According to the second aspect of the present invention, since the transistor connected to the storage node electrode of the capacitor is composed of a p-channel MOSFET, it is possible to obtain a DRAM having a simple structure and a small leak current.

That is, as described above, it is advantageous to use p-type silicon or polycrystalline silicon for the storage node for storing charges in the DRAM, but at this time, the transistor formed on the silicon surface is used. The use of a p-channel transistor that transfers and receives charges through a p-type region has an advantage that it can be formed without being structurally complicated. That is, it is possible to directly form a capacitor on the p-type layer by using the p-type layer as a source / drain region formed on the silicon surface as a storage node.
A type of polycrystalline silicon may be formed and used as a storage node. On the other hand, when an n-channel transistor is used, a metal layer for contact needs to be provided at the n / p interface in order to use p-type silicon for the storage node, which significantly complicates the manufacturing process. There is also.

In this way, it is possible to obtain a capacitor having a high capacitance and a high charge retention capability, and a DRAM having a simple structure and high reliability can be obtained.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In the first embodiment of the present invention, the p channel M
Source / drain region 1 consisting of p- diffusion layer of OSFET
05, a p + polycrystalline silicon film 108 as a lower electrode (storage node), a tantalum oxide film 109 as a capacitor insulating film, and a tungsten film 110 as an upper electrode are sequentially laminated directly on top of each other to form a capacitor. The feature is that a DRAM having a structure is formed. 1 (a) to 1 (e) are manufacturing process diagrams thereof.

First, as shown in FIG. 1 (a), the specific resistance 10
An element isolation insulating film 102 is formed in a (100) n-type silicon substrate 101 of about Ω · cm by a normal LOCOS method. Then, a silicon oxide layer 103 having a film thickness of 15 nm to be a gate insulating film and a first p + polycrystalline silicon layer 104 having a thickness of 300 nm to be a gate electrode are deposited by a thermal oxidation method, and these are deposited by a photolithography method and a reactive ion etching method. Is patterned to form a gate insulating film 103 and a gate electrode 104. Further, by using this gate electrode 104 as a mask, boron ions are ion-implanted to form a source / drain of a p- type diffusion layer 105 in a self-aligned manner.
A drain region is formed to form a MOSFET as a switching transistor.

Further, as shown in FIG. 1 (b), a silicon oxide film 106 having a film thickness of about 150 nm is deposited on the entire surface by a CVD method, and then a photolithography method and a reactive ion etching are performed to store the silicon oxide film 106. A di-node contact 107 is formed. After that, as shown in FIG. 1C, after depositing a second p + polycrystalline silicon film 108 having a film thickness of 80 nm on the entire surface, by photolithography and chemical dry etching (isotropic etching), Pattern.

Further, as shown in FIG. 1 (d), the upper layer is formed by reactive sputtering or CVD.
The tantalum oxide film 109 is formed to have a thickness of 20 to 30 nm, for example.

Finally, as shown in FIG. 1 (e), a 100 nm-thickness tungsten film 110 is formed on the entire surface as a capacitor upper electrode, and patterning is performed using a normal photolithography method to form a memory cell. Form. After this, steps of forming a passivation film, Al wiring, etc. are continued, but are omitted here.

The leakage current characteristic of the DRAM thus formed is shown by a curve a in FIG. For comparison, an n-channel MOSFET was used as a conventional example, an n + polycrystalline silicon film was formed as a storage node electrode so as to be connected to the source / drain region, and a tantalum oxide film was used as a capacitor insulating film in a single-layer structure. The leakage current characteristic in this case is shown by the curve b. From these comparisons as well, it can be seen that the DRAM of the embodiment of the present invention has significantly reduced leakage.

Although the capacitor insulating film 109 made of tantalum oxide is formed directly on the p + polycrystalline silicon film 108 in the above-mentioned embodiment, the film quality is deteriorated because tantalum oxide is reduced by silicon at high temperature. I will leave.

By forming the bit line prior to forming the capacitor, it is possible to prevent a high temperature process from being performed after forming the capacitor.

However, since it is often necessary to go through a high temperature process, it is necessary to prevent the tantalum oxide from being reduced by silicon.

As a method of preventing reduction of this tantalum oxide,
An extremely thin silicon nitride film may be interposed between tantalum oxide and silicon.

Example 2 As a second example of the present invention, an example in which an extremely thin silicon nitride film is interposed between tantalum oxide and silicon will be described.

3 (a) to 3 (e) are manufacturing process diagrams thereof.

In this example, an extremely thin silicon nitride film 209 having a film thickness of about 1 nm is interposed between the p + polycrystalline silicon layer 208 serving as a storage node electrode and the tantalum oxide film 210 serving as a capacitor insulating film. The silicon is prevented from being reduced. This silicon nitride film 209 is a p + polycrystalline silicon layer 208.
Is formed by nitriding the surface of.

The rest is formed exactly as in the first embodiment.

First, as shown in FIG. 3A, the specific resistance 10
An element isolation insulating film 202 is formed by a normal LOCOS method in a (100) n-type silicon substrate 201 of about Ω · cm. Then, a silicon oxide layer 203 having a film thickness of 200 nm to be a gate insulating film and a first p + polycrystalline silicon layer 204 having a thickness of 300 nm to be a gate electrode are deposited by a thermal oxidation method, and these are deposited by a photolithography method and a reactive ion etching method. The gate insulating film 203.
And the gate electrode 204 is formed. Furthermore, this game
The boron ion is ion-implanted using the transparent electrode 204 as a mask, and the source / drain is composed of the p- type diffusion layer 205 in a self-aligned manner.
A drain region is formed to form a MOSFET as a switching transistor.

Further, as shown in FIG. 3 (b), a silicon oxide film 206 having a film thickness of about 150 nm is deposited on the entire surface by a CVD method, and then a storage is performed by a photolithography method and reactive ion etching. A di-node contact 207 is formed. Then, as shown in FIG. 3C, a second p + polycrystalline silicon film 208 having a film thickness of 80 nm is deposited on the entire surface, and then patterned by photolithography and chemical dry etching (isotropic etching). To do.

Thereafter, as shown in FIG. 3 (d), the surface of the p + polycrystal silicon layer 208 is nitrided by performing a heat treatment at 600 ° C. for 60 minutes, for example, in an ammonia atmosphere to have a film thickness of about 1 nm. A silicon nitride film 209 is formed. Further, on this upper layer, reactive sputtering method or C
The tantalum oxide film 210 is, for example, 20 to 3 by the VD method.
Form 0 nm. The heat treatment in the ammonia atmosphere described above may be performed by appropriately changing the temperature and the time. For example, when the temperature is raised to about 950 ° C. to perform heat treatment, RTA (Rapid T
hermal annealing).

Finally, as shown in FIG. 3 (e), a tungsten film 211 having a film thickness of 200 nm is formed on the entire surface as a capacitor upper electrode, and then patterned by a normal photolithography method to form a memory cell. Form. After this, steps of forming a passivation film, Al wiring, etc. are continued, but are omitted here.

Also in this case, a DRAM having a small leak current
Can be obtained.

In each of the above-described embodiments, an example in which tantalum oxide is used as the capacitor insulating film has been described, but other metal oxide films can be used.

For example, the capacitor insulating film is not limited to a single-layer film, but may be a three-layer film of tantalum oxide film / titanium oxide film / tantalum oxide film, a two-layer film, or a laminated film of four or more layers. Further, the material for the capacitor insulating film is not limited to the combination of tantalum oxide and titanium oxide, and other single layer films such as hafnium oxide film, yttrium oxide film, zirconium oxide (ZrO ₂ ) film, tantalum oxide film, etc. (TaO ₂ ) and strontium titanate film (Sr
TiO ₃ ), a yttrium oxide film (Y ₂ O ₃ ) and a lead titanate film (PbTiO ₃ ), and the like can be appropriately selected. For example, a three-layer structure film of zirconium oxide (ZrO ₂ ) film-titanium oxide film-zirconium oxide film is formed as a capacitor insulating film directly on the polycrystalline silicon film 208 in the above embodiment, and p + polycrystal is used as an upper electrode. A silicon film may be used. Further, p + polycrystalline silicon may be used as the lower electrode, and a metal film such as a tungsten film may be used as the upper electrode. Further, three-layer structure film of zirconium oxide film-titanium oxide film-hafnium oxide film, three-layer structure film of hafnium oxide film-titanium oxide film-hafnium oxide film, three-layer structure of hafnium oxide film-titanium oxide film-zirconium oxide film Membranes are also effective. Further, although the tungsten film is used as the upper electrode of the capacitor, it is not necessarily limited to these, and it can be appropriately changed within the range of satisfying the conditions of the present invention such as metal or metal alloy.

Furthermore, the silicon nitride film in the second embodiment is for preventing the reaction between the p + polycrystalline silicon and the capacitor insulating film due to the high temperature treatment, and the high temperature process can be avoided. In this case, or when a low-reactivity substance such as a hafnium oxide film, a yttrium oxide film, or a zirconium oxide film is used for the capacitor insulating film, the nitriding step for forming silicon nitride is unnecessary.

In addition, in these embodiments, the DRAM having the laminated capacitor structure has been described, but it goes without saying that the present invention can also be applied to a DRAM having a planar structure or a trench structure.

[0051]

As described above, according to the capacitor of the present invention, when the metal oxide film is used as the capacitor insulating film, the p-type insulating film is more preferable as the polycrystalline silicon electrode than the n-type. The height of the energy barrier between and can be made large, and even at the time of high integration, the leakage current can be reduced, and the charge retention ability can be improved while maintaining a sufficient capacitor capacitance.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a DRAM having a stacked memory cell structure according to a first embodiment of the present invention.

FIG. 2 is a comparative diagram showing leakage currents of a DRAM capacitor according to an embodiment of the present invention and a conventional DRAM capacitor.

FIG. 3 is a manufacturing process diagram of a DRAM having a stacked memory cell structure according to a second embodiment of the present invention.

FIG. 4 is a band diagram of p + polycrystalline silicon / tantalum oxide / tungsten and n + polycrystalline silicon / tantalum oxide / tungsten.

[Explanation of symbols]

 101 n-type silicon substrate 102 element isolation insulating film 103 gate insulating film 104 gate electrode 105 p-type diffusion layer 106 interlayer insulating film 107 storage node contact 108 p + type polycrystalline silicon layer (lower electrode) 109 tantalum oxide Film 110 Tungsten film (upper electrode) 201 n-type silicon substrate 202 element isolation insulating film 203 gate insulating film 204 gate electrode 205 p-type diffusion layer 206 interlayer insulating film 207 storage node contact 208 p + type polycrystalline silicon Layer (lower electrode) 209 Silicon nitride film 210 Tantalum oxide film 211 Tungsten film (upper electrode)

Claims (2)

[Claims] 1. A semiconductor device comprising a capacitor having a first electrode, a second electrode, and a capacitor insulating film made of a metal oxide film formed between these electrodes, wherein the first electrode At least one of the second electrode and the second electrode is made of p-type silicon. 2. A p-channel type MOSF having a p-type region formed on an n-type silicon substrate as a source / drain region.
A switching transistor made of ET and p electrically connected to one of the source / drain regions.
A semiconductor device comprising: a capacitor having a first electrode made of a silicon layer, a second electrode, and a capacitor insulating film made of a metal oxide film formed between these electrodes. ..