JPH0590435A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0590435A JPH0590435A JP25147591A JP25147591A JPH0590435A JP H0590435 A JPH0590435 A JP H0590435A JP 25147591 A JP25147591 A JP 25147591A JP 25147591 A JP25147591 A JP 25147591A JP H0590435 A JPH0590435 A JP H0590435A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- substrate
- integrated circuit
- hybrid integrated
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半田ランドを下層導体に
より基板上に形成する混成集積回路に係り、特に、半田
ランドを改良した混成集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit in which a solder land is formed on a substrate by a lower layer conductor, and more particularly to a hybrid integrated circuit having an improved solder land.
【0002】[0002]
【従来の技術】従来、この種の混成集積回路の一例とし
ては図3に示すものがある。この混成集積回路1はセラ
ミックス製等の基板2上に、例えば左右一対の半田ラン
ド3a,3bの複数対を下層導体により形成し、これら
一対の半田ランド3a,3b間に、チップ部品4等の表
面実装用部品の一対の接続端子4a,4bを載せ、リフ
ロー半田により半田付けしている。2. Description of the Related Art Conventionally, an example of this type of hybrid integrated circuit is shown in FIG. The hybrid integrated circuit 1 is formed by forming a plurality of pairs of left and right solder lands 3a and 3b on a substrate 2 made of ceramics or the like by a lower layer conductor, and inserting a chip component 4 or the like between the pair of solder lands 3a and 3b. A pair of connection terminals 4a and 4b of the surface mounting component are placed and soldered by reflow soldering.
【0003】したがって、半田ランド3a,3bが下層
導体パターンと同じ下層導体から成るので、半田ランド
3a,3bや下層導体パターンの印刷時のずれが防止さ
れ、高密度に配線することができる。Therefore, since the solder lands 3a and 3b are made of the same lower layer conductor as the lower layer conductor pattern, the solder lands 3a and 3b and the lower layer conductor pattern are prevented from being displaced during printing, and wiring can be performed at a high density.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の混成集積回路1ではチップ部品が軽量である
場合には、リフロー半田時に、溶融する半田の表面張力
や流動力により、半田ランドからずれることがある。However, in such a conventional hybrid integrated circuit 1, when the chip component is light in weight, it is displaced from the solder land due to the surface tension and the fluid force of the melting solder at the time of reflow soldering. Sometimes.
【0005】また、図4に示すように、チップ部品が例
えばRFCコイル5等のように、その左右一対の接続端
子5a,5bの図中下面が、半田ランド3a,3bの上
面よりも上方にあるとき、つまり、基板2の上面からR
FCコイル5の各接続端子5a,5bの上面までの高さ
aが、半田ランド3a,3bの高さ(膜厚)bよりも高
く、両者間にギャップgがあるときには、RFCコイル
5自体が基板2上で自立してしまう上に、半田付け面積
が減少する。Further, as shown in FIG. 4, the lower surface of the pair of left and right connection terminals 5a and 5b of the chip component is higher than the upper surfaces of the solder lands 3a and 3b, as in the case of the RFC coil 5 or the like. At some point, that is, from the top surface of substrate 2 R
When the height a to the upper surface of each connection terminal 5a, 5b of the FC coil 5 is higher than the height (film thickness) b of the solder lands 3a, 3b and there is a gap g between them, the RFC coil 5 itself is In addition to being self-supporting on the substrate 2, the soldering area is reduced.
【0006】このために、半田ランド3a,3bに、接
続端子5a,5bを半田6により固着し難い上に、その
固着位置がずれ易いという課題がある。Therefore, there is a problem that the connection terminals 5a and 5b are not easily fixed to the solder lands 3a and 3b by the solder 6, and the fixing positions are easily displaced.
【0007】そこで本発明はこのような事情を考慮して
なされたもので、その目的は半田ランドに半田付けしよ
うとするチップ部品が軽量であるとき、または、チップ
部品の接続端子の高さが半田ランドよりも高いときで
も、これらチップ部品を半田ランドに確実に半田付けす
ることができる混成集積回路を提供することにある。The present invention has been made in view of such circumstances, and its purpose is to reduce the weight of a chip component to be soldered to a solder land or to increase the height of a connection terminal of the chip component. An object of the present invention is to provide a hybrid integrated circuit capable of reliably soldering these chip parts to the solder land even when the chip land is higher than the solder land.
【0008】[0008]
【課題を解決するための手段】本発明は前記課題を解決
するために次のように構成される。The present invention is configured as follows in order to solve the above-mentioned problems.
【0009】本願の請求項1に記載の発明(以下、第1
の発明という)は、基板上に、半田ランドを下層導体に
より形成する混成集積回路において、前記基板と前記半
田ランドの一部との間に、誘電体層を介在させたことを
特徴とする。The invention according to claim 1 of the present application (hereinafter, referred to as the first
In a hybrid integrated circuit in which a solder land is formed by a lower layer conductor on a substrate, a dielectric layer is interposed between the substrate and a part of the solder land.
【0010】また本願の請求項2に記載の発明(以下、
第2の発明という)は、基板上に、半田ランドを下層導
体により形成する混成集積回路において、前記半田ラン
ドの一部上に、上層導体層を積層すると共に、この上層
導体層の一部と前記半田ランドとの間に、電気絶縁体層
を介在させたことを特徴とする。The invention according to claim 2 of the present application (hereinafter,
According to a second invention), in a hybrid integrated circuit in which a solder land is formed by a lower conductor on a substrate, an upper conductor layer is laminated on a part of the solder land, and a part of the upper conductor layer is formed. An electrical insulator layer is interposed between the solder land and the solder land.
【0011】[0011]
【作用】〈第1の発明〉基板と半田ランドの一部との間
に誘電体層を介在させているので、その誘電体層の膜厚
の分だけ半田ランドの一部が嵩上げされる。<First Invention> Since the dielectric layer is interposed between the substrate and a part of the solder land, part of the solder land is raised by the film thickness of the dielectric layer.
【0012】したがって、この一対の半田ランドの嵩上
げ部上に、RFCコイル等の自立し易いチップ部品の接
続端子を載せることにより、その自立を阻止した状態で
半田付けすることができるので、その半田付けを確実に
することができる上に、チップ部品がずれるのを防止す
ることができる。Therefore, by mounting the connection terminals of the chip parts such as the RFC coil, which are easily self-supporting, on the raised parts of the pair of solder lands, the soldering can be performed in a state where the self-supporting is prevented. The attachment can be ensured, and the chip components can be prevented from being displaced.
【0013】〈第2の発明〉半田ランドはその一部上に
電気絶縁体層と上層導体層の2層を積層して、一部を嵩
上げしているので、この一対の嵩上げ部間にチップ部品
を載置することにより、このチップ部品を軸方向両側か
ら挟み込むように半田付けすることができるので、チッ
プ部品が軽量であっても、リフロー半田時にずれるのを
防止することができ、確実に半田付けすることができ
る。<Second Invention> Since the solder land is formed by laminating two layers of an electric insulator layer and an upper conductor layer on a part of the solder land and partially raising it, the chip is placed between the pair of raised portions. By mounting the parts, this chip part can be soldered so as to be sandwiched from both sides in the axial direction, so even if the chip part is lightweight, it is possible to prevent it from shifting during reflow soldering, and to ensure Can be soldered.
【0014】[0014]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【0015】図1は本願第1の発明の一実施例の部分縦
断面図であり、図において、混成集積回路11は混成集
積回路基板12上に、例えば図中左右一対の半田ランド
13a,13bの複数対を下層導体により形成してい
る。FIG. 1 is a partial vertical cross-sectional view of an embodiment of the first invention of the present application, in which a hybrid integrated circuit 11 is mounted on a hybrid integrated circuit substrate 12, for example, a pair of left and right solder lands 13a, 13b in the figure. Are formed by the lower layer conductor.
【0016】そして、一対の半田ランド13a,13b
の一部、例えば内端部13a1,13b1と基板12との間
には左右一対の誘電体層14a,14bをそれぞれ介在
させて、両内端部13a1,13b1を嵩上げしている。Then, a pair of solder lands 13a, 13b
A pair of left and right dielectric layers 14a and 14b are respectively interposed between a part of each of the inner end portions 13a1 and 13b1 and the substrate 12 to raise the inner end portions 13a1 and 13b1.
【0017】誘電体層14a,14bの膜厚は、例えば
RFCコイル15等、基板12上で自立し易いチップ部
品の一対の接続端子15a,15bを、自立しない高さ
を設定し得る厚さに設定されている。The thickness of the dielectric layers 14a and 14b is set such that the height of the pair of connection terminals 15a and 15b of the chip component such as the RFC coil 15 which is easily self-supporting on the substrate 12 can be set so as not to be self-supporting. It is set.
【0018】したがって本実施例によれば、一対の半田
ランド13a,13bの嵩上げされた両内端部13a1,
13b1間に例えばRFCコイル15の一対の接続端子1
5a,15bを架け渡すことにより、RFCコイル15
の自立を防止した状態で、半田16によりリフロー半田
することができる。Therefore, according to the present embodiment, the raised inner ends 13a1, 13a1 of the pair of solder lands 13a, 13b,
For example, a pair of connection terminals 1 of the RFC coil 15 is provided between 13b1.
The RFC coil 15 is formed by bridging 5a and 15b.
It is possible to perform reflow soldering with the solder 16 while preventing the self-standing.
【0019】このために、RFCコイル15の半田付け
を確実にし、しかも、リフロー半田時に溶融する半田の
表面張力等によりずれるのを防止することができる。Therefore, it is possible to ensure soldering of the RFC coil 15 and prevent the RFC coil 15 from being displaced due to the surface tension of the molten solder during the reflow soldering.
【0020】図2は本願第2の発明の一実施例の一部省
略縦断面図であり、図において、混成集積回路21はセ
ラミックス製等の基板22上に、例えば図中左右一対の
半田ランド23,24の複数対を下層導体により形成し
ている。FIG. 2 is a partially omitted vertical sectional view of an embodiment of the second invention of the present application. In the figure, a hybrid integrated circuit 21 is provided on a substrate 22 made of ceramics or the like, for example, a pair of left and right solder lands in the figure. Plural pairs 23 and 24 are formed by the lower conductor.
【0021】そして、一対の半田ランド23,24の各
一部、例えば外端部23a,24a上に、上方に凸の突
出部25,26を突設している。各突出部25,26は
半田ランド23,24の外端部23a,24a上に、上
層導体層27,28を積層すると共に、この上層導体層
27,28の各中間部と半田ランド23,24との間
に、所要膜厚の電気絶縁体層29,30を介在させて構
成されている。Then, projecting portions 25 and 26 projecting upward are provided on the respective parts of the pair of solder lands 23 and 24, for example, on the outer end portions 23a and 24a. The projecting portions 25, 26 are formed by laminating the upper conductor layers 27, 28 on the outer end portions 23a, 24a of the solder lands 23, 24, and the intermediate portions of the upper conductor layers 27, 28 and the solder lands 23, 24. And the electric insulator layers 29 and 30 having a required film thickness, are interposed between the two.
【0022】また、比較的軽量のチップ部品31を基板
12上に実装するときは、このチップ部品31の左右一
対の接続端子31a,31bを、一対の半田ランド2
3,24の両突出部25,26間の一段低い内端部上に
載置し、リフロー半田等により半田32で固着する。When mounting a relatively lightweight chip component 31 on the substrate 12, the pair of left and right connecting terminals 31a and 31b of the chip component 31 are connected to the pair of solder lands 2.
It is placed on the lower inner end portion between the projecting portions 25 and 26 of 3, 24 and fixed by the solder 32 by reflow soldering or the like.
【0023】したがって本実施例によれば、チップ部品
31の一対の接続端子31a,31bの両外側面を、そ
の軸方向の外方両側から、左右一対の半田ランド23,
24の両突出部25,26により挟み込むように固着す
ることができる。Therefore, according to the present embodiment, the outer side surfaces of the pair of connection terminals 31a, 31b of the chip part 31 are provided on both outer sides in the axial direction from the pair of left and right solder lands 23,
It can be fixed so as to be sandwiched by both projecting portions 25 and 26 of 24.
【0024】したがって、リフロー半田時に溶融する半
田の表面張力等により、軽量のチップ部品31が半田ラ
ンド23,24からずれるのを防止し、確実に固着する
ことができる。Therefore, it is possible to prevent the lightweight chip component 31 from being displaced from the solder lands 23 and 24 due to the surface tension of the solder that melts during the reflow soldering, and to firmly fix the chip component 31.
【0025】[0025]
【発明の効果】以上説明したように本願第1の発明は、
基板と半田ランドの一部との間に誘電体層を介在させた
ので、この半田ランドの一部を嵩上げすることができ
る。As described above, the first invention of the present application is
Since the dielectric layer is interposed between the substrate and a part of the solder land, a part of the solder land can be raised.
【0026】したがって、一対の半田ランドの嵩上げ部
間に自立し易いチップ部品を架け渡すことにより、その
自立を防止した状態で半田付けすることができ、その半
田付けを確実にすることができる上に、リフロー半田時
のずれを防止することができる。Therefore, by bridging the chip parts, which are easily self-supporting, between the raised portions of the pair of solder lands, soldering can be performed while the self-supporting is prevented, and the soldering can be ensured. In addition, it is possible to prevent the displacement during reflow soldering.
【0027】また、本願第2の発明は、半田ランドの一
部上に電気絶縁体層と上層導体層とを積層して突出部と
を形成するので、一対の半田ランドの両突出部間に比較
的軽量のチップ部品を載せて、半田付けすることによ
り、チップ部品の軸方向外側面を一対の突出部により両
側から挟み込むように半田付けすることができるので、
その半田付けを確実にすることができる上に、リフロー
半田時のずれを防止することができる。Further, according to the second invention of the present application, since the projecting portion is formed by laminating the electric insulator layer and the upper conductor layer on a part of the solder land, the projecting portion is formed between the pair of solder lands. By mounting a relatively lightweight chip component and soldering it, the axial outer surface of the chip component can be soldered so as to be sandwiched from both sides by a pair of protrusions.
In addition to ensuring the soldering, it is possible to prevent misalignment during reflow soldering.
【図1】本願第1の発明の一実施例の要部縦断面図。FIG. 1 is a longitudinal sectional view of an essential part of an embodiment of the first invention of the present application.
【図2】本願第2の発明の一実施例の一部を省略して示
す部分縦断面図。FIG. 2 is a partial vertical cross-sectional view showing a part of an embodiment of the second invention of the present application with a part thereof omitted.
【図3】従来例の一例を示す正面図。FIG. 3 is a front view showing an example of a conventional example.
【図4】他の従来例の一部の部分縦断面図。FIG. 4 is a partial vertical sectional view of a part of another conventional example.
11,21 混成集積回路 12,22 基板 13a,13b,23,24 一対の半田ランド 13a1,13b1 一対の半田ランドの内端部 14a,14b 誘電体層 15 RFCコイル 16,32 半田 25,26 上層導体層 29,30 電気絶縁体層 31 チッブ部品 11, 21 Hybrid integrated circuit 12, 22 Substrate 13a, 13b, 23, 24 Pair of solder lands 13a1, 13b1 Pair of inner ends of solder land 14a, 14b Dielectric layer 15 RFC coil 16, 32 Solder 25, 26 Upper layer conductor Layer 29,30 Electrical insulator layer 31 Chip parts
Claims (2)
形成する混成集積回路において、前記基板と前記半田ラ
ンドの一部との間に、誘電体層を介在させたことを特徴
とする混成集積回路。1. A hybrid integrated circuit in which a solder land is formed of a lower layer conductor on a substrate, wherein a dielectric layer is interposed between the substrate and a part of the solder land. circuit.
形成する混成集積回路において、前記半田ランドの一部
上に、上層導体層を積層すると共に、この上層導体層の
一部と前記半田ランドとの間に、電気絶縁体層を介在さ
せたことを特徴とする混成集積回路。2. In a hybrid integrated circuit in which a solder land is formed of a lower conductor on a substrate, an upper conductor layer is laminated on a part of the solder land, and a part of the upper conductor layer and the solder land are formed. A hybrid integrated circuit, characterized in that an electrical insulator layer is interposed between the hybrid integrated circuit and the insulating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25147591A JPH0590435A (en) | 1991-09-30 | 1991-09-30 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25147591A JPH0590435A (en) | 1991-09-30 | 1991-09-30 | Hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0590435A true JPH0590435A (en) | 1993-04-09 |
Family
ID=17223371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25147591A Pending JPH0590435A (en) | 1991-09-30 | 1991-09-30 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0590435A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007123789A (en) * | 2005-10-31 | 2007-05-17 | Mitsumi Electric Co Ltd | Electronic component mounting structure of electronic module |
JP2015099889A (en) * | 2013-11-20 | 2015-05-28 | スズキ株式会社 | Printed circuit board |
-
1991
- 1991-09-30 JP JP25147591A patent/JPH0590435A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007123789A (en) * | 2005-10-31 | 2007-05-17 | Mitsumi Electric Co Ltd | Electronic component mounting structure of electronic module |
JP2015099889A (en) * | 2013-11-20 | 2015-05-28 | スズキ株式会社 | Printed circuit board |
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