JPH0590435A - Hybrid integrated circuit - Google Patents

Abstract

PURPOSE:To solder securely a chip part on a solder land of a substrate, the chip part being relatively light and easy to fix on the substrate. CONSTITUTION:Dielectric layers 14a and 14b are sandwiched between each inner end 13a1 and 13b1 of a pair of solder lands 13a and 13b formed on a substrate 12 with a sublayer conductor and the substrate 12, and thereby the solder lands are raised up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit in which a solder land is formed on a substrate by a lower layer conductor, and more particularly to a hybrid integrated circuit having an improved solder land.

[0002]

2. Description of the Related Art Conventionally, an example of this type of hybrid integrated circuit is shown in FIG. The hybrid integrated circuit 1 is formed by forming a plurality of pairs of left and right solder lands 3a and 3b on a substrate 2 made of ceramics or the like by a lower layer conductor, and inserting a chip component 4 or the like between the pair of solder lands 3a and 3b. A pair of connection terminals 4a and 4b of the surface mounting component are placed and soldered by reflow soldering.

Therefore, since the solder lands 3a and 3b are made of the same lower layer conductor as the lower layer conductor pattern, the solder lands 3a and 3b and the lower layer conductor pattern are prevented from being displaced during printing, and wiring can be performed at a high density.

[0004]

However, in such a conventional hybrid integrated circuit 1, when the chip component is light in weight, it is displaced from the solder land due to the surface tension and the fluid force of the melting solder at the time of reflow soldering. Sometimes.

Further, as shown in FIG. 4, the lower surface of the pair of left and right connection terminals 5a and 5b of the chip component is higher than the upper surfaces of the solder lands 3a and 3b, as in the case of the RFC coil 5 or the like. At some point, that is, from the top surface of substrate 2 R
When the height a to the upper surface of each connection terminal 5a, 5b of the FC coil 5 is higher than the height (film thickness) b of the solder lands 3a, 3b and there is a gap g between them, the RFC coil 5 itself is In addition to being self-supporting on the substrate 2, the soldering area is reduced.

Therefore, there is a problem that the connection terminals 5a and 5b are not easily fixed to the solder lands 3a and 3b by the solder 6, and the fixing positions are easily displaced.

The present invention has been made in view of such circumstances, and its purpose is to reduce the weight of a chip component to be soldered to a solder land or to increase the height of a connection terminal of the chip component. An object of the present invention is to provide a hybrid integrated circuit capable of reliably soldering these chip parts to the solder land even when the chip land is higher than the solder land.

[0008]

The present invention is configured as follows in order to solve the above-mentioned problems.

The invention according to claim 1 of the present application (hereinafter, referred to as the first
In a hybrid integrated circuit in which a solder land is formed by a lower layer conductor on a substrate, a dielectric layer is interposed between the substrate and a part of the solder land.

The invention according to claim 2 of the present application (hereinafter,
According to a second invention), in a hybrid integrated circuit in which a solder land is formed by a lower conductor on a substrate, an upper conductor layer is laminated on a part of the solder land, and a part of the upper conductor layer is formed. An electrical insulator layer is interposed between the solder land and the solder land.

[0011]

<First Invention> Since the dielectric layer is interposed between the substrate and a part of the solder land, part of the solder land is raised by the film thickness of the dielectric layer.

Therefore, by mounting the connection terminals of the chip parts such as the RFC coil, which are easily self-supporting, on the raised parts of the pair of solder lands, the soldering can be performed in a state where the self-supporting is prevented. The attachment can be ensured, and the chip components can be prevented from being displaced.

<Second Invention> Since the solder land is formed by laminating two layers of an electric insulator layer and an upper conductor layer on a part of the solder land and partially raising it, the chip is placed between the pair of raised portions. By mounting the parts, this chip part can be soldered so as to be sandwiched from both sides in the axial direction, so even if the chip part is lightweight, it is possible to prevent it from shifting during reflow soldering, and to ensure Can be soldered.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial vertical cross-sectional view of an embodiment of the first invention of the present application, in which a hybrid integrated circuit 11 is mounted on a hybrid integrated circuit substrate 12, for example, a pair of left and right solder lands 13a, 13b in the figure. Are formed by the lower layer conductor.

Then, a pair of solder lands 13a, 13b
A pair of left and right dielectric layers 14a and 14b are respectively interposed between a part of each of the inner end portions 13a1 and 13b1 and the substrate 12 to raise the inner end portions 13a1 and 13b1.

The thickness of the dielectric layers 14a and 14b is set such that the height of the pair of connection terminals 15a and 15b of the chip component such as the RFC coil 15 which is easily self-supporting on the substrate 12 can be set so as not to be self-supporting. It is set.

Therefore, according to the present embodiment, the raised inner ends 13a1, 13a1 of the pair of solder lands 13a, 13b,
For example, a pair of connection terminals 1 of the RFC coil 15 is provided between 13b1.
The RFC coil 15 is formed by bridging 5a and 15b.
It is possible to perform reflow soldering with the solder 16 while preventing the self-standing.

Therefore, it is possible to ensure soldering of the RFC coil 15 and prevent the RFC coil 15 from being displaced due to the surface tension of the molten solder during the reflow soldering.

FIG. 2 is a partially omitted vertical sectional view of an embodiment of the second invention of the present application. In the figure, a hybrid integrated circuit 21 is provided on a substrate 22 made of ceramics or the like, for example, a pair of left and right solder lands in the figure. Plural pairs 23 and 24 are formed by the lower conductor.

Then, projecting portions 25 and 26 projecting upward are provided on the respective parts of the pair of solder lands 23 and 24, for example, on the outer end portions 23a and 24a. The projecting portions 25, 26 are formed by laminating the upper conductor layers 27, 28 on the outer end portions 23a, 24a of the solder lands 23, 24, and the intermediate portions of the upper conductor layers 27, 28 and the solder lands 23, 24. And the electric insulator layers 29 and 30 having a required film thickness, are interposed between the two.

When mounting a relatively lightweight chip component 31 on the substrate 12, the pair of left and right connecting terminals 31a and 31b of the chip component 31 are connected to the pair of solder lands 2.
It is placed on the lower inner end portion between the projecting portions 25 and 26 of 3, 24 and fixed by the solder 32 by reflow soldering or the like.

Therefore, according to the present embodiment, the outer side surfaces of the pair of connection terminals 31a, 31b of the chip part 31 are provided on both outer sides in the axial direction from the pair of left and right solder lands 23,
It can be fixed so as to be sandwiched by both projecting portions 25 and 26 of 24.

Therefore, it is possible to prevent the lightweight chip component 31 from being displaced from the solder lands 23 and 24 due to the surface tension of the solder that melts during the reflow soldering, and to firmly fix the chip component 31.

[0025]

As described above, the first invention of the present application is
Since the dielectric layer is interposed between the substrate and a part of the solder land, a part of the solder land can be raised.

Therefore, by bridging the chip parts, which are easily self-supporting, between the raised portions of the pair of solder lands, soldering can be performed while the self-supporting is prevented, and the soldering can be ensured. In addition, it is possible to prevent the displacement during reflow soldering.

Further, according to the second invention of the present application, since the projecting portion is formed by laminating the electric insulator layer and the upper conductor layer on a part of the solder land, the projecting portion is formed between the pair of solder lands. By mounting a relatively lightweight chip component and soldering it, the axial outer surface of the chip component can be soldered so as to be sandwiched from both sides by a pair of protrusions.
In addition to ensuring the soldering, it is possible to prevent misalignment during reflow soldering.

[Brief description of drawings]

FIG. 1 is a longitudinal sectional view of an essential part of an embodiment of the first invention of the present application.

FIG. 2 is a partial vertical cross-sectional view showing a part of an embodiment of the second invention of the present application with a part thereof omitted.

FIG. 3 is a front view showing an example of a conventional example.

FIG. 4 is a partial vertical sectional view of a part of another conventional example.

[Explanation of symbols]

 11, 21 Hybrid integrated circuit 12, 22 Substrate 13a, 13b, 23, 24 Pair of solder lands 13a1, 13b1 Pair of inner ends of solder land 14a, 14b Dielectric layer 15 RFC coil 16, 32 Solder 25, 26 Upper layer conductor Layer 29,30 Electrical insulator layer 31 Chip parts

Claims (2)

[Claims] 1. A hybrid integrated circuit in which a solder land is formed of a lower layer conductor on a substrate, wherein a dielectric layer is interposed between the substrate and a part of the solder land. circuit. 2. In a hybrid integrated circuit in which a solder land is formed of a lower conductor on a substrate, an upper conductor layer is laminated on a part of the solder land, and a part of the upper conductor layer and the solder land are formed. A hybrid integrated circuit, characterized in that an electrical insulator layer is interposed between the hybrid integrated circuit and the insulating layer.