JPH0588976A - Cache storage device and information processor using the same and its information processing method - Google Patents

Abstract

PURPOSE:To provide a cache storage device capable of improving a data processing speed by storing data to be always used for the cache storage device and previously storing the data of addresses continued to a data address. CONSTITUTION:In an information processor constituted of successively connecting an instruction processor 1, a primary cache 2, a secondary cache 3, and a main storage device 4, an address register/counter 35 for tentatively storing a data address requested by the cache 3 is provided with a request data predictive storing means including a counting function, 64k-byte data and 256k-byte data are respectively stored in the caches 2, 3 and the transfer of 4-byte data from the cache 2 to the processor 1, the transfer of 16-byte data from the cache 3 to the cache 2 and the transfer of 64-byte data from the device 4 to the cache 3 are occasionally executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache storage device having a small storage capacity but a high access speed, and further, an information processing device using a secondary cache storage device having a two-stage hierarchical structure of the cache storage device and information thereof. Regarding processing method.

[0002]

2. Description of the Related Art In recent years, in an information processing device which is required to have high performance, a cache memory device is used between a main memory device and an instruction processing device for speeding up. The main memory has a large capacity but a low access speed, and the cache memory has a small capacity but a high access speed. Therefore, frequently used data is stored in the cache memory to cope with the speedup. However, the performance of the instruction processing device continues to increase due to the progress of semiconductor technology, and the capacity of the main memory device also continues to increase. Therefore, in some recent devices, the cache storage device itself is hierarchized into two stages. The first stage is called the primary cache storage device, the next stage is called the secondary cache storage device, and the primary cache storage device (hereinafter referred to as the primary cache). In the order of the secondary cache storage device (hereinafter referred to as the secondary cache) and the main storage device (hereinafter referred to as the main memory), the storage capacity is from small capacity to large capacity, and conversely, the access speed is from high speed to low speed in the same order. There is a configuration of a three-level storage device.

With reference to FIG. 9, the structure of an information processing apparatus of the conventional three-tier storage system will be described. This information processing apparatus is composed of an instruction processing device 1 and a storage device having a three-tiered structure of a primary cache 2, a secondary cache 3 and a main memory 4, and the instruction processing device and the primary cache are provided with a first data request signal 51 and a first data request signal 51. The first address bus 52, the first data bus 53, and the first data response signal 54 are connected to each other, and the primary cache and the secondary cache include a second data request signal 61, a second address bus 62, and a second data bus 63. Connected via the second data response signal 64, the secondary cache and the main memory are connected to the third data request signal 71, the third address bus 72, the third data bus 73, and the third data response signal 7.
4 are connected and configured.

The process of transferring data from the three-level storage device to the instruction processing device in the information processing device according to this conventional technique will be described below. In the initial state, the storage contents of the primary cache and the secondary cache are all cleared. First, the instruction processing device inputs the first data request signal to the primary cache and outputs the address of the requested data to the first address bus. In response to this, the primary cache checks whether or not the address exists in the storage unit of the primary cache, and if the address exists, that is, when it is a hit, it sends a first data response signal to the instruction processing unit. When the address is not present, that is, when there is a miss, the second data request signal is input to the secondary cache and the requested data is output to the second address bus. Output address.

In response to this, the secondary cache checks whether or not the address exists in the storage unit of the secondary cache, and if the address exists, that is, when there is a hit, the secondary cache stores the second address in the secondary cache. A data response signal is output and the data at that address is output to the second data bus. The primary cache having received this stores the address and the data of the address, outputs the first data response signal to the instruction processing device, and outputs the requested data to the first data bus.

If the address does not exist in the secondary cache, that is, when there is a mishit, the secondary cache will
The third data request signal is input to the main memory and the address is output to the third address bus. In response to this, the main memory is
The third data response signal is output to the secondary cache, and the data at that address is output to the third data bus.

In response to this, the secondary cache stores the address and the data of the address, outputs the second data response signal to the primary cache, and outputs the data of the address to the second data bus. In response, the primary cache stores the address and the data at the address, outputs the first data response signal to the instruction processing device, and outputs the requested data to the first data bus.

In this way, among the data in the main storage device, the most frequently used data is stored in the primary cache, and the next most used data is stored in the secondary cache, whereby the storage capacity of the cache storage device is increased. Has been used to increase the processing speed of the instruction processing device and improve the performance by utilizing the small access speed. This property is called locality.

[0009]

In recent years, due to advances in semiconductor manufacturing technology, it has become possible to manufacture high-performance instruction processing devices and large-capacity cache memory devices. A large-capacity cache storage device can be used for the primary cache, and even if the locality is applied to a two-tiered secondary cache, there is no effect and only the primary cache is sufficient for locality.

Therefore, not only the data requested by the instruction processing device and the address of the data are stored in the primary cache or the secondary cache, but also the data of the address continuous with the address of the data and the continuous address are stored. By doing so, on the program of the normal instruction processing device, the data (or program) requested next to the data (or program) requested to the storage device is
Because of the continuity of the program, they exist at consecutive addresses, so by storing the data of consecutive addresses in the primary cache or the secondary cache,
By utilizing the high access speed of the cache, the processing speed of the instruction processing device can be increased and the performance can be improved. This property is called continuity.

In the prior art cache memory system, only the data required to be requested is stored in the cache memory, and the data to be requested next is not stored in advance in the cache memory. There is a problem that the processing speed of the device is slow. Therefore, an object of the present invention is to provide one cache with locality and continuity when there is only one cache storage device, and to provide primary cache locality and secondary cache continuity when there are two cache storage devices. The object is to provide an information processing device having a high processing speed.

[0012]

According to the cache storage device of the present invention, in at least one cache storage device 2, 3 interposed between the instruction processing device 1 and the main storage device 4, the cache storage devices 2, 3 are When one data is requested from the instruction processing device 1, the data that will be requested after the next time is predicted corresponding to the data, and the data is read from the main memory device 4 of the next stage and the data is read in advance. It is characterized in that it comprises request data prediction storage means 31, 32, 33, 34, 35 to be stored in the cache storage devices 2, 3.

A cache storage device and an information processing device using the same according to the present invention are connected to the instruction processing device 1, a primary cache storage device 2 connected to the instruction processing device 1, and the primary cache storage device 2. In an information processing device including a secondary cache storage device 3 and a main storage device 4 connected to the secondary cache storage device 3, the primary cache storage device 2 stores data requested by the instruction processing device 1. It searches whether it exists in itself, transfers the data to the instruction processing device 1 if it exists, requests the data to the secondary cache storage device 3 if it does not exist, and requests the data from the secondary cache storage device 3. Is a device for storing the data transferred by the instruction processing device 1 and transferring the requested data to the instruction processing device 1. The secondary cache storage device 3 is the primary cache storage device. The requested data is searched for whether it exists in itself, and if it exists, the data is transferred to the primary cache storage device 2, and the address subsequent to the address of the data requested by the primary cache storage device 2 is further transferred. Is searched for whether it exists in itself, and if it exists, it is left as it is, and if it does not exist, the data is requested to the main storage device, the data transferred from the main storage device 3 is stored, and the secondary data is stored. If the data requested by the primary cache memory 2 does not exist in the cache memory 3, the cache memory 3 requests the main memory for the data and stores the data transferred from the main memory 3 to store the data in the primary cache. The requested data is transferred to the storage device 2, and the data of the address following the address of the data requested by the primary cache storage device 2 exists in itself. If whether exist as intact as long searched exists or wherein the requesting the data to the main storage device is a device for storing data transferred from the main memory 3.

[0014]

By providing the address register counter 35 in the cache memory device according to the present invention, when the data requested by the instruction processing device is not in the cache memory device (in the case of a mishit), the address register counter is incremented by +.
One count-up is performed, and the output address and the data in the main memory corresponding to the address are stored in the cache memory.

[0015]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of an information processing apparatus of a three-tiered storage system according to an embodiment of the present invention.
In the figure, the same parts as those in the configuration diagram (FIG. 9) of the information processing apparatus of the cache storage system according to the prior art are designated by the same reference numerals and the description thereof will be omitted. As shown in FIG. 1, the primary cache storage device includes a tag RAM 21, a comparison circuit 22, a control circuit 23, a data RAM 24, an address register 25 and a data driver 26.

FIG. 2 shows an internal circuit configuration diagram of the primary cache memory device. The tag RAM 21 is a storage unit that sequentially stores upper addresses (AB16 to 31) of data or a program (hereinafter referred to as data) requested by the instruction processing device 1 each time a mishit occurs. The comparison circuit 22 determines the upper address (AB16 to 31) of the data requested by the instruction processing device 1 and the lower address (AB04 to AB04).
15) The address stored in the tag RAM 21 designated in 15) is compared to determine whether these addresses match (that is, hit or miss).

The control circuit 23 receives the first data request signal 51 from the instruction processing device 1 and, if the result of the comparison circuit 22 is a hit, sends the first data response signal 54 to the instruction processing device 1 to cause a miss. If it is a hit, it is a circuit that transmits the second data request signal 61 to the secondary cache and receives the second data response signal 64 from the secondary cache, and is a circuit that controls its own internal circuit.

The data RAM 24 stores the data (DB00 to 31) sent from the secondary cache at the address (AB0).
It is a storage unit that stores 2 to 15 entries (4096 entries) and has a storage capacity of 64 Kbytes. The address register 25 is a register for temporarily storing the address of the data requested by the instruction processing device 1.

The data driver 26 is a data RAM 24.
It is a circuit for transferring the data requested by the instruction processing device 1 from the data stored in the instruction processing device 1. Next, as shown in FIG. 1, the secondary cache memory device includes a tag RAM 31, a comparison circuit 32, and a control circuit 3.
3, a data RAM 34, an address register counter 35, and a data driver 36.

FIG. 3 shows an internal circuit configuration diagram of the secondary cache memory device. The tag RAM 31 is a storage unit that sequentially stores the upper address (AC 18 to 31) of the data requested from the primary cache 1 each time there is a mishit. The comparison circuit 32 compares the upper address (AC18 to 31) of the data requested from the primary cache 2 with the address stored in the tag RAM specified by the lower address (AC06 to 17), and those addresses are compared. Discriminate whether or not (that is, hit or miss).

The control circuit 33 receives the second data request signal 61 from the primary cache 2 and sends a second data response signal 64 to the primary cache 2 if the result of the comparison circuit 32 is a hit. For example, it is a circuit that transmits the third data request signal 71 to the main memory and receives the third data response signal 74 from the main memory, and is a circuit that controls its own internal circuit.

The data RAM 34 is a storage unit for storing data (DC00 to 63) addresses (4096 entries for AC03 to 17) sent from the main memory, and has a storage capacity of 256 Kbytes. The address register counter 35 is a register that temporarily stores the address of the data requested from the primary cache 2, and the secondary cache 3
Also has a counter function of adding +1 to the address when is miss-hit.

The data assembly circuit 36 includes a data RAM 34.
Is a circuit for transferring the data requested by the primary cache 2 from the data stored in the primary cache 2 to the output (DC00 to DC00) from the data RAM 34.
63) 64-bit upper (DC32 to 63) and lower (D)
This is a circuit assembled into 32 bits each of C00 to 31).

FIG. 4 is a diagram showing mapping of the primary cache, secondary cache, and main memory according to the embodiment of the present invention. As a mapping method, a direct mapping method is used as is clear in the figure. FIG. 4-A shows the mapping between the primary cache and the main memory. The addresses (A04 to A15) of the primary cache are 12 bits and 4096.
Each entry has one entry and one block (16 bytes) of data is transferred from the main memory via the secondary cache. That is, 4096 × 16 bytes = 64 Kbytes of data is stored in the data RAM of the primary cache.
For each primary cache entry, for example, entry 0 is, as shown in FIG.
Entry 1 corresponds to any one of address 0000, address 20000, ...
It corresponds to any one of address 0, address 20010, ..., And so on.

FIG. 4B shows the mapping between the secondary cache and the main memory. The addresses (A06-A06) of the secondary cache are shown.
17) has 12 bits and 4096 entries, and one entry transfers one block (64 bytes) of data from the main memory. That is, data of 4096 × 64 bytes = 256 Kbytes is stored in the data RAM of the secondary cache. For each secondary cache entry, for example, entry 0 corresponds to any one of main memory addresses 0, 40000, 80000, ... As shown in FIG. 4-B, and entry 1 corresponds to the main memory. Address 40, 4
It corresponds to any one of 0040 address, 80040 address, ... And so on.

Next, the operation of the three-level storage device according to the present invention will be described with reference to FIGS. FIG. 5 is a time chart showing a data transfer process in the case of a primary cache hit. When the instruction processing device 1 requests data from the primary cache 2, the instruction processing device 1 receives the first address bus 52 at time t ₁₀ .
The address is output to and the first data request signal 51 is output.

The primary cache 2 is the address register 2
5 outputs the address on the first address bus 52 to the second address bus 62, and the lower address AB04 ...
Input 15 into the address of the first tag RAM 21. The tag RAM 21 outputs the addresses stored in the tag RAM 21 corresponding to the lower addresses AB04 to 15 at that time to the read comparison circuit 22.

The comparison circuit 22 compares the address read by the tag RAM 21 with the upper addresses AB16 to 31 on the second address bus 62. When the result matches, it becomes a hit. At this time, at time t ₁₁ , the primary cache 2 inputs the addresses AB02 to 15 on the second address bus 62 to the data RAM 24, outputs the read data (4 bytes) to the second data bus 63, and then the data The data is output to the first data bus 53 via the driver 26 and the first data response signal 54 is output to the instruction processing device 1.

FIG. 6 is a time chart showing a data transfer process in the case of a primary cache miss hit and a secondary cache hit (1) when there is a hit when the address register counter counts up. Instruction processing device 1
Requests data from the primary cache 2 at time t ₂₀
Outputs the address to the first address bus 52 and outputs the first data request signal 51.

The primary cache 2 is an address register 25.
Outputs the address on the first address bus 52 to the second address bus 62, and the lower address AB04 to 1
5 is input to the address of the first tag RAM 21. Tag R
The AM 21 reads the address stored in the tag RAM 21 corresponding to the lower addresses AB04 to 15 at that time and outputs it to the comparison circuit 22.

The comparison circuit 22 compares the address read by the tag RAM 21 with the upper addresses AB16 to 31 on the second address bus 62. As a result, when they do not match, it becomes a miss hit. At this time, at time t ₂₁ , the primary cache 2 outputs the second address bus 62 and the second data request signal 61 to the secondary cache 3.

At time t ₂₂ , the secondary cache 3 receives the second data request signal 61, sets the addresses AB03 to 31 on the second address bus 62 in the address register counter 35, and outputs it on the third address bus 72. Then, the lower address AC06 to 17 is input to the address of the second tag RAM 31. The tag RAM 31 reads the address stored in the tag RAM 31 corresponding to the lower address AC 06 to 17 at that time and outputs it to the comparison circuit 32.

The comparison circuit 32 compares the address read by the tag RAM 31 with the upper address AC18-31 on the third address bus 72. When the result matches, it becomes a hit. At this time, at the time t ₂₃ , the secondary cache 3 inputs the addresses AC03 to AC17 on the third address bus 72 to the data RAM 34 and outputs the data (8 bytes × 2 = 16 bytes) read therefrom to the data assembling circuit. It outputs to the third data bus 73 as data of 4 bytes × 4 via the data 36, and then the data driver 36
To the second data bus 63 and the second data response signal 64 to the primary cache 2.

In response to this, the primary cache 2 receives this 4
Input the data of byte x 4 into the first data RAM 24,
Moreover, the corresponding address of the first tag RAM 21 is also updated. Next, at time t ₂₄ , the address register counter 35 becomes +
Count up by 1, and output lower address AC
In the same manner as above, the tag RAM 31 and the comparison circuit 32 are used to store the upper address A 06 to A 17 on the third address bus 72.
Compare with C18-31. If the results match, it will be a hit. At this time, the primary cache 2 receives the second data response signal 64 and receives the address AB on the second address bus 62.
02 to 15 are input to the data RAM 24, the read data (4 bytes) is output to the second data bus 63,
Thereafter, via the data driver 26, the first data bus 53
And outputs the first data response signal 54 to the instruction processing device 1.

FIG. 7 is a time chart showing a data transfer process in the case of a primary cache miss hit and a secondary cache hit (2) when the address register counter counts up and there is a miss hit. When requesting data from the primary cache 2, the instruction processing device 1 outputs an address to the first address bus 52 at time t ₃₀ and also outputs a first data request signal 51.

The primary cache 2 is an address register 25.
Outputs the address on the first address bus 52 to the second address bus 62, and the lower address AB04 to 1
5 is input to the address of the first tag RAM 21. Tag R
The AM 21 reads the address stored in the tag RAM 21 corresponding to the lower addresses AB04 to 15 at that time and outputs it to the comparison circuit 22.

The comparison circuit 22 compares the address read by the tag RAM 21 with the upper addresses AB16 to 31 on the second address bus 62. As a result, when they do not match, it becomes a miss hit. At this time, at time t ₃₁ , the primary cache 2 outputs the second address bus 62 and the second data request signal 61 to the secondary cache 3.

At the time t ₃₂ , the secondary cache 3 receives the second data request signal 61 and transfers the addresses AB 03 to 31 on the second address bus 62 to the address register counter 35.
, And outputs to the third address bus 72, and the lower address AC06 to 17 is input to the address of the second tag RAM 31. The tag RAM 31 reads the address stored in the tag RAM 31 corresponding to the lower address AC 06 to 17 at that time and outputs it to the comparison circuit 32.

The comparison circuit 32 compares the address read by the tag RAM 31 with the upper address AC18-31 on the third address bus 72. When the result matches, it becomes a hit. At this time, at time t ₃₃ , the secondary cache 3 inputs the addresses AC 03 to 17 on the third address bus 72 to the data RAM 34 and assembles the read data (8 bytes × 2 = 16 bytes) into the data. The data is output to the third data bus 73 as 4 bytes × 4 data via the circuit 36, and then the data driver 3
The data is output to the second data bus 63 via 6 and the second data response signal 64 is output to the primary cache 2.

Next, at time t ₃₄ , the address register counter 35 counts up by +1 and the lower addresses AC06 to 17 of the output are counted by the tag RAM 31 and the comparison circuit 32 in the same manner as described above to the upper address AC18 on the third address bus 72. Compare with ~ 31. As a result, if they do not match, a miss hit occurs. At this time, the primary cache 2 receives the second data response signal 64 and inputs the addresses AB02 to 15 on the second address bus 62 to the data RAM 24,
The read data (4 bytes) is used as the second data bus 63
, And then to the first data bus 53 via the data driver 26 to output the first data response signal 54 to the instruction processing device 1.

Next, at time t ₃₅ , the secondary cache 3 outputs the third address bus 72 and the third data request signal 71 to the main memory 4. Next, at time t ₃₆ , the main memory 4
Receives the third data request signal 71 from the secondary cache 3 and outputs the data (8 bytes × 8 = 64 bytes) read to the third address bus 72 to the third data bus 7
3 to the third data bus 73 of the secondary cache 3 as 8 bytes × 8 data, and the third data response signal 74. In response to this, the secondary cache 3 inputs the data of 8 bytes × 8 to the second data RAM 34, and also updates the corresponding address of the second tag RAM 31.

FIG. 8 is a time chart showing a data transfer process in the case of a primary cache miss hit and a secondary cache miss hit. When requesting data from the primary cache 2, the instruction processing device 1 outputs an address to the first address bus 52 at time t ₄₀ and also outputs the first data request signal 51.
Is output.

The primary cache 2 is an address register 25.
Outputs the address on the first address bus 52 to the second address bus 62, and the lower address AB04 to 1
5 is input to the address of the first tag RAM 21. Tag R
The AM 21 reads the address stored in the tag RAM 21 corresponding to the lower addresses AB04 to 15 at that time and outputs it to the comparison circuit 22.

The comparison circuit 22 compares the address read by the tag RAM 21 with the upper addresses AB16 to 31 on the second address bus 62. As a result, when they do not match, it becomes a miss hit. At this time, at time t ₄₁ ,
The primary cache 2 outputs the second address bus 62 and the second data request signal 61 to the secondary cache 3.

At time t ₄₂ , the secondary cache 3 receives the second data request signal 61, and transfers the addresses (AB03 to 31) on the second address bus 62 to the address register counter 3
5, the data is output to the third address bus 72, and the lower address AC06 to 17 is input to the address of the second tag RAM 31. The tag RAM 31 reads the address stored in the tag RAM 31 corresponding to the lower address AC 06 to 17 at that time and outputs it to the comparison circuit 32.

The comparison circuit 32 compares the address read by the tag RAM 31 with the upper address AC18-31 on the third address bus 72. As a result, when they do not match, it becomes a miss hit. At time t ₄₃ , the secondary cache 3 outputs the third address bus 72 to the main memory 4 and also outputs the third data request signal 71.

Next, at time t ₄₄ , the main memory 4 receives the third data request signal 71 from the secondary cache 3 and the data read out to the third address bus 72 (8 bytes ×
(8 = 64 bytes) is output to the third data bus 73 as 8 bytes × 8 data to the third data bus 73 of the secondary cache 3 and the third data response signal 74 is output.

In response to this, the secondary cache 3 receives this 8
Input the data of byte × 8 into the second data RAM 34,
Moreover, the corresponding address of the tag RAM 31 is also updated. Next, at time t ₄₅ , the secondary cache 3 inputs the addresses AC03 to 17 on the third address bus 72 to the data RAM 34 and reads the data (8 bytes × 2 = 16 bytes).
Is output to the third data bus 73 as data of 4 bytes × 4 via the data assembling circuit 36, and then to the second data bus 63 via the data driver 36, and the second data response signal is sent to the primary cache 2. 64 is output.
At the same time, the corresponding address in the tag RAM 21 is also updated.

Next, at time t ₄₆ , the primary cache 2 receives the second data response signal 64, inputs the addresses AB02 to 15 on the second address bus 62 to the data RAM, and reads the read data (4 bytes). ) Is output to the second data bus 63 and then to the first data bus 53 via the data driver 26, and the first data response signal 54 is output to the instruction processing device 1.

[0050]

According to the present invention, since the data or program at the address next to the address of the data or program requested by the instruction processing device is stored in the cache storage device, the program of the normal instruction processing device is ,
Since the data or program requested next to the data or program requested from the storage device exists at consecutive addresses due to the continuity of the program, the processing speed of the instruction processing device can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus of a three-tier storage system according to an embodiment of the present invention.

FIG. 2 is an internal circuit configuration diagram of a primary cache storage device.

FIG. 3 is an internal circuit configuration diagram of a secondary cache storage device.

FIG. 4 is a memory mapping diagram of a primary cache, a secondary cache, and a main memory.

FIG. 5 is a time chart showing a data transfer process at the time of a primary cache hit.

FIG. 6 is a time chart showing a data transfer process in the case of a primary cache miss hit and a secondary cache hit (1).

FIG. 7 is a time chart showing a data transfer process at the time of a primary cache miss hit and a secondary cache hit (2).

FIG. 8 is a time chart showing a data transfer process at the time of a primary cache miss hit and a secondary cache miss hit.

FIG. 9 is a configuration diagram of an information processing device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Instruction processing device 2 ... Primary cache storage device 3 ... Secondary cache storage device 4 ... Main storage device 21 ... Primary cache tag RAM 22 ... Primary cache comparison circuit 23 ... Primary cache control circuit 24 ... Primary cache data RAM 25 ... Primary Cache address register 26 ... Primary cache data driver 31 ... Secondary cache tag RAM 32 ... Secondary cache comparison circuit 33 ... Secondary cache control circuit 34 ... Secondary cache data RAM 35 ... Secondary cache address register counter 36 ... Secondary cache Data driver 51 ... First data request signal 52 ... First address bus 53 ... First data bus 54 ... First data response signal 61 ... Second data request signal 62 ... Second address bus 63 ... Second data bus 64 ... Two data response signal 71 Third data request signal 72 ... third address bus 73 ... third data bus 74 ... third data response signal

Claims (3)

[Claims] 1. An instruction processing device (1) and a main storage device (4).
At least one cache storage device (2, 3) interposed between the cache storage device (2, 3)
When one data is requested from the instruction processing device (1), it predicts the data that will be requested from the next time onward corresponding to the data, and the data from the main memory device (4) in the next stage is predicted. To read the cache storage device (2, 3) in advance
Request data prediction storage means (31, 32,
33, 34, 35). 2. An instruction processing device (1), a primary cache storage device (2) connected to the instruction processing device (1),
An information processing device comprising a secondary cache storage device (3) connected to the primary cache storage device (2) and a main storage device (4) connected to the secondary cache storage device (3), The primary cache storage device (2) is an instruction processing device (1).
The data requested by the server is searched for whether it exists in itself, and if it exists, the data is transferred to the instruction processing unit (1), and if it does not exist, the data is stored in the secondary cache storage unit (3). Is a device for storing the data transferred from the secondary cache storage device (3) and transferring the requested data to the instruction processing device (1), the secondary cache storage device (3) Searches whether the data requested by the primary cache storage device (2) exists in itself, transfers the data to the primary cache storage device (2) if it exists, and further, the primary cache storage device The device (2) searches for the data at the address following the address of the data requested by the device (2),
If it exists, it is left as it is. If it does not exist, the data is requested to the main storage device (4), the data transferred from the main storage device (4) is stored, and further, the second cache storage device ( If the data requested by the primary cache storage device (2) does not exist in itself, 3) requests the data from the main storage device (4), and the data transferred from the main storage device (4). And stores the requested data in the primary cache storage device (2), and further searches for data at an address following the address of the data requested by the primary cache storage device (2). If it exists, it is left as it is, and if it does not exist, it is a device for requesting the data to the main storage device (4) and storing the data transferred from the main storage device (4). Information processing apparatus. 3. An instruction processing device (1), a primary cache storage device (2) connected to the instruction processing device (1),
Information of an information processing device including a secondary cache storage device (3) connected to the primary cache storage device (2) and a main storage device (4) connected to the secondary cache storage device (3) In the processing method, in the primary cache storage device (2), a step of searching whether or not the data requested by the instruction processing device (1) exists in itself, and if the data exists, the instruction processing device (1 ), The step of transferring the data to the secondary cache storage device (3), the step of requesting the data from the secondary cache storage device (3) if the data does not exist, and the data transferred from the secondary cache storage device (3). And a step of transferring the requested data to the instruction processing device (1), wherein the secondary cache storage device (3) stores the primary cache storage data. (2) searching for whether or not the requested data exists in itself, transferring the data to the primary cache storage device (2) if the data exists, and the primary cache A step of searching whether or not the data of the address following the address of the data requested by the storage device (2) exists in itself, and if the data exists, it is left as it is and the main storage device (4 ) To store the data transferred from the main storage device (4), and further, in the secondary cache storage device (3), the data is transferred from the primary cache storage device (2). If the requested data does not exist in itself, the step of requesting the data from the main storage device (4), and the data transferred from the main storage device (4) are stored in the primary cache storage device. (2) transferring the requested data, searching for whether or not data at an address following the address of the data requested by the primary cache storage device (2) exists in itself, and If it exists, it is left as it is, and if it does not exist, a step of requesting the data to the main storage device (4) and storing the data transferred from the main storage device (4) is provided. A characteristic information processing method.