JPH0588428B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of sampling and measuring high-speed signals, and in particular, a method of changing the start address of word generation of a word generator connected to a device under test. This invention relates to a moving address sampling measurement method that changes the phase of a sampling point.

[Prior art and its problems]

6 and 7 are diagrams showing the principle of sampling measurement. When the minimum sampleable interval T _s of the sampling circuit is larger than the desired measurement interval t _i and the waveform to be measured is repetitive, the seventh
By selecting sample points as shown in the figure, the waveform shown in FIG. 6 can be reproduced. In FIG. 7, the same point is sampled twice, but by increasing the number of samples in this way, the sampling efficiency can be compensated for or averaged.

Here, in the conventional circuit, when sampling the same point of the signal under test multiple times to compensate for sampling efficiency, the trigger point synchronized with the signal under test is used as a reference, as shown in Figure 7, and from that trigger point The delay up to the sample point was changed by t _i (t _i , 2t _i , ...). In the past, programmable delay lines were used to shift sample points by a predetermined amount of time. However, in this method, the resolution and accuracy for shifting t _i depend on the performance of the programmable delay line, and it is difficult to accurately shift t _i by a desired amount of time, resulting in an element of time error. Furthermore, when the period t of the signal to be measured is long, even though _Ts is sufficiently shorter than t, it is necessary to wait for t until the next sample point, resulting in an increase in measurement time.

[Purpose of the invention]

The present invention was made in order to eliminate the above-mentioned drawbacks, and it is possible to sample the sample point of the signal under test without time error, and also sample the entire signal under test at high speed even if the period of the signal under test is long. An object of the present invention is to provide a sampling measurement method that can perform the following steps.

[Summary of the invention]

In the present invention, a word generator is used as the signal source connected to the device under test, and instead of shifting the time from the trigger point to the sampling point,
The start address of the word generation of the word generator is changed, thereby changing the phase of the sample point. Further, if the period of the signal to be measured is sufficiently longer than the minimum sampleable interval of the sampling circuit, sampling is performed by repeatedly generating a portion of the words in the word generator. Then, the portions are sequentially moved to perform a measurement equivalent to sample measurement for one period of the signal under test.

[Embodiments of the invention]

FIG. 1 is a block diagram illustrating an example of a sampling measuring device for embodying the method according to the invention.

In the following, the device under test (DUT) 3 is
(digital-to-analog converter) as an example. A word generator 1 is connected to the input of the device under test 3, and a sampling circuit 5 is connected to its output. As shown in FIG. 2, the word generator 1 has a length N having a value corresponding to each value of T _i of a sine wave having a period T.
It consists of 1 memory. and word generator 1
sequentially generates digital words in response to clock pulses A from word generation clock signal source 7. The DAC 3 outputs, for example, a pseudo sine wave corresponding to this digital word. The trigger generation clock signal source 9 is composed of a counter or a frequency divider, receives the clock A from the clock signal source 7, and is synchronized so that one clock B is generated from N clocks A. . Then, a trigger signal is given to the sampling circuit 5. Sampling circuit 5
samples the output signal (signal under test) of the DAC 3 in response to the trigger signal, but generates a sample pulse S _p after a scheduled time delay after receiving the trigger signal. For example, the trigger signal occurs at S _p after a time of T _i ×(N/2) has elapsed. This time delay uses the clock B of the clock signal source 7, and uses a counter,
It can be easily obtained using a frequency divider etc. A conventional circuit may be used as the sampling circuit 5, and its details will be omitted.

The operation of the above embodiment will be explained below. FIG. 3 is an explanatory diagram of the operation. As mentioned above, it is assumed that the sampling circuit 5 generates the sample pulse S _p after T _i ×(N/2) after receiving the trigger signal from the clock signal source 9. When clock signal source 9 generates clock B, word generator 1 outputs a word at address 0 in response to clock A from clock signal source 7 (start address: 0). Then, in response to clock A, 1, 2, ... (N-
The word 1) is output, and when the address reaches (N-1), it returns to 0 and repeats this process. At this time, the sampling circuit 5 samples the signal under measurement corresponding to the word at address N/2. After the signal under test corresponding to address N/2 has been sampled once or multiple times (averaged), the start address of word generator 1 at the time of clock B generation is changed to 1 (other settings are the same). ). Therefore, the value of the signal under test sampled by the sampling circuit 5 is the value when the address is (N/2+1), and the sampling time point is changed by the time interval of the clock A. In this way, the start addresses at the time of clock B generation are sequentially 2, 3, ... (N-
1), the sampling circuit 5 starts from N/2, (N/2+1), ... (N-1),
The values of the signal under test for words at addresses 0, 1, . . . (N/2-1) are sampled, and one cycle of the signal under test is sampled. Note that the change in the start address is, for example, when measuring the same point of the signal under test 10 times, the address pointer is changed by 1 after 10 clocks B are generated.
All you have to do is increment by 1. Also, the sampling point is T _i × (N/2) after receiving clock B.
set to, but not limited to,
Of course, it may be set arbitrarily.

FIG. 4 is an explanatory diagram of the operation of a sampling measurement method according to another embodiment of the present invention. The circuit configuration is the first
It is similar to that shown in the figure. This embodiment can be applied when the period T of the signal under test is sufficiently longer than the minimum sampleable interval T _s of the sampling circuit 5. For example, if the device under test 3 is a DAC, all its codes (N = 1024 for 10 bits, 12
This is a case where N=4094 bits are tested.
The N words are divided into M groups such that T _i ×M is equal to or slightly longer than T _s .
In FIG. 4, M=8. In measurement 1, addresses 0 to 7 are selected, and only addresses between these are selected repeatedly. In the same manner as described in FIGS. 1-3, in response to clock B, address 5 is
The value corresponding to the word is repeatedly sampled (arrow a). At this time, the repetition period is T _i ×8 (≧
T _s ), so the sampling circuit 5 is wasted (waiting).
The time will be significantly shorter. After repeating the sampling for address 5 a necessary number of times, the process moves to measurement 2. Already, the start address has moved to 1, and sampling for address 6 is performed with eight repetitions of addresses 1 to 8. The start address is sequentially moved, and finally, the signal under test for the word at address 4 is sampled by repeating 6 times from address (N-1). For example, the repetition of addresses 0 to 7 can be done by specifying start and stop addresses and using clock A to cycle through them. Note that when sampling N words divided into M groups, there are discontinuous points in the input and output of DUT3 (for example, from address 7 to 0), compared to when N words are generated repeatedly. changes) occur more frequently, but
The influence of discontinuity can be removed by setting the value of M to a certain degree and by setting the sampling point as late as possible from the start address (sixth in this embodiment). This is because if a sampling point comes immediately after a discontinuity point, it may be affected by the discontinuity.

In the above description, a DAC was used as the test element, but an analog input device such as an amplifier may also be used.
In this case, as shown in FIG. 5, the signal source is a word generator 1 with a built-in DAC or a low-pass filter built-in.
The output may be output to the device under test.

〔Effect of the invention〕

As explained above, according to the present invention, (1) the sampling delay remains fixed, the start address of the word generator is changed, and the amount of change is determined by the accuracy of the clock signal, so the desired point of the signal under test is can be accurately sampled and measured.
(2) Even if the period of the signal under test is significantly longer than the minimum sampling interval of the sampling circuit, the word generator can repeatedly generate a portion of all words and move the portion in sequence. A measurement equivalent to a sampling measurement of one period of the measurement signal can be performed at high speed. (3) When the start address is changed, the continuity of the signal under test is lost, but the sampling point can be set at any point to avoid this effect; (4) The same point on the signal under test can be set. You can freely sample multiple times.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a sampling measuring device for realizing the sampling measuring method according to the present invention, FIGS. 2 and 3 are operation explanatory diagrams of the sampling measuring method according to the present invention, and FIG. An explanatory diagram of the operation of a sampling measurement method according to another embodiment of the invention, FIG. 5 is a block diagram showing an example of another sampling measurement device for realizing the sampling measurement method according to the invention, and FIGS. 6 and 7 is a diagram showing the principle of sampling measurement. DESCRIPTION OF SYMBOLS 1... Word generator, 3... Device under test, 5... Sampling circuit, 7, 9... Clock signal source.

Claims (1)

[Scope of Claims] 1 A measurement signal which is a digital word signal corresponding to each of the N addresses or an analog signal corresponding to the digital word signal is applied to the device under test in response to a first clock signal; A sampling pulse is generated in response to a second clock signal generated at a frequency of 1/N of one clock signal and delayed by a predetermined time from the second clock signal, and the output signal of the device under test is controlled by the sampling pulse. At the same time as sampling, by changing the start address at which the digital word signal is sequentially generated, the generation point of the sampling pulse with respect to the digital word signal is changed so that different points of the output signal are sampled; 2. A sampling measurement method in which the time interval between the two clock signals and the sampling pulse is fixed during sample measurement. 2. Sampling is performed by repeatedly generating the measurement signal with address 0 to address M (M<N) as one group, and sampling is performed sequentially for each group by sequentially shifting the start address by one, and one of the output signals is The sampling measurement method according to claim 1, wherein sampling is performed over a period.