JPH0588038B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a color killer circuit that eliminates the need for a large capacitor constituting an ACK (automatic color killer) filter.

(Prior Art) A color killer circuit used in color signal processing of a VTR (video tape recorder) has the following two functions in order to prevent unnatural colors from being added to the reproduced video signal.

(A) Turn off the color signal output when the black and white signal or the input amplitude is a minute color signal below the controllable level of the AGC circuit (automatic gain control circuit).

(B) Turn off the color signal output when the APC circuit (color synchronization signal) is disconnected.

Figure 4 shows the conventional method used in VTR color signal processing.
FIG. 3 is a block diagram of an ACK processing circuit. In this figure 4, APC detector 1 and APC filter 2
A PLL (Phase Loop Look) is configured with the VCO3, and the phase of the color burst signal a input from the input terminal 4 of the VCO3 is detected by the APC detector 1, and the detected output is passed through the APC filter 2 to create a DC current. A voltage is generated and this DC voltage is applied to the VCO 3 as a control voltage for the VCO 3 to control its output oscillation frequency.

Also, the output of VCO3 is passed through the 90° transfer device 5.
In addition to the ACK detector 6, this ACK detector 6 performs phase detection between the color burst signal a and the output signal b of the 90° shifter 5, and outputs the output signal C.
In addition to the ACK filter 7, the output signal d of the ACK filter 7 is output to a comparator 8 for comparison with the ACK detection level.

In FIG. 4, when the PLL is locked, the phase of the signal at the output terminal 3a of the VCO 3 maintains a phase delayed by 90 degrees with respect to the color burst signal a, and the phase of the signal at the output terminal 3a of the VCO 3 after passing through the 90 degrees shifter 5 is delayed by 90 degrees. 5a
Then, it is in phase with the color burst signal a.

The ACK detector 6 has the function B described above.
For the phase, it operates as a synchronous detector and APC
It determines whether the circuit is in a locked state or not, and operates as a peak detector for amplitude, having the function of A described above.

In order to realize such a function with a single detector, a multiplier with a certain gain is used for color burst signals. Furthermore, since it operates only during the burst gate, the operation is stopped in other sections and the voltage at the end of the ACK filter is held.

The operation of the ACK detector 6 under each condition is explained in the fifth section.
Illustrated with diagrams. In FIG. 5, indicates the operation when the amplitude of the color burst signal a is large (ACC flat level) and the APC circuit is in a locked state. In this case, the color burst signal a at terminal 4 shown in FIG. 5a and the color burst signal a shown in FIG.
With respect to the output signal b of the output terminal 5a of the 90° phase shifter 5, the output signal c of the output terminal 6a of the ACK detector 6 at the burst gate has a synchronous detection waveform as shown in FIG. filter end 7a of
The filter end voltage d increases as shown in FIG. 5d.

Furthermore, FIG. 5 shows the operation when the amplitude of the color burst signal is small and the APC circuit is in a locked state. In this case, the output terminal c of the ACK detector 6a during the burst gate becomes a synchronous detection waveform with a smaller peak value than the case shown in Fig. 5c, and the terminal voltage d of the ACK filter 7 is as shown in Fig. 5d. As low as

Furthermore, FIG. 5 shows the operation when the APC circuit is in an unlocked state, although the amplitude of the color burst signal is large (ACC flat level). In this case, the output signal c of the output terminal 6a of the ACK detector 6 at the time of the burst gate becomes a multiplied waveform of an arbitrary phase difference, as shown in FIG. 5c, and its average voltage changes according to the phase difference.

ACK detector 6 when APC circuit is unlocked
Since the phase difference between the input signals changes with the beat frequency, the output signal d from the output terminal 6d of the ACK detector 6 has an envelope waveform whose frequency coincides with the beat frequency, as shown by the dotted line in Fig. 5d. The pulse train of the burst gate section is as follows.

At this time, if the time constant of the ACK filter 7 is sufficiently large, the filter end voltage d becomes a direct current as shown by the solid line in FIG. 5e, and its value is equal to the voltage (bias voltage) when no input is applied.

The filter end voltage d of the ACK filter 7 is compared with the ACK detection level by a comparator 8, and an ACK signal f is outputted to the terminal 9 depending on the magnitude thereof.
If the ACK detection level is selected as shown by the dotted line in Fig. 5e, the killer can be turned on in the case of , and the killer can be applied only in the case of the functions A and B described above.

However, in the conventional color killer circuit as shown in Fig. 4, when the APC circuit is in the unlocked state,
It is necessary to make the time constant of the ACK filter 7 large so as not to malfunction with respect to the beat signal output from the ACK detector 6.

Therefore, there are two problems: a large capacity capacitor must be used for the ACK filter 7, and when this circuit is incorporated into an IC, one pin must be prepared as the ACK filter terminal. I was getting used to it.

In addition, since the ACK detector 6 performs amplitude detection and phase detection simultaneously, it is necessary to achieve both detection performances with a single circuit, and it is also necessary to provide hysteresis characteristics, which reduces the degree of freedom in circuit design. It was a complicated circuit.

(Problems to be Solved by the Invention) This invention solves the problem that in the conventional color killer circuit described above, one pin is used as the ACK filter terminal because it is necessary to use a large capacity capacitor in order to increase the time constant of the ACK filter. This was done in order to eliminate the disadvantages of having to prepare the ACK filter, having little flexibility in circuit design, and making it complicated.It not only eliminates the need for a large capacitor in the ACK filter, but also simplifies the circuit configuration. The purpose is to provide a color killer circuit that can increase the degree of freedom in design.

[Structure of the Invention] (Means for Solving the Problems) The color killer circuit of the present invention includes an ACK phase detector that performs phase detection between a color burst signal and a signal shifted by 90 degrees from the output of a VOC, and a color burst ACK amplitude detector that detects the amplitude of the signal and ACK
It is provided with a pulse count circuit that counts the AND output of the outputs of the phase detector and the ACK amplitude detector.

(Operation) In this invention, the ACK phase detector performs phase detection of the color burst signal and a signal whose phase is shifted by 90 degrees from the output of the VCO, and also detects the phase of the color burst signal.
The output of amplitude detected by the ACK amplitude detector is 1H (1
(horizontal synchronization), the AND gate is used to calculate the AND gate, and the output pulses are counted by the pulse count circuit.

(Example) Hereinafter, an example of the color killer circuit of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment. In FIG. 1, a color burst signal 11a is connected to a terminal 11.
is now being entered. This color burst signal 11a is input to an APC detector 12, an ACK phase detector 13, and an ACK amplitude detector 14.

APC detector 12, APC filter 15, VCO 1
6 constitutes a PLL as in the case of FIG. 4, and this PLL synchronizes the oscillation output of the VCO 16 with the color burst signal 11a.

The output signal of the output terminal 16a of this VCO 16 is
The signal is input to an APC detector 12 and a 90° phase shifter 10. The 90° phase shifter 10 shifts the phase of the output signal of the VCO 16 by 90°, and the PLL
This is to correct the fact that the output signal of the VCO 16 is delayed by 90 degrees with respect to the color burst signal 11a when the color burst signal 11a is locked.

The output signal b at the output terminal 10a of the 90° phase shifter 10 is sent to the ACK phase detector 13. The ACK phase detector 13 performs phase detection between the output signal b of the 90° shifter 10 and the color burst signal 11a, and sends the output signal c from the output terminal 13a to the first input terminal of the AND gate 17. It's summery.

Further, the ACK amplitude detector 14 performs amplitude detection of the color burst signal 11a, and its output terminal 1
The output signal d from 4a is sent to the second input terminal of an AND gate 17, and the output signal of the AND gate 17 is sent to a pulse count circuit 18.

The output terminal of this pulse count circuit 18 is connected to a terminal 19, and the ACK
The signal is now being extracted.

Figure 2 shows the color killer circuit of this invention.
This figure shows the specific circuit configuration of the circuit that performs ACK processing, and shows the details of the ACK phase detector 13, ACK amplitude detector 14, AND gate 17, and pulse count circuit 18 in FIG. It is.

In FIG. 2, a color burst signal 11a input to a terminal 11 is transmitted to a multiplier 20 and an amplifier 2
I am trying to send it to 1. This multiplier 20,
A burst gate pulse BG input from a terminal 22 is applied to the amplifier 21.

During this period of the burst gate pulse BG, the multiplier 20 multiplies the color burst signal 11a and the reference signal, that is, the output signal b of the 90° phase shifter 10 in FIG. It is now output. This ACK
An output signal e, which is the same as the output signal c of the ACK phase detector 13 shown in FIG. A reference voltage E1 is applied to the other input terminal of the comparator 23. The output terminal of the comparator 23 is connected to a set terminal S of a flip-flop circuit (hereinafter referred to as FF) 24.

On the other hand, the amplifier 21 outputs the burst gate pulse BG
During the interval, the color burst signal 11a is amplified and sent to one input terminal of the comparator 25. A reference voltage E2 is applied to the other input terminal of the comparator 25.

From the output terminal of comparator 25 to
A signal corresponding to the output signal d of the ACK amplitude detector 14 is sent to the set input terminal S of the FF 26.

The reset input terminal R of these FF24, 26 has
A burst gate pulse BG is inputted via an inparator 27. Both FF24,
26 output terminals are the first and second output terminals of AND gate 17.
The output signal e of this AND gate 17 is sent to a counter 28.

The counter 28 and the hysteresis circuit 29 constitute the pulse count circuit 18 shown in FIG. 1, and the output signal of the counter 28 is sent to the hysteresis circuit 29. The output terminal of the hysteresis circuit 29 is connected to the terminal 19, and the ACK signal is taken out from the terminal 19 in the same manner as in FIG.

Note that a head switching pulse P is input to the terminal 30, thereby resetting the counter 28.

Next, the operation of this invention will be described with reference to FIG. 2. For phase detection of color burst signal 11a, burst gate pulse BG
The color burst signal 11a is multiplied by the output signal of the 90° phase shifter 10, that is, the reference signal b, by the multiplier 20, and the output is sent to the ACK filter 22.
After obtaining a voltage according to the input phase difference, it is compared with the reference voltage EI by the comparator 23, and FF2
4, the waveform is shaped to obtain a pulse train.

The ACK filter 22 in this path is the multiplier 20
This is to attenuate the frequency component twice that of reference signal b generated at the output of NTSC.
Since the signal is 7.16MHz, this ACK
The capacitor used for the filter 22 may be of small capacity, and may be built into the IC.

The output of the FF 24 thus obtained is a pulse train that generates pulses only when the phase difference between the color burst signal 11a and the reference signal b is within a certain range centered around zero.

On the other hand, for amplitude detection of the color burst signal 11a, the color burst signal 11a is amplified by a fixed gain amplifier 21, its output is compared with a reference voltage E2 by a comparator 25, the waveform is shaped by an FF 26, and a pulse train is generated. get.

The output of the FF 26 thus obtained is a pulse train that generates a pulse every 1H when the amplitude of the color burst signal 11a is above a certain level.

Thereafter, the two pulse trains output from the FFs 24 and 26 are sent to the AND gate 17, where they are ANDed, and a counter 28 forming the pulse count circuit 18 counts the number of pulses for a certain period of time. In a VTR, for example, a head switching pulse SP (period: 525H) is used for this counting period. This can be set by resetting the counter 28 at the edge of this pulse.

ACK based on the result of this count and the previous state.
The hysteresis circuit 29 is used to provide hysteresis characteristics to the on/off threshold so that the state does not easily change.
After performing digital hysteresis processing, the ACK signal is output from the output terminal 19.

FIG. 3 is a waveform diagram of each part for explaining the operation of FIGS. 1 and 2, FIGS. 3a to 3e.
1 and 2 show signals a to f in FIGS. 1 and 2, respectively. FIG. 3 shows the operation when the amplitude of the color burst signal 11a is large and the APC circuit is in a locked state. At this time, the output signal e of the output terminal 17a of the AND gate 17 generates continuous pulses every 1H as shown in FIG. 3e.

In addition, the color burst signal 11a in FIG.
This is the operation when the amplitude of is small and the APC circuit is in a locked state. At this time, it is the output terminal 25 of the comparator 25. At this time, since no pulse is generated in the output signal d of the output terminal 25a of the comparator 25, no pulse is generated in the output terminal 17a of the AND gate 17.

Furthermore, the color burst signal 11 in FIG.
Although the amplitude of a is large, it shows the operation when the APC circuit is in an unlocked state. At this time, a pulse train having a height corresponding to the input phase difference is generated at the output terminal 23a of the ACK filter 23, and its envelope corresponds to the beat signal.

Therefore, the output signal 24a of the FF 24 has a phase difference between the input signals, which is determined by the phase detection sensitivity and the comparator 2.
A pulse train is generated only when the voltage is below a certain value determined by the reference voltage E1 of No. 3, and a similar pulse example is generated at the output terminal 17a of the AND gate 17.

This pulse train is counted by a counter 28 for a certain period of time, and killer on/off is determined based on the counted value. In the case of Figure 3, the killer must be off, and in the case of , the killer must be on.

Now, the input phase difference range where the pulse is generated is ±θ
(deg) and the counting period is sufficiently large compared to the beat signal period, then the pulse generation rate is
Set to 2θ/360. Therefore, as a ratio of the pulse count number to the total number of pulses, the killer-on level is selected to be a value slightly larger than 2θ/360, the killer-off level is selected to be a value close to "1", and a hysteresis circuit 29 is set between these two levels. A good killer function can be achieved by providing hysteresis characteristics. Furthermore, if the two comparators in the phase detection system have analog hysteresis characteristics, even more reliable hysteresis characteristics can be obtained.

[Effects of the Invention] As described above, according to the color killer circuit of the present invention, the electrolytic capacitor with a capacitance of several μF, which was conventionally attached externally to the color signal processing IC of a VTR, can be replaced with a capacitor of a small capacitance (several + PF). can be a capacitor,
Built-in IC is also possible. Therefore, it is possible to reduce component prices, reduce the board area, and reduce the number of IC pins, thereby reducing costs around the IC.

Furthermore, digitalization is possible to a greater extent than in the past, and low-frequency processing reduces power consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the color killer circuit of the present invention, Fig. 2 is a circuit diagram showing a specific configuration of the circuit portion that performs ACK processing in the color killer circuit of the above, and Fig. 3 is a block diagram of an embodiment of the color killer circuit of the above. Signal waveform diagrams of each part to explain the operation of the killer circuit,
Figure 4 is a block diagram of a conventional color killer circuit.
FIG. 5 is a signal waveform diagram of each part for explaining the operation of the color killer circuit of FIG. 4. 10...90° phase shifter, 12...APC detector, 1
3...ACK phase detector, 14...ACK amplitude detector, 15...APC filter, 16...VCO, 1
7...AND gate, 18...Pulse count circuit, 20...Multiplier, 22...ACK filter,
23, 25... Comparator, 24, 26... Flip-flop circuit, 28... Counter, 29
...Hysteresis circuit.

Claims (1)

[Claims] 1. Amplitude detection means for detecting the amplitude of the color burst signal at the time of burst gate for each horizontal period of the color video signal; a phase detection means for performing phase detection between the color burst signal and the reference signal at the time of the burst gate; and the amplitude detection means. A color killer circuit comprising: a pulse count circuit that counts a pulse signal obtained by ANDing the output of the phase detection means and the output of the phase detection means for a predetermined period and operates the color killer according to the counted number.