JPH0588036U - Clock pulse phase adjustment circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In the receiving system of digital data communication, the phase of the sampling clock pulse with respect to the input digital data is always properly and automatically adjusted. [Structure] A clock pulse CK ₀₁ having a phase synchronized with input digital data D _I1 and having a data communication frequency is generated by a clock pulse generation circuit 1, and this clock pulse C
K _{01 is applied} to the clock pulse delay circuit 2 for delay time control signal S
delayed make delayed clock pulse CK _d1 in response to _dc, the delay time control in accordance with the comparison judgment signal S _det at the delayed clock pulse CK _d1 sample and hold has been a delay data D _d1 and the input digital data D _I1 The circuit 5 generates the delay time control signal S _dc .

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to automatic phase adjustment of clock pulses in a digital data communication receiving system or a digital data reproducing system from a data recording medium.

[0002]

[Prior Art]

 Digital data received or reproduced in a receiving system for asynchronous data communication that does not transmit a clock pulse separately from the data signal, or in a digital data reproducing system from a data storage medium that also does not reproduce a clock pulse separately from the data signal. Is generally sampled by a clock pulse having a frequency equal to the data communication speed and held to synchronize the data with the clock pulse, thereby facilitating data processing in the subsequent stage. In order to correctly sample and hold the input data, this clock pulse that synchronizes the data needs to be sampled and held around the switching point of the data where the signal amplitude is unstable as digital data.

In particular, when the distortion of the signal waveform of the input data is large, when the slew rate of the sampling and holding circuit with respect to the data frequency is not sufficiently high, or when the slew rate of the sampling and holding circuit varies widely, If the data cycle has time-axis fluctuations, it is necessary to adjust the phase of the clock pulse to the data so that the optimum sampling and holding timing can be obtained while the actual sampling and holding circuit is operating. is there.

As shown in FIG. 7A, a conventional clock pulse phase adjusting circuit is a clock pulse that generates a clock pulse CK ₀₂ having a frequency that is phase-locked to the input digital data D _I2 and is equal to the data communication speed. The generation circuit 6 and the clock pulse delay circuit 7 which receives the clock pulse C K ₀₂ as an input, outputs the delayed clock pulse CK _{d2 in} which the phase of the clock pulse CK ₀₂ is delayed, and has a variable delay time. Is configured.

In this circuit, as shown in FIG. 7b, the phase of the delayed clock pulse CK _d2 to be output is adjusted by the delay time variable function of the clock pulse delay circuit 7 so that the coordinator or a machine equivalent thereto actually operates the circuit. input waveform Oh Rui digital data D _I2 observes and phase relationship between the delayed clock pulse CK _d2 waveform or both and delayed clock pulses CK _d2 of delay data D _d2 sampled hold by while being The delay time T _d2 in the clock pulse delay circuit 7, that is, the phase of the delayed clock pulse CK _d2 is adjusted so as to obtain a timing that allows stable and error-free sample and hold.

[0006]

[Problems to be solved by the device]

 In such a conventional clock pulse generation circuit, not only time is required for adjustment, but also when humans make adjustments, quality variations due to human factors occur, and adjustments are also made when making adjustments by machines. It is said that the adjustment point at the time of completion of adjustment may not always be optimal due to changes in the characteristics of the circuit including the adjuster due to changes in the environment such as temperature and humidity after completion, and differences in the input signal waveform. There was a problem.

Therefore, an object of the present invention is to automatically adjust the phase of the clock pulse and to perform the automatic phase adjustment constantly or at any time during the operation of the circuit so that the time required for the adjustment can be eliminated and the variation in the quality due to the adjustment can be eliminated. The purpose of the present invention is to provide a circuit that always generates a clock pulse adjusted to an appropriate phase even when the environment changes or the waveform characteristic of input data changes.

[0008]

[Means for Solving the Problems]

 Therefore, in order to achieve the above-mentioned object, the present invention provides a clock pulse generator that is phase-locked to input digital data and generates a clock pulse having a frequency equal to the data communication speed. Then, the clock pulse delay unit that outputs the delayed clock pulse whose phase is delayed according to the delay time control signal from the delay time control unit and the delayed clock pulse and the digital data are input, and the delay clock pulse A data delay section that holds digital data at the time of rising or falling and outputs delay data, a data comparison section that compares and judges the delay data and digital data, and outputs a judgment signal, and Delay control that outputs a delay time control signal that changes the phase delay time of the clock pulse delay unit It is those with a door.

[0009]

[Action]

 The delayed clock pulse generated by the present invention becomes an automatically appropriate phase-adjusted clock pulse that solves the above problems.

[0010]

【Example】

 Next, an embodiment of the present invention will be described with reference to FIGS.

In FIG. 1, reference numeral 1 denotes a clock pulse generation circuit, which generates a clock pulse CK ₀₁ having a frequency which is phase-synchronized with the input digital data D _I1 and is equal to the data communication frequency. As shown in FIG. 2, the clock pulse generating circuit 1 detects the synchronization of the input digital data D _{I1 with} the synchronization detector 8 and oscillates at the data communication frequency so as to be in phase synchronization with the detected synchronous signal S _sy. It is realized by an oscillating circuit having a phase-locked loop (PLL) configuration for controlling the voltage-controlled oscillator 10.

The clock pulse delay circuit 2 shown in FIG. 1 receives a clock pulse CK ₀₁ generated by the clock pulse generation circuit 1 and generates a delayed clock pulse CK _d1 by phase-delaying the clock pulse CK _01. It has a function of being changed by a delay time control signal S _dc from a delay time control circuit 5 which will be described later. For example, as shown in FIG. 3a, it is triggered by the rising edge of the signal input to the input terminal D, and the time constant terminal T This can be realized by the monostable multivibrator 12 and the inverter 13 in which the width T _d of the output pulse CK ₁₁ is determined by the product of the resistance value R and the capacitance C of each of the resistors and capacitors connected to. The operation of the clock pulse delay circuit 2 is, as shown in FIG. 3b, a pulse CK ₁₁ having a falling timing obtained by delaying the rising of the clock pulse CK ₀₁ input by the monostable multivibrator 12 by a delay time T _d. Is generated and inverted by the inverter 13, the delayed clock pulse C K _{d1 in} which the rising edge of the clock pulse CK ₀₁ is delayed by T _d is obtained. Further, the delay time T _d can be varied by connecting the capacitors C ₁ , C ₂ , C ₃ , ..., C _n that determine the time constant of the monostable multivibrator 12 with the delay time control signal S _dc . This can be realized by controlling the switches SW ₁ , SW ₂ , SW ₃ , ..., SW _n on or off. The data delay circuit 3 shown in FIG. 1 is, for example, a circuit which samples and holds the input digital data D _I1 at the rising _edge of the delayed clock pulse CK _d1 generated by the clock pulse delay circuit 2, and thereby the delayed clock pulse C The delay data D _d1 delayed from the input digital data D _I1 by the delay time T _{d with} respect to the clock pulse CK ₀₁ of K _d1 is output. This circuit can be realized by a D flip-flop 14 as shown in FIG. 4, for example.

In the data comparison circuit 4 shown in FIG. 1, the input digital data D _I1 and the delay data D _d1 from the data delay circuit 3 are equal at the time when the data delay circuit 3 completes the sample _hold of the data. Whether or not it is compared, and the determination signal S _det is output. Here, when the input digital data D _I1 and the delay data D _d1 are equal, the phase of the delayed clock pulse CK _d1 which is the timing of sample and hold input to the data delay circuit 3 is appropriate, and conversely both are If they are not equal, it is inappropriate. The data comparison circuit 4 can be realized by a logic circuit as shown in FIG. 5, for example. Here, the timing immediately after the sample and hold of the data in the data delay circuit 3 is generated by further delaying the delayed clock pulse CK _d1 by the delay circuit 15, and at this timing, the input digital data D _{The I1} and the delay data D _d1 are sampled and held by the D flip-flops 16 and 17, respectively, and both outputs are judged by the exclusive OR 18 to determine whether they are equal to each other and output as a judgment signal S _det . In this example, the determination signals S _det are “0” if they are equal and “1” if they are not equal.

The delay time control circuit 5 shown in FIG. 1 receives the judgment signal S _det “1” indicating that the input digital data D _I1 and the delay data D _d1 are not equal in the data comparison circuit 4, That is, when the phase of the delayed clock pulse CK _d1 is inappropriate, the delay time control signal S _dc controls the delay time in the clock pulse delay circuit 2. For example, in the case where the data comparison circuit 4 is a circuit as shown in FIG. 5, the determination signal S _det becomes “1” when the input digital data D _I1 and the delay data D _d1 are not equal to each other. When this is input to the circuit as shown in FIG. 6a, which is the embodiment, the output of the logical product 19 is the pulse CK _det only during the period when the determination signal S _det is “1” as shown in FIG. 6b. When this pulse CK _det is counted by the binary counter 20, binary count values are output to Q ₁ , Q ₂ , ..., Q _n . This output is used as the delay time control signal S _dc to connect the time constant capacitors C ₁ , C ₂ , C ₃ , ..., C _n for determining the delay time of the clock pulse delay circuit 2 shown in FIG. 3a, respectively. The delay time is changed by turning on or off by the changeover switches SW ₁ , SW ₂ , SW ₃ , ..., SW _n . When the input digital data D _I1 and the delay data D _d1 become equal, the judgment signal S _det becomes “0” and the pulse CK _det is not input to the clock input CLK of the binary counter, so the count outputs Q ₁ , Q ₂ , ... , Q _n retains the previous state, and therefore the delay time of the delay clock pulse CK _d1 also remains the previous time. This condition provides the proper delayed clock pulse phase.

[0015]

[Effect of the device]

 As described above, the present invention operates so that the phase of the delayed clock pulse that generates the timing for sampling and holding the input digital data is changed until it becomes appropriate, and when it becomes appropriate, the phase is held. This has the result that it is possible to automatically generate a delayed clock pulse adjusted to an appropriate phase automatically.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a clock pulse generation circuit according to FIG.

FIG. 3 is a block diagram showing a clock pulse delay circuit according to FIG. 1 and a timing chart explaining its operation.

FIG. 4 is a block diagram showing a data delay circuit according to FIG.

5 is a block diagram showing a data comparison circuit according to FIG. 1. FIG.

FIG. 6 is a block diagram showing a delay time control circuit according to FIG. 1 and a timing chart explaining its operation.

FIG. 7 is a block diagram showing an embodiment of a conventional clock pulse generation circuit and a timing chart explaining its operation.

[Explanation of Codes] 1,6 Clock pulse generation circuit 2,7 Clock pulse delay circuit 3 Data delay circuit 4 Data comparison circuit 5 Delay time control circuit 8 Synchronization detector 9 Phase comparator 10 Voltage controlled oscillator 11 Divider 12 Monos Table multivibrator 13 Inverter 14, 16, 17 D Flip flop 15 Delay circuit 18 Exclusive OR 19 Logical product 20 Binary counter C _{0 to} C _n Time constant capacitor CK ₀₁ , CK ₀₂ Clock pulse CK _d1 , CK _d2 delayed clock pulse CK _det S _det ANDed CLK clock input terminal D data input terminal D _d1, D _d2 delay data D _I1, D _I2 input data Q output terminal Q ₁ to Q _n 2 binary counter counts the CK ₀₁ Output R Time constant resistor S _dc Delay time control signal S _det judgment signal S _e Phase comparison error signal S _sy Sync signal SW ₁ ~ SW _n Time constant switch T Time constant terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H03K 5/13 4239-5J 5/135 4239-5J H03L 7/06 H04L 7/02 // G11B 20 / 14 321 Z 8322-5D

Claims (1)

[Scope of utility model registration request] 1. A clock pulse generator that is phase-synchronized with input digital data and that generates a clock pulse having a frequency equal to the data communication speed, and a delay from a delay time control unit by inputting this clock pulse. A clock pulse delay unit that outputs a delayed clock pulse whose phase is delayed according to a time control signal, and this delayed clock pulse and digital data are input, and digital data is held at the rising or falling edge of the delayed clock pulse. Then, the data delay unit that outputs the delay data, the data comparison unit that compares and determines the delay data and the digital data, and outputs the determination signal, and the phase delay time of the clock pulse delay unit is changed according to the determination signal. A delay time control section for outputting a delay time control signal for The phase adjustment circuit of the pulse.