JPH0587839B2 - - Google Patents

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a character generator used in dot printers, character displays, etc. Concerning a character generator to store.

(Prior Art) The size of the dot matrix of graphic characters used in display devices, dot printers, etc. that display and output graphic characters including kanji is horizontal x
16 x 16, 24 x 24, and 32 x 32 dots are common, and 24 x 24 dot matrices are often used, especially from the viewpoint of device characteristics and readability.

The graphic character dot pattern may be provided individually for each device, or may be provided at one location in the entire system and shared by a plurality of devices. In either case, the storage area of the dot pattern corresponding to the externally specified graphic character code (2-byte JIS code is often used) is read and sent to the output device. At this time, a read-only mask ROM is often used as a storage device for dot patterns.

In recent years, due to the higher integration and lower cost of mask ROMs, even low-priced devices such as word processors, personal computers, and small terminal devices are increasingly equipped with dot patterns. Further, especially in dot printers, a 24×24 dot matrix is very often used for ease of viewing and aesthetics. Due to these circumstances, 24x24 dot matrix graphic characters have already been standardized by JIS. Therefore,
A conventional example will be explained below based on the drawings, taking a 24×24 dot matrix graphic character as an example.

FIG. 9 shows an example of the configuration of a 24×24 dot matrix character generator using a conventional method.
The figure shows a 1M bit (8 bits x 128kW) mask.
This is an example using ROM, in which a 24 x 24 dot matrix is divided into three partial matrices of 8 horizontal x 24 vertical dots, and a maximum of 4096 characters can be accommodated in 3 mask ROM chips.

The example shown in FIG. 9 is for reading in the row direction (horizontal direction) and is mainly used for CRT displays.
Also, in the case of column direction (vertical direction) readout, which is mainly used in serial printers, in the same way as for row direction readout, it is divided into three partial matrices of 24 horizontal dots x 8 vertical dots, and each is stored in a 1M bit mask ROM3 chip. Can accommodate up to 4096 characters.

FIG. 10 is a block diagram of a dot pattern generating section in a CRT display using the mask ROM shown in FIG. 9, which stores dot patterns as described above, as a character generator. Below, an outline of the operation of outputting a dot pattern from inputting a character code will be explained.

In FIG. 10, the control unit 1 converts a character code specified from the outside, generates a character address indicating the first address where a one-character dot pattern is stored, and transfers it to the address register 2. At the same time, 5-bit row address counter 3
Clear.

Next, mask the outputs of address register 2 and row address counter 3 as ROM addresses.
Accesses ROMs 4 to 6 and transfers the ROM output data (dot pattern) to the CRT display section. Furthermore, row address counter 3 is incremented (+
1) Do.

This operation is repeated 24 times, and 3 bytes of data for one character x 24 times = 72 bytes are output. When a new character code is specified, the above operation is repeated.

When converting a dot pattern into ROM, in order to make the dot pattern easier to access,
The number of pattern bytes of one character occupying a ROM1 chip is 2 to the power of n (n is a positive integer), that is,
2, 4, 8, 16, 32, etc., and as shown in FIG. 10, it is necessary to completely separate the start address (character address) of the dot pattern from the row address.

(Problems to be Solved by the Invention) However, in the case of conventional character generators, the total number of dots divided into 8 dots, such as a 16 x 16 dot pattern or a 32 x 32 dot pattern, is As mentioned above, there is no problem in the case of a pattern configuration that is 2 to the nth power, but if the number divided into 8 dot units is not 2 to the n power, such as a 24 x 24 dot pattern, the conventional method will not work. mask
There will be empty space in the ROM. In the example shown in FIG. 9, although the number of bytes per character required for one ROM chip is 24 bytes, a capacity of 32 (2 ⁵ ) bytes is required.
This creates an unused area of 32 bytes - 24 bytes = 8 bytes per character, and looking at the entire mask ROM, 4096 characters x 8 bytes per ROM =
It is 32588 bytes, which is actually one-fourth of the ROM capacity.
There was a problem in that it was wasted.

In addition, in order to eliminate the waste mentioned above and improve the utilization efficiency of ROM capacity, if the dot pattern data is packed and stored without creating an unused area, the 10th
It becomes impossible to completely separate character addresses and row addresses as shown in the figure, and the ROM access method becomes complicated. At this time, if address conversion for ROM access is implemented using hardware, the amount of hardware will increase significantly and is not practical. In addition, even if address conversion is performed by software, it will take several steps to execute the instruction, so particularly high-speed access is required.
It is not practical for CRT displays.

The present invention is to effectively use the unused area of the mask ROM described above, thereby increasing the number of dot patterns that can be accommodated in the same number of ROM chips as in the past, and furthermore, using simple and small amount of hardware. An object of the present invention is to provide a character generator that enables dot pattern access in a computer.

(Means for Solving the Problems) The present invention is directed to a character generator that stores graphic patterns including characters, symbols, and Chinese characters in units of dots. In such a character generator, the present invention provides a first block in which dot patterns of one graphic character are successively stored, and a block provided between the first blocks. and a second block in which the pattern is divided into a plurality of blocks and stored. Then, a plurality of consecutive blocks within the second block are combined to store a dot pattern of one graphic character.

(Function) According to the present invention, the dot pattern of one graphic character is stored in a form divided into a plurality of parts in the second block between the first blocks, which was wasted in the conventional character generator. Therefore, the number of graphic character dot patterns stored in the character generator can be increased. The dot pattern can be read out from the character generator in the same manner as before for the first block, and for the second block, it can be read out by combining a plurality of consecutive blocks in this block. A dot pattern of graphic characters is read out.

(Example) The present invention will be explained below based on one embodiment.

FIG. 1 is a block diagram of a character generator showing an embodiment of the present invention.

This example uses 1M bits (8 bits x 128kW)
A character generator is constructed by using three mask ROMs to store a character pattern consisting of 24 x 24 dots.

In the figure, the characters "a", "i" to "ku" are patterns stored in a conventional manner. 1
Divide the character dot pattern into a partial matrix of 8 horizontal x 24 vertical dots x 3 blocks, and divide each block into
Since data is stored every 32 bytes, there is an unused area of 8 bytes between patterns that are stored one after the other.

Next, for the characters ``kan'' and ``ji'', the dot pattern is divided into partial matrices of 8 x 8 dots x 9 blocks, and each block is divided into the dot patterns of the characters ``a'', ``i'', and ``ku''. It is stored in an unused area (an area of 8×8 dot units) that can be created between the two. At this time, in order to easily access the dot patterns, between the dot patterns that are stored one after the other, such as the characters ``kan'' and ``ji,'' dot patterns are stored using the conventional method. An unused area for one character that can be created when
Leave the .

According to this embodiment, three conventional mask ROMs are required.
Although it was possible to store dot patterns for 4096 characters, it is now possible to additionally store dot patterns at a ratio of one character to every four, so with the same number of ROM chips as before, it can store dot patterns for 4096 + 4096/4 = 5120 characters. It becomes possible to store dot patterns.

FIG. 2 shows a code table of the mask ROM in this embodiment. In the figure, bits _CA12 to _CA0 indicate the start address (character address) where the dot pattern of each character is stored. In the figure, the lower 7 bits (CA ₆ to CA ₀ ) of the character addresses CA ₁₂ to CA ₀ are shown as the X-axis coordinates.
Further, the code table is expressed by assigning the upper 6 bits (CA ₁₂ to CA ₇ ) to the Y-axis coordinate. Also, the lower 7 bits (CA ₆ to CA ₀ ) are displayed in hexadecimal 00 to 7F, and the upper 6 bits (CA ₁₂ to _{CA 7} ) are displayed in binary.
Displayed as 000000 to 111111.

The characters whose dot patterns are stored using the conventional method are a total of 4096 characters in the range of CA ₁₂ = 0 shown in Figure 2.
Applies to characters. Also, CA _{12, 11, 10} are respectively 1,
A total of 1024 characters in the range 0, 0 (shaded area) is the area of the dot pattern that can be newly accommodated by this embodiment. The character “A” shown in Figure 3
"KU" is a character pattern stored in the range of CA ₁₂ = 0 in the code table in Figure 2, and the characters "Kan" and "JI" are stored in CA _{12, 11, 10} in the same diagram. These are character patterns stored in the range of 1, 0, and 0, respectively.

Next, a method of accessing the character generator constructed according to the present invention will be explained based on the drawings.

FIG. 3 is a block diagram showing an example of a character pattern generating section in an output device using a character generator according to the present invention.

The control section 1 has the same function and operation as the control section 1 shown in FIG. 10, except for the output of the character address CA ₁₂ . Further, the address register 2 and the row address counter 3 are each
It is completely the same in function and operation as the address register 2 and row address counter 3 in FIG.

Character addresses CA ₁₂ and CA ₁₁ to CA ₀ are respectively CA ₁₂ and CA ₁₁ to CA 0 in FIG.
Compatible with CA ₀ .

The control unit 1 converts the character code specified from the outside and outputs the corresponding character address CA ₁₂ to _{CA 0.}
is transferred to address register 2. The operation of the row address counter 3 at this time is the first one described above.
The operation of the row address counter in FIG.

The selection circuit 7 first determines whether the ₁₂ bits of the character address CA output from the address register 2 are 0 or 1. If CA ₁₂ = 0, character addresses CA ₁₁ to CA ₀ are each set as a ROM address.
Output in correspondence with A ₁₆ to ₅ . Additionally, row addresses RA ₄ to RA ₀ are set to ROM addresses A ₄ to RA 0, respectively.
Output in correspondence with A ₀ . ROM address A ₄ ~
A ₀ is as row address counter 3 increments.
Counting is performed 24 times from 00000(2) to 11000(2), and a dot pattern for one character is obtained by ROM output data of 24 bits x 24 times.

FIG. 4a shows the character address CA ₁₂ =0.
This shows the bit correspondence of character addresses, row addresses, and ROM addresses in the case of . In addition, Figure 4b shows the character address
The bit correspondence of the character address, row address, and ROM address when CA ₁₂ =1 is shown.

In this embodiment, the character pattern in the area marked with ○ shown in FIG. 2 is stored between the character patterns in the area of character addresses CA _{11 to 10} 00(2) on the actual ROM. It is something. Similarly, the areas ○Ro, _○ C, and ○D in FIG. Stored between patterns. In addition, character addresses CA _{11 to 10} in the areas ○A, ○B, ○C, and ○D shown in Fig. 2 are all 00(2), so CA _{11 to 10} in Fig. 4B are always 00. (2) becomes. Furthermore, the areas ○A, ○B, ○C, and ○D shown in Figure 2 are distinguished by character addresses CA _{6 to 5} (○I is
00(2), ○Ro is 01(2), ○C is 10(2), ○D is 11(2)).

FIG. 5 shows an example of the configuration of the selection circuit 7 in FIG. 3 when the bit patterns shown in FIGS. 4a and 4b are used. As can be seen from the figure, the selection circuit 7 can be realized with a simple multiplexer circuit. When the Sel line of the multiplexer circuit is 0, that is, the character address CA ₁₂ =0, the A side input of the multiplexer circuit is selected and output. Also, the Sel line is 1, that is, the character address CA ₁₂
When =1, the B side input is selectively output. Therefore, when character address CA ₁₂ = 0, the fourth
The bit conversion shown in figure a is performed, and CA ₁₂ =1
In this case, the bit conversion shown in FIG. 4b is performed.
In this case, the row address counter 3 in FIG. 3 is incremented, and the row addresses _RA4 to _RA0 are 00000(2) to
Counted 24 times to 11000(2).

FIG. 8 shows changes in the ROM address accessed when the character address CA ₁₂ =1. Row address RA _4~0 is 00000(2)~
When counted 24 times to 11000(2), the figure shows ~
addresses are accessed sequentially. The 8 consecutive addresses×3 blocks accessed here correspond to the area in which the dot pattern of the character ``Kan'' or ``character'' in FIG. 1 is stored. By assembling the 8 addresses x 3 blocks, the character address CA ₁₂ = 1 shown in Figure 2 is obtained.
The dot pattern of characters in the area (1024 characters) can be read out.

FIG. 6 shows another configuration example of bit conversion when character address CA ₁₂ =1. In this configuration example, the bit orders of character addresses CA _6-5 and CA _9-7 are swapped. In other words, the above-mentioned ○I,
Character addresses CA _{6 to 5} for distinguishing the respective areas of ○B, ○C, and ○D are character addresses.
It is assigned to the upper two bits A _{16 to 15} of the ROM address corresponding to CA _{11 to 10} .

When bit conversion is performed in the case of character address CA ₁₂ =1 as shown in FIG. 6, the multiplexer circuit constituting the selection circuit 7 is constructed as shown in FIG. As can be seen from the figure, character addresses CA 9 to CA ₇ when character address CA ₁₂ =0 shown in FIG. 4A can be directly used as address inputs of ROM chips 1 to 3. Therefore, for example 4
When using a bit input multiplexer, the fifth
In the configuration shown in the figure, the number of inputs of the multiplexer circuit is 14.
Since it is a book, four multiplexers are required, whereas in the configuration shown in FIG. 7, the number of inputs of the multiplexer circuit is 11, so three multiplexers may be used. Therefore, by using the bit conversion shown in FIG. 6, the number of multiplexer elements can be reduced.

(Effects of the Invention) As described above in detail, according to the present invention,
Mask ROM that was previously unused and wasted
It becomes possible to divide and store the character dot pattern in the address area of . This allows the ROM
improved utilization of address space for the same number of addresses.
Even when a ROM chip is used, the number of characters that can be accommodated can be increased.

In the case where a character pattern consisting of 24 x 24 dots is stored in the ROM3 chip as in the above embodiment, it was possible to store up to 4096 characters in the past, but now it can store up to 5120 characters, an increase of 1024 characters, and the device It can also contribute to downsizing and lowering prices.

Furthermore, the access method requires only adding a simple multiplexer circuit to the conventional circuit, and can be applied to devices such as CRT displays that require high-speed access.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the character generator according to the present invention, FIG. 2 is a diagram showing codes representing the characters accommodated in the character generator shown in FIG. 1, and FIG. FIG. 4 is a diagram showing the address correspondence relationship showing the operation of the selection circuit 7 shown in FIG. 3, and FIG. FIG. 6 is a diagram showing address correspondence relationships showing other operations of the selection circuit 7, FIG. 7 is a diagram showing another example of the configuration of the selection circuit 7,
FIG. 8 is a ROM address diagram showing the correspondence between ROM addresses and data during ROM access, FIG. 9 is a diagram showing an example of the configuration of a conventional character generator, and FIG. FIG. 2 is a block diagram of a dot pattern generating section using a lactage generator. 1...Control unit, 2...Address register, 3...
...Row address counter, 4...ROM chip 1,
5...ROM chip 2, 6...ROM chip 3,
7...Selection circuit.

Claims (1)

[Scope of Claims] A character generator that stores graphic patterns including characters, symbols, and Chinese characters in units of one dot, comprising: a first block in which dot patterns of one graphic character are successively stored; This block is provided between the first block and has a second block in which a dot pattern of one graphic character is divided into a plurality of blocks and stored, and in the second block, a plurality of consecutive dot patterns are stored. A character generator characterized in that a dot pattern of one graphic character is stored by combining blocks.