JPH0586662B2 - - Google Patents

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Publication number
JPH0586662B2
JPH0586662B2 JP58141319A JP14131983A JPH0586662B2 JP H0586662 B2 JPH0586662 B2 JP H0586662B2 JP 58141319 A JP58141319 A JP 58141319A JP 14131983 A JP14131983 A JP 14131983A JP H0586662 B2 JPH0586662 B2 JP H0586662B2
Authority
JP
Japan
Prior art keywords
plate
aln
power semiconductor
semiconductor module
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58141319A
Other languages
Japanese (ja)
Other versions
JPS6032343A (en
Inventor
Masako Nakabashi
Kazumi Shimotori
Hiromitsu Takeda
Tatsuo Yamazaki
Makoto Shirokane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP14131983A priority Critical patent/JPS6032343A/en
Publication of JPS6032343A publication Critical patent/JPS6032343A/en
Publication of JPH0586662B2 publication Critical patent/JPH0586662B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731Ceramic materials or glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0104Zirconium [Zr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Ceramic Products (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はパワー半導体素子の改良に関する。 〔発明の技術的背景とその問題点〕 近年、パワー半導体素子に対する高密度集積
化、ハイブリツド化、更には大電流の制御など、
種々の要求が高まつている。こうした要求を達成
しようとすると、半導体素子より発生する多量の
熱が問題となる。このため、発生する多量の熱を
放出して半導体素子の温度上昇を防ぐ必要があ
る。 このようなことから、従来、放熱基板を用いた
第1図に示すパワー半導体モジユールが多用され
ている。即ち、図中の1はCu等からなるヒート
シンクであり、このヒートシンク1上には後記熱
拡散板との絶縁を図るためのAl2O3からなる第1
絶縁板21が半田層3を介して接合されている。
この絶縁板21上には熱拡散板4が半田層3を介
して接合されている。また、この熱拡散板4上に
は実装すべき半導体素子との絶縁を図るための
Al2O3からなる第2絶縁板22…が半田層3を介
して接合されている。そして、これら絶縁板22
…上には半導体素子5…が半田層3…を介して
夫々接合されている。なお、図中の6…は第1、
第2の絶縁板21,22…と半田層3の間に形成さ
れた接合層である。 しかしながら、従来のパワー半導体モジユール
に用いられる放熱基板は同第1図に示す如く非常
に複雑となる欠点があつた。これは、第1、第2
の絶縁板21,22…を構成するAl2O3は耐圧が
100KV/cmと良好であるものの、熱伝導率が
20W/m・℃と低いために、放熱と絶縁の両機能
をCuとAl2O3の両材料を用いて満足させる必要が
あるからである。 一方、最近、窒素アルミニウム(AlN)は電
気絶縁性(140〜170V/cm)と熱伝導性(60W/
m・℃)が共に優れていることに着目し、これを
Cu部材に接合してモジユール基板を造ることが
試みられている。しかしながら、AlNはろう材
に対する濡れ性が劣るため、銀ろう材等でAlN
部材とCu部材を接合しようとしても充分な接合
強度を得ることはほとんど困難であつた。 〔発明の目的〕 本発明は簡略化された構造で、かつ良好な絶縁
耐圧を有することはもとより放熱特性の優れたパ
ワー半導体モジユール基板を提供しようとするも
のである。 〔発明の概要〕 本発明者らは、電気絶縁性及び熱伝導性が優れ
ているものの、ろう材等との濡れ性の悪いAlN
に対する接合材について鋭意研究を重ねた結果、
TiやZr等の活性金属がAlNに対して良好な濡れ
性を有することを究明し、該活性金属又は活性金
属と銅の合金を用いてAlN部材とCu部材を接合
することによつて、接合強度が高く、既述の如く
簡素化された構造で放熱特性の優れたパワー半導
体モジユール基板を見い出した。 即ち、本発明のパワー半導体モジユール基板は
AlN部材とCu部材とを活性金属層又は活性金属
とCuの合金属を用いて接合してなるものである。 次に、本発明のパワー半導体モジユール基板の
製造方法を説明する。 まず、AlN部材とCu部材の接合部にTi、Zr、
Hfなどの活性金属層又は活性金属とCuの合金層
を介在させる。この工程において、活性金属層等
を前記接合部に介在させる手段としては、例えば
活性金属箔を用いて介在させる方法、或いはCu
部材に活性金属層をスパツタリング法、LPC法
(低圧プラズマコーテイング法)などにより堆積
して介在させる方法等を採用し得る。 次いで、AlN部材とCu部材の接合部を真空雰
囲気或いは不活性雰囲気中にて加熱する。この工
程において、基本的には圧力を加えなくともよい
が、必要に応じて0.01〜1Kg/mm2の低圧を加えて
加熱してもよい。加熱温度はCu部材の融点より
低いことが必要である。具体的には872〜1082℃
の範囲で加熱すればよい。こうした熱処理により
AlN部材とCu部材の間にCuと活性金属の合金融
液が生成され、この後冷却することによりAlN
部材とCu部材とが強固に接合されたパワー半導
体モジユール基板が造られる。 なお、上記加熱工程において、更に加熱を続行
して合金融液をCu部材に拡散させてもよい。こ
のような方法を行なうことによつて、熱衝撃によ
るAlN部材のクラツク発生を防止したパワー半
導体モジユール基板を得ることができる。即ち、
Cu或いは活性金属のような金属とAlNとは熱膨
張係数(Cu;17×10-6/℃、AlN;4×10-6
℃)が大きく異なるため、接合部の温度が上昇し
たり、下降したりすると、その接合部に大きな応
力が生じる。この場合、Cuはその硬度が低く、
柔かいため、前記応力により容易に変形して応力
を緩和し易い。これに対し、CuとTi、Zrなどの
活性金属との合金は硬く、変形し難いため、接合
部にこれら合金層が圧く存在すると、応力の緩和
作用が小さく、AlN部材に応力が加わつてクラ
ツクが発生するものと考える。このようなことか
ら、既述の如く接合部の合金をCu部材に拡散し
てその合金層の厚さを著しく薄くするか、或いは
ほとんど存在しない状態にすることによつて
AlNの熱衝撃によるクラツチ発生を防止できる。
こうした合金の拡散を行なう際は、Cu部材と活
性金属の合金融液を加圧して生成した場合、合金
融液が接合部に生成した時に圧力を解除して合金
のCu部材への拡散を行なうことが望ましい。ま
た、合金の拡散を行なう場合には拡散時間を短縮
させる観点から活性金属層の厚さを100μm以下に
することが望ましい。 〔発明の実施例〕 以下、本発明の実施例を図面を参照して説明す
る。 実施例 1 まず、絶縁板、熱放熱板及びヒートシンクを兼
ねたAlN板11と複数枚のCu板12…をトリク
レン及びアセトンで洗浄して脱脂した後、AlN
板11とCu板12…の接合部に厚さ20μmのTi箔
を挿入し、2×10-5torrの真空度に保持したホツ
トプレス中にセツトした。つづいて、AlN板1
1と複数枚のCu板12…間に上下方向から0.1
Kg/mm2の圧力を加え、高周波加熱により接合部を
930℃に保持した。加熱後、30分間未満の時間で
接合部が溶融した。この後、アルゴンガス雰囲気
中で冷却して第2図Aに示す如くAlN板11に
Cu板12…をCuとTiを含む合金層13…を介し
て接合した構造のパワー半導体モジユール基板
4を得た。 得られたモジユール基板14はAlN板11と
Cu板12…とが合金層13…により強固に接合
されたものであつた。 また、前記モジユール基板14のCu板12…
に第2図Bに示す如く半導体素子15…をPd−
Sn系半田16…を介して実装したところ、半導
体素子15…からの多量を熱をCu板12…及び
AlN板11より良好に放出できるパワー半導体
モジユールを得ることができた。 実施例 2 前記実施例1と同様、AlN板とCu板の接合部
を930℃に保持し、該接合部を溶融してCuとTiを
含む合金融液を生成した後、圧力を解除去し、
950℃で96時間保持してCuとTiを含む合金をCu
板に拡散せしめてAlN板とCu板とが接合された
パワー半導体モジユール基板を得た。 得られたモジユール基板の接合部を100倍の光
学顕微鏡で観察したところ、CuとTiを含む合金
層は観察されず、かつAlN板のクラツク発生も
なく、良好な接合状態を有することが確認され
た。また、実施例1と同様、得られたパワー半導
体モジユール基板のCu板上に半導体素子をPd−
Sn系半田を介して実装したところ、半導体素子
からの多量の熱を良好に放出できると共に、
AlN板のクラツク発生のない高信頼性のパワー
半導体モジユールを得ることができた。 実施例 3 まず、複数枚のCu板12…及びCu製熱拡散板
17を夫々トリクレン及びアセトンで脱脂した
後、これらCu板12…、熱拡散板17の片面に
60torr、アルゴン雰囲気の条件の低圧プラズマ溶
射法により厚さ30μmのCu−Ti合金層(72重量%
Cu−28重量%Ti)を堆積した。つづいて、熱拡
散板17のCu−Ti合金層上に表面がトリクレン
及びアセトンで洗浄されたAlN板11を載せ、
更にAlN板11上に複数枚のCu板12…を該Cu
板12…片面上のCu−Ti合金層がAlN板11側
に位置するように載せ、2×10-5torrの真空度に
保持したポツトプレス中にセツトした。ひきつづ
き、上方のCu板12…と下方の熱拡散板17の
間に上下方向から0.1Kg/mm2の圧力を加え、高周
波加熱によりAlN板1とCu板12…、及びAlN
板1と熱拡散板17の接合部を900℃に保持した。
加熱後、直ちに各接合部が溶融した。この後、ア
ルゴンガス雰囲気中で冷却してAlN板11の上
面にCu板12…を、AlN板11の下面に熱拡散
板17を、夫々CuとTiを含む合金層13′…を介
して接合した。次いで、熱拡散板17の下面に
Cu製ヒートシンク18をPd−Sn系半田16を介
して接合し第3図Aに示すパワー半導体モジユー
ル基板14′を製造した。 得られたモジユール基板14′はAlN板11と
Cu板12…、及びAlN板11と熱拡散板17が
夫々合金層13′…により強固に接合されたもの
であつた。 また、前記モジユール基板14′のCu板12…
に第3図Bに示す如く半導体素子15…をPd−
Sn系半田16を介して実装したところ、半導体
素子15…からの多量の熱をCu板12…、AlN
板11、熱拡散板17及びヒートシンク18より
良好に放出できるパワー半導体モジユールを得る
ことができた。 実施例 4 前記実施例3と同様、ポツトプレス中にて
AlN板とCu板、及びAlN板と熱拡散板の夫々の
接合部を900℃に保持し、各接合部を溶融してCu
とTiを含む合金融液を生成した後、圧力を解除
し、更に950℃で96時間保持して各接合部の合金
をCu板、熱拡散板に夫々拡散せしめて接合した。
つづいて、熱拡散板の下面にCu製ヒートシンク
をPd−Sn系半田を介して接合しパワー半導体モ
ジユール基板を製造した。 得られたモジユール基板におけるAlN板とCu
板、及びAlN板と熱拡散板の各接合部を100倍の
光学顕微鏡で観察したところ、CuとTiを含む合
金層は観察されず、かつAlN板のクラツク発生
もなく、良好な接合状態を有することが確認され
た。また、実施例3と同様、得られたパワー半導
体モジユール基板のCu板上に半導体素子をPd−
Sn系半田を介して実装したところ、半導体素子
からの多量の熱を良好に放出できると共に、
AlN板のクラツク発生のない高信頼性のパワー
半導体モジユールを得ることができた。 〔発明の効果〕 以上詳述した如く、本発明によれば簡素化され
た構造で、良好な絶縁耐圧を有することはもとよ
り、放熱特性の優れたパワー半導体モジユール基
板を提供できる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in power semiconductor devices. [Technical background of the invention and its problems] In recent years, power semiconductor devices have become increasingly densely integrated, hybridized, and even large current control
Various demands are increasing. Attempting to meet these requirements poses the problem of large amounts of heat generated by semiconductor devices. Therefore, it is necessary to release a large amount of generated heat to prevent the temperature of the semiconductor element from rising. For this reason, conventionally, a power semiconductor module shown in FIG. 1 using a heat dissipation substrate has been widely used. That is, 1 in the figure is a heat sink made of Cu or the like, and on this heat sink 1 there is a first plate made of Al 2 O 3 for insulation from the heat diffusion plate described later.
An insulating plate 2 1 is bonded via a solder layer 3 .
A heat diffusion plate 4 is bonded onto this insulating plate 2 1 via a solder layer 3 . Additionally, on this heat diffusion plate 4, there is a
Second insulating plates 2 2 made of Al 2 O 3 are bonded via a solder layer 3 . And these insulating plates 2 2
. . . Semiconductor elements 5 . . . are bonded to each other via solder layers 3 . In addition, 6... in the figure is the first,
This is a bonding layer formed between the second insulating plates 2 1 , 2 2 . . . and the solder layer 3. However, the heat dissipation substrate used in the conventional power semiconductor module has the drawback of being extremely complicated, as shown in FIG. This is the first and second
The Al 2 O 3 constituting the insulating plates 2 1 , 2 2 ... has a withstand voltage.
Although the thermal conductivity is good at 100KV/cm,
This is because it is as low as 20 W/m·°C, so it is necessary to satisfy both the heat dissipation and insulation functions using both materials, Cu and Al 2 O 3 . On the other hand, recently aluminum nitrogen (AlN) has been shown to have electrical insulation (140-170V/cm) and thermal conductivity (60W/cm).
Focusing on the fact that both m and °C) are excellent, this
Attempts have been made to create a modular substrate by bonding it to Cu members. However, since AlN has poor wettability to brazing filler metal, AlN can be used with silver brazing filler metal etc.
Even when attempting to join a member and a Cu member, it was almost difficult to obtain sufficient joint strength. [Object of the Invention] It is an object of the present invention to provide a power semiconductor module substrate which has a simplified structure, good dielectric strength, and excellent heat dissipation characteristics. [Summary of the Invention] The present inventors discovered that although AlN has excellent electrical insulation and thermal conductivity, it has poor wettability with brazing filler metals, etc.
As a result of extensive research into bonding materials for
It was discovered that active metals such as Ti and Zr have good wettability with AlN, and by joining AlN members and Cu members using the active metals or an alloy of active metals and copper, bonding was achieved. We have found a power semiconductor module board that has high strength, has a simplified structure as described above, and has excellent heat dissipation characteristics. That is, the power semiconductor module board of the present invention is
It is formed by joining an AlN member and a Cu member using an active metal layer or an alloy of active metal and Cu. Next, a method for manufacturing a power semiconductor module board according to the present invention will be explained. First, Ti, Zr,
An active metal layer such as Hf or an alloy layer of an active metal and Cu is interposed. In this step, the method for interposing the active metal layer or the like in the bonding portion includes, for example, a method using an active metal foil, or a method of interposing the active metal layer etc.
A method may be adopted in which an active metal layer is deposited on the member by sputtering, LPC (low-pressure plasma coating), or the like. Next, the joint between the AlN member and the Cu member is heated in a vacuum atmosphere or an inert atmosphere. In this step, it is basically not necessary to apply pressure, but if necessary, a low pressure of 0.01 to 1 Kg/mm 2 may be applied for heating. The heating temperature needs to be lower than the melting point of the Cu member. Specifically, 872-1082℃
You can heat it within this range. Through this heat treatment
A composite liquid of Cu and active metal is generated between the AlN member and the Cu member, and by cooling it, the AlN
A power semiconductor module board is manufactured in which the component and the Cu component are firmly bonded. Note that in the heating step, the heating may be continued to diffuse the alloy liquid into the Cu member. By carrying out such a method, it is possible to obtain a power semiconductor module substrate in which cracks in the AlN member are prevented from occurring due to thermal shock. That is,
Metals such as Cu or active metals and AlN have a thermal expansion coefficient (Cu; 17×10 -6 /℃, AlN: 4×10 -6 /℃).
℃), so when the temperature of the joint increases or decreases, large stresses are generated at the joint. In this case, Cu has low hardness and
Since it is soft, it is easily deformed by the stress and eases the stress. On the other hand, alloys of Cu and active metals such as Ti and Zr are hard and difficult to deform, so if these alloy layers exist tightly at the joint, the stress relaxation effect will be small and stress will be applied to the AlN member. I think that a crack will occur. For this reason, as mentioned above, by diffusing the alloy in the joint into the Cu member and making the thickness of the alloy layer extremely thin, or almost non-existent.
Clutching caused by thermal shock of AlN can be prevented.
When diffusing such an alloy, if the alloy liquid of the Cu member and the active metal is pressurized and generated, when the alloy liquid forms at the joint, the pressure is released and the alloy is diffused into the Cu member. This is desirable. Further, when diffusing the alloy, it is desirable that the thickness of the active metal layer be 100 μm or less from the viewpoint of shortening the diffusion time. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Example 1 First, an AlN plate 11 that also serves as an insulating plate, a heat dissipation plate, and a heat sink, and a plurality of Cu plates 12... are cleaned and degreased with trichlene and acetone, and then AlN
A Ti foil with a thickness of 20 μm was inserted into the joint between the plate 11 and the Cu plate 12, and set in a hot press maintained at a vacuum level of 2×10 -5 torr. Next, AlN plate 1
1 and multiple Cu plates 12...0.1 from the vertical direction between
Apply a pressure of Kg/mm 2 and use high-frequency heating to seal the joint.
It was held at 930°C. After heating, the joint melted in less than 30 minutes. After that, it is cooled in an argon gas atmosphere and formed into an AlN plate 11 as shown in FIG. 2A.
A power semiconductor module substrate 1 having a structure in which Cu plates 12 are bonded via an alloy layer 13 containing Cu and Ti.
I got 4. The obtained module substrate 14 is connected to the AlN plate 11.
The Cu plates 12 were firmly joined by the alloy layers 13. Further, the Cu plate 12 of the module board 14 ...
As shown in FIG. 2B, the semiconductor elements 15... are Pd-
When mounted via the Sn-based solder 16..., a large amount of heat from the semiconductor element 15... is transferred to the Cu plate 12...
It was possible to obtain a power semiconductor module that can emit light better than the AlN plate 11. Example 2 As in Example 1, the joint between the AlN plate and the Cu plate was held at 930°C, the joint was melted to produce a composite liquid containing Cu and Ti, and then the pressure was removed. ,
The alloy containing Cu and Ti was heated to 950°C for 96 hours.
A power semiconductor module substrate was obtained in which an AlN plate and a Cu plate were bonded together by diffusion into the plate. When the bonded area of the resulting module substrate was observed under a 100x optical microscope, no alloy layer containing Cu and Ti was observed, and no cracks occurred in the AlN plate, confirming a good bonding condition. Ta. In addition, as in Example 1, semiconductor elements were placed on the Cu plate of the obtained power semiconductor module substrate using Pd-
When mounted using Sn-based solder, a large amount of heat from the semiconductor element can be dissipated well, and
We were able to obtain a highly reliable power semiconductor module with no cracks in the AlN plate. Example 3 First, after degreasing a plurality of Cu plates 12... and the Cu heat diffusion plate 17 with trichlene and acetone, one side of each of the Cu plates 12... and the heat diffusion plate 17 was degreased.
A 30 μm thick Cu-Ti alloy layer (72 wt%
Cu−28 wt% Ti) was deposited. Next, an AlN plate 11 whose surface has been cleaned with trichlene and acetone is placed on the Cu-Ti alloy layer of the heat diffusion plate 17.
Furthermore, a plurality of Cu plates 12... are placed on the AlN plate 11.
Plate 12 was mounted so that the Cu--Ti alloy layer on one side was located on the AlN plate 11 side, and set in a pot press maintained at a vacuum level of 2×10 -5 torr. Subsequently, a pressure of 0.1 Kg/mm 2 is applied from above and below between the upper Cu plate 12... and the lower heat diffusion plate 17, and the AlN plate 1, Cu plate 12... and AlN are heated by high frequency heating.
The joint between plate 1 and heat diffusion plate 17 was maintained at 900°C.
After heating, each joint melted immediately. Thereafter, the Cu plate 12 is bonded to the upper surface of the AlN plate 11, and the heat diffusion plate 17 is bonded to the lower surface of the AlN plate 11 via alloy layers 13' containing Cu and Ti, respectively, by cooling in an argon gas atmosphere. did. Next, on the bottom surface of the heat diffusion plate 17
A heat sink 18 made of Cu was bonded via Pd--Sn solder 16 to produce a power semiconductor module board 14 ' shown in FIG. 3A. The obtained module substrate 14 ' is connected to the AlN plate 11.
The Cu plates 12 . . . and the AlN plates 11 and the heat diffusion plate 17 were each firmly joined by alloy layers 13 ′. Further, the Cu plate 12 of the module board 14 '...
Then, as shown in FIG. 3B, the semiconductor elements 15...
When mounted via Sn-based solder 16, a large amount of heat from semiconductor elements 15... is transferred to Cu plates 12..., AlN
It was possible to obtain a power semiconductor module that can better emit light from the plate 11, the heat diffusion plate 17, and the heat sink 18. Example 4 Similar to Example 3 above, in a pot press
The joints between the AlN plate and the Cu plate, and between the AlN plate and the thermal diffusion plate, are held at 900°C, and each joint is melted and the Cu plate is melted.
After producing an alloy alloy liquid containing Ti and Ti, the pressure was released and the mixture was further held at 950°C for 96 hours to diffuse the alloy at each joint into the Cu plate and the heat diffusion plate, respectively, and bond them.
Next, a Cu heat sink was bonded to the bottom surface of the heat diffusion plate via Pd-Sn solder to produce a power semiconductor module board. AlN plate and Cu in the obtained module substrate
When the joints between the plates and the AlN plates and the heat diffusion plate were observed using an optical microscope at 100x magnification, no alloy layer containing Cu and Ti was observed, and there were no cracks in the AlN plates, indicating a good bonding condition. It was confirmed that it has. In addition, as in Example 3, semiconductor elements were placed on the Cu plate of the obtained power semiconductor module substrate using Pd-
When mounted using Sn-based solder, a large amount of heat from the semiconductor element can be dissipated well, and
We were able to obtain a highly reliable power semiconductor module with no cracks in the AlN plate. [Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a power semiconductor module substrate with a simplified structure, not only having good dielectric strength but also excellent heat dissipation characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の放熱基板を有するパワー半導体
モジユールを示す断面図、第2図Aは本発明の実
施例1におけるパワー半導体モジユール基板を示
す断面図、同図Bは同図Aのモジユール基板に半
導体素子を実装したパワー半導体モジユールの断
面図、第3図Aは本発明の実施例3におけるパワ
ー半導体モジユール基板を示す断面図、同図Bは
同図Aのモジユール基板に半導体素子を実装した
パワー半導体モジユールの断面図である。 11……AlN板、12……Cu板、13,1
3′……合金層、1414′……パワー半導体モ
ジユール基板、15……半導体素子、16……半
田、17……熱拡散板、18……ヒートシンク。
FIG. 1 is a sectional view showing a power semiconductor module having a conventional heat dissipation board, FIG. 2A is a sectional view showing a power semiconductor module board in Embodiment 1 of the present invention, and FIG. FIG. 3A is a sectional view of a power semiconductor module board in Embodiment 3 of the present invention, and FIG. FIG. 2 is a cross-sectional view of a semiconductor module. 11...AlN board, 12...Cu board, 13,1
3'... Alloy layer, 14 , 14 '... Power semiconductor module board, 15... Semiconductor element, 16... Solder, 17... Heat diffusion plate, 18... Heat sink.

Claims (1)

【特許請求の範囲】 1 窒化アルミニウム(AlN)部材と銅(Cu)
部材とを活性金属層又は活性金属と銅の合金層を
用いて接合してなるパワー半導体モジユール基
板。 2 活性金属がTi又はZrであることを特徴とす
る特許請求の範囲第1項記載のパワー半導体モジ
ユール基板。
[Claims] 1. Aluminum nitride (AlN) member and copper (Cu)
A power semiconductor module board formed by bonding components to each other using an active metal layer or an alloy layer of active metal and copper. 2. The power semiconductor module substrate according to claim 1, wherein the active metal is Ti or Zr.
JP14131983A 1983-08-02 1983-08-02 Power semiconductor module substrate Granted JPS6032343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14131983A JPS6032343A (en) 1983-08-02 1983-08-02 Power semiconductor module substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14131983A JPS6032343A (en) 1983-08-02 1983-08-02 Power semiconductor module substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6300702A Division JP2519402B2 (en) 1994-12-05 1994-12-05 Method for manufacturing power semiconductor module substrate

Publications (2)

Publication Number Publication Date
JPS6032343A JPS6032343A (en) 1985-02-19
JPH0586662B2 true JPH0586662B2 (en) 1993-12-13

Family

ID=15289145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14131983A Granted JPS6032343A (en) 1983-08-02 1983-08-02 Power semiconductor module substrate

Country Status (1)

Country Link
JP (1) JPS6032343A (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847445A (en) * 1985-02-01 1989-07-11 Tektronix, Inc. Zirconium thin-film metal conductor systems
JPH0738424B2 (en) * 1986-08-07 1995-04-26 昭和電工株式会社 Hybrid integrated circuit board and manufacturing method thereof
JPH0738423B2 (en) * 1986-08-07 1995-04-26 昭和電工株式会社 Hybrid integrated circuit board and manufacturing method thereof
JP2573225B2 (en) * 1987-02-10 1997-01-22 株式会社東芝 Electronic component manufacturing method
EP0326077B1 (en) * 1988-01-25 1995-04-12 Kabushiki Kaisha Toshiba Circuit board
JP3011433B2 (en) * 1990-05-25 2000-02-21 株式会社東芝 Manufacturing method of ceramic circuit board
JPH0497966A (en) * 1990-08-09 1992-03-30 Ngk Spark Plug Co Ltd Production of ceramic sliding parts
JP3845925B2 (en) 1996-02-05 2006-11-15 住友電気工業株式会社 Semiconductor device member using aluminum nitride substrate and method for manufacturing the same
KR100371974B1 (en) 1997-05-26 2003-02-17 스미토모덴키고교가부시키가이샤 Copper circuit junction substrate and method of producing the same
JP3794454B2 (en) * 1998-09-16 2006-07-05 富士電機ホールディングス株式会社 Nitride ceramic substrate
JP2000335983A (en) * 1999-05-28 2000-12-05 Denki Kagaku Kogyo Kk Production of conjugate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175972A (en) * 1974-12-26 1976-06-30 Ngk Insulators Ltd Seramitsukuno metaraijinguhoho
JPS53102310A (en) * 1977-02-18 1978-09-06 Tokyo Shibaura Electric Co Heat conducting base plates
JPS56163093A (en) * 1980-04-21 1981-12-15 Bbc Brown Boveri & Cie Activated wax and manufacture of thin sheet consisting of said wax
JPS5848926A (en) * 1981-09-18 1983-03-23 Hitachi Ltd Insulated type semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175972A (en) * 1974-12-26 1976-06-30 Ngk Insulators Ltd Seramitsukuno metaraijinguhoho
JPS53102310A (en) * 1977-02-18 1978-09-06 Tokyo Shibaura Electric Co Heat conducting base plates
JPS56163093A (en) * 1980-04-21 1981-12-15 Bbc Brown Boveri & Cie Activated wax and manufacture of thin sheet consisting of said wax
JPS5848926A (en) * 1981-09-18 1983-03-23 Hitachi Ltd Insulated type semiconductor device

Also Published As

Publication number Publication date
JPS6032343A (en) 1985-02-19

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