JPH0585868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention is applicable to devices having a plurality of signal generators, such as a press safety device or a level crossing obstacle detection device. Regarding a scanner that scans for abnormalities, n-channel signal generators are sequentially driven by the output of a ring counter, and the pulse output of each signal generator is input to one of the input terminals of an AND gate provided with n-channels. At the same time, this pulse signal and the signal input from the preceding AND gate through the delay circuit to the other input terminal cause the AND gate to perform self-holding operation one after another to advance the counting operation, and all of the signal generators When the signal generator is normal, an output is obtained from the final stage AND gate, and if an abnormality occurs, the counting operation will not proceed to the final stage AND gate. and other circuit failures.

<Prior art> Fig. 6 is a block diagram showing an example of a conventional scanner, in which 1 is a pulse generator, 2 is a ring counter,
3 is a group of signal generators, and 4 is a monitoring circuit.

The ring counter 2 counts the pulses input from the pulse generator 1, and sequentially supplies the counting output to each signal generator 31 to 3n of the signal generator group 3.
This is driven repeatedly.

The signal generators 31 to 3n are obstacle detection circuits formed by, for example, a combination of a light emitting element and a light receiving element.
The output signals of the signal generators 31 to 3n are input to the monitoring circuit 4.

The monitoring circuit 4 includes flip-flops individually corresponding to the signal generators 31-3n. Flop circuits 411-41
n, and this flip. Flop 411-41
n is set by the output of the signal generators 31 to 3n, and the delay circuit 42 is set from the ring counter 2.
It is designed to be reset by a signal applied through terminals 1 to 42n.

Vs is the operating power supply of the signal generators 31 to 3n.

When the signal generators 31 to 3n are normal, the flip . Flop 411-41n
are set by the outputs of the corresponding signal generators 31-3n, and the delay circuits 421-42n
Since each flip . of the monitoring circuit 4 is reset by . From flops 411 to 41n, almost
A pulse having a width corresponding to the delay time of the delay circuits 421 to 42n is output.

However, if an abnormality occurs in the signal generators 31 to 3n, normal output cannot be obtained from the signal generator in which the abnormality has occurred, so that the corresponding flip. Flop not set.

Therefore, flip. By looking at the flops 411-41n, it can be seen that among the signal generators 31-3n,
The signal generator causing the failure can be identified.

<Problems to be Solved by the Invention> However, in the conventional scanner described above, the signal generators 31 to 3n are not in a normal state;
For example, even if a signal cannot be generated, the flip flops constituting the monitoring circuit 4. Flop 411-4
If a circuit failure occurs in 1n or the delay circuits 421 to 42n, a normal monitoring output may be generated.

Further, since independent monitoring systems are formed in accordance with the number n of signal generators 31 to 3n, and the monitoring output of each monitoring system must be viewed individually, processing of the monitoring output is troublesome.

<Means for Solving the Problems> In order to solve the above-mentioned conventional problems, the present invention provides a pulse generator, a ring counter that counts pulses output from the pulse generator, and a ring counter for counting the pulses output from the pulse generator. In a scanner that includes a plurality of signal generators whose outputs are scanned and a monitoring circuit that monitors the outputs of these signal generators, a plurality of the monitoring circuits are provided corresponding to the signal generators, and the monitoring circuits are configured to scan the outputs of the previous stage and Generating an output to the next stage using the output generation from the signal generator as an input condition, and feeding back a part of the output to the next stage to the input side to which the output generation from the signal generator is applied. The structure includes an AND gate forming a self-holding circuit, and a delay circuit inserted between the output side of the AND gate and the input side of the next-stage AND gate, and the AND gate is connected to the final stage of the ring counter. It is characterized by being reset by counting output.

<Function> The scanner described above sequentially drives the signal generators equipped with n channels by the output of the ring counter that counts the pulses of the pulse generator, and the pulse output of each signal generator is This pulse signal is input to one of the input terminals of the AND gate, and this pulse signal is input to the other input terminal from the AND gate in the previous stage via a delay circuit. Let me go. This sequential self-holding operation of the AND gate is a type of counting operation. Then, by utilizing the fact that when all of the signal generators are normal, an output is obtained from the AND gate at the final stage, and when an abnormality occurs, the counting operation will not proceed to the AND gate at the final stage. It monitors the signal generator for normality, abnormality, and other circuit failures. The AND gate is reset by the final count output (n+1) of the ring counter, thereby returning to its initial state.

The monitoring circuit is provided with AND gates corresponding to the signal generators, and each of the AND gates generates an output to the next stage using the output of the previous stage and the output generation from the signal generator as input conditions, and also generates an output to the next stage. Since a part of the output of the signal generator is fed back to the input side to which the output generation of the signal generator is applied to form a self-holding circuit, the output generation sequentially applied from the signal generation circuit is ANDed, and all An AND of n output occurrences is obtained at a given time. For this reason,
If the AND condition cannot be obtained in the middle, the subsequent AND cannot be obtained, so the fail-safe property is higher than the conventional method of taking AND outputs of the outputs of each flip-flop. In other words, if one of the AND gates fails and then appears normal when it recovers from the failure and obtains the final AND output, the AND output cannot be obtained because n ANDs cannot be obtained. Therefore, the fail-safe property is improved.

Since a delay circuit is inserted between the output side of the AND gate and the input side of the next stage AND gate,
Even if the delay circuit breaks down and the delay time is incorrect,
Since n times of AND cannot be obtained within a certain period of time, the fail-safe property becomes high.

Since the AND gate is reset with the final count output of the ring counter, it can be reliably determined whether or not n times of ANDs have been obtained within a certain period of time, resulting in high fail-safety.

<Embodiment> FIG. 1 is an electrical circuit connection diagram in an embodiment of the scanner according to the present invention. In the figure, the same reference numerals as in FIG. 6 indicate the same components. In this embodiment, the signal generator 3 is a simple n-channel signal generator 31 to 3 by optical coupling.
n, and each of the signal generators 31 to 3n sequentially scans the transistors 31a to 3na with the n output pulses from the ring counter 2 to generate a light emitting diode 31b to 3nb.
emit light, and the phototransistors 31c to 3nc
It is designed to receive light. 31d, 31e~
3nd and 3ne are resistances.

The ring counter 2 includes signal generators 31a to 31n.
In addition to the output terminals (1 to n) for outputting n count pulses for scanning, there is also an output terminal (n+) for outputting the final count pulse as a reset signal.
1).

The phototransistors 31c to 3nc of the signal generators 31 to 3n have their collectors connected in common, and are further input to the monitoring circuit 4 via a coupling capacitor 5 and an amplifier 6.

The monitoring circuit 4 monitors (n+1) of the ring counter 2.
An AND is performed using the th counting pulse and the output generation from the signal generator 31 as input conditions, and the resistor 451
A fail-safe AND gate 43 that self-holds the input signal from the signal generator 31 by feeding back a part of the output to the input side through the gate, and generates an output to the next stage.
1 and the output of the previous stage and the output generation from the group of signal generators 32 to 3n as input conditions,
Fail-safe AND gates 432-43n that feed back part of the output to the input side through resistors 452-45n, self-hold the signals input from the signal generators 32-3n, and generate outputs to the next stage;
It is configured to include delay circuits 441 to 44n _-1 inserted between the output side of the AND gate and the input side of the next-stage AND gate so that the delay time will not be shortened due to circuit failure.

The AND gates 431 to 43n are connected to the signal generator 3
n channels are provided so that the number is the same as 1 to 3n. Each of the AND gates 431 to 43n includes coupling capacitors C1 to Cn and clamp diodes _D11 to D1n to clamp the input signal to the power supply voltage Vs in order to input signals from the signal generators ₃₁ to _3n . and input terminals A ₁ to An that are input via diodes D ₂₁ to _{D 2} n for inputting only the positive input signal to the AND gate, and delay circuits 441 to 44n _-1 for outputting from the AND gate in the previous stage. It is equipped with input terminals B ₂ to Bn for inputting data through the input terminals.
Furthermore, each of the AND gates 431 to 43n connects a resistor 451 from the output side to the input terminal A ₁ to An.
It has a feedback circuit of ~45n.

Furthermore, the input terminal B ₁ of the AND gate 431 has
Diode D ₁ clamps the input signal to the voltage Vs
r, a coupling capacitor Cr connected to the output side of the inverting amplifier 7, and a diode D ₂ r that passes only the positive input signal. When the output pulse of the final count output terminal (n+1) of the ring counter 2 is at a low level, the output of the inverting amplifier 7 is at a high level.
When a signal is input to the input terminal A ₁ from the input terminal A 1 , an AND condition between the input terminal B ₁ and the input terminal A ₁ is established, and this input signal is self-held through the feedback circuit formed by the resistor 451 . On the other hand, when the output pulse of the final count output terminal (n+1) of the ring counter 2 becomes a high level, the output of the inverting amplifier 7 becomes a low level, so the AND condition between the input terminal B ₁ and the input terminal A ₁ is not satisfied. The self-holding operation of the AND gate 431 is canceled, and along with this, the self-holding operation of the subsequent AND gates 432 to 43n is also sequentially canceled. Therefore, the high level of the output pulse at the final count output terminal (n+1) of the ring counter 2 becomes the reset signal.

Further, the AND gates 432 to 43n input the delayed output signals to the input terminals _B2 to Bn through the delay circuits 441 to 44n- ₁ , and then output the delayed output signals from the signal generators 32 to
When the signal from 3n is input to the input terminals A ₂ to An, a self-holding operation is performed by feedback provided through the resistors 452 to 45n.

The AND gates 431 to 43n are configured as a combination of AND operation oscillators OS ₁ to OSn and rectifier circuits RC ₁ to RCn, which do not generate an output in the event of a failure. Such AND operation oscillators OS ₁ to OSn and rectifier circuit RC ₁ are known, for example, in Japanese Utility Model Application Publication No. 57-4764 and Japanese Patent Publication No. 51-38211.

Figure 2 shows an example of an AND operation oscillator disclosed in these publications.
Tr ₁ and Tr ₂ are directly connected, and _the collector of transistor Tr ₂ is connected to the base of transistor Tr ₃ via Zener diode ZD ₁ .
Zener diode ZD ₂ connected to the collector of
The connection point between the resistor _R3 and the resistor _{R3 is connected to the base of the transistor Tr1} through the resistor _R4 . R ₁ and R ₂ are collector resistances, A and B are input terminals, and Vs is the potential of the power supply input terminal.

In the AND operation oscillator shown in FIG _. 2, Zener voltages Vz ₁ , Vz ₂ (usually Zener voltages _{Vz 1 ,}
(Vz ₂ is selected to be slightly larger than the power supply voltage Vs) When a higher potential voltage is input, that is, when the potential of input terminals A and B becomes a potential outside the power supply range, transistors Tr ₁ to _{Tr 3} are turned on in sequence. , the OFF operation is repeated, and an oscillation output that oscillates between the input voltage level applied to the input terminal B and substantially zero level is obtained at the output terminal C. On the other hand, if the input voltage applied to input terminals A and B does not reach a sufficient level to operate transistors Tr ₁ to _{Tr 3} , or if a disconnection failure occurs in the circuit, the oscillation operation will stop. Therefore, no output is generated at output terminal C.

Next, FIG. 3 shows a specific embodiment of the rectifier circuits RC ₁ to RCn, and includes a diode D ₁ s for clamping the AC voltage Vo given from the AND operation oscillators OS ₁ to OSn to the power supply potential Vs, and a rectifier for rectification. The circuit has a circuit configuration in which rectification and smoothing is performed by a diode D ₂ s and a four-terminal smoothing capacitor C ₂ s, and a rectified output is obtained from an output terminal D. C ₁ s is a coupling capacitor. This rectifier circuit loses rectified output when a disconnection failure or the like occurs.

In addition, when operating with a negative power supply, convert the PNP transistor and NPN transistor to each other,
The direction of the diode may be reversed to make the input signal a negative voltage.

The input circuit on the input terminal B ₁ side of the AND operation oscillator OS ₁ has a capacitor Cr and a diode D ₂ r connected in series, and a capacitor Cr and a diode D ₂
The configuration is such that a clamping diode D ₁ r is connected to the connection point with r.

In addition, the input terminals of the AND operation oscillators OS ₂ to OSn
Capacitors C ₁ , C ₂ , ...Cn and diodes D ₂₁ , D ₂₂ , ...D ₂ n are connected in series to A ₁ to An, and capacitors C ₁ to Cn and diodes D ₂₁ to D ₂ n are connected in series.
Clamp diodes D ₁₁ to D ₁ n at the connection point with
are connected, and the amplifier 6 supplies the outputs of the signal generators 31 to 3n.

Delay circuits 441 to 44n _-1 output from AND gates 431 to 43n _-1 having self-holding circuits,
After a certain delay time _T1 , the signal is input to the input terminals _B2 to Bn of the self-holding circuit at the next stage. These delay circuits 441 to 44n _-1 are configured as delay circuits whose delay time is not extended due to failure. Such a delay circuit, for example, as shown in _FIG .
This can be achieved by combining this with a normal capacitor _C3 . However, if the capacitor lead wire breaks and there is no output, use a four-terminal capacitor as shown by capacitor _C3 in Figure 4.

In Figure 1, 8 is the AND gate 4 at the final stage.
A relay driver 9 is driven by the AC output of 3n, and a relay 9 is driven by this relay driver 8.

Next, the operation will be explained with reference to the time chart shown in FIG. First, as shown in FIG. 5a, clock pulses CL ₁ , CL ₂ , CL ₃ are supplied from the pulse generator 1 at regular intervals such as t ₁ , t ₂ , t ₃ .
Corresponding to ..., (n+1) of ring counter 2
Pulses are sequentially output from output terminals 1 to (n+1).
_P1 to Pn ₊₁ are outputted, and the signal generators 31 to 3n of the signal generating section 3 are sequentially scanned by n pulses _P1 to Pn.

If the signal generators 31 to 3n are normal, outputs are generated sequentially from the signal generators 31 to 3n in response to scanning by the pulses P ₁ to Pn described above, and the capacitor 5, amplifier 6, and capacitor C ₁
~Cn and diodes _D21 ~ _D2n to input terminals _A1 ~An of AND gates 431~43n.

Here, in a steady state when the output pulse of the final count output terminal (n+1) of the ring counter 2 is at a low level and the output of the inverting amplifier 6 is at a high level as shown in FIG. 5c, Since the input voltage of the input terminal B ₁ of the AND gate 431 in the first stage also becomes high level, the signal generator 31 is scanned by the first pulse P ₁ and its output is input to the AND gate 431. When the input is input to the terminal A ₁ , the input logic at the input terminals A ₁ and B ₁ of the AND gate 431 is arranged, and at the same time, an output is generated.
With the addition of a self-holding operation by the feedback circuit of resistor 451, the scanning result of signal generator 31 is stored in AND gate 431. Therefore, as shown in FIG. 5d, the output of the AND gate 431 has a logic value of 1, almost coinciding with the time t ₁ when the first pulse P ₁ is generated. The output of the AND gate 431 is the ON/OFF signal of the delay circuit 441. Due to the delay operation, the signal is input to the input terminal _B2 of the AND gate 432 in the next stage after a predetermined delay time _T1 .

Next, at time _t2 , the signal generator 32 is scanned by the second pulse _P2 , and its output is input to the input terminal _A2 of the AND gate 432.
The other input terminal B ₂ has already been connected to the AND gate 431
Since the self-holding output of is inputted through the delay circuit 441, the input logic of the AND gate 432 is arranged and the output becomes a logical value 1. At the same time, a self-holding operation is applied by the feedback circuit formed by the diode 452, and the output becomes a logical value 1. is maintained in the state of

The other signal generators 33 to 3n are scanned in the same manner. When no abnormality occurs in the signal generators 33 to 3n, the output of the AND gate 43n at the final stage becomes a logical value 1 at time tn due to the n-th pulse, and the relay driver 8 is operated by that output. Then, relay 9 is activated.

After the n-th pulse Pn is generated, the ring counter 2 outputs (n+1) as shown in Figure 5c.
The th pulse P(n ₊₁ ) is generated. This pulse P
(n ₊₁ ) is input as a reset pulse to the input terminal B ₁ of the first-stage AND gate 431, and resets the AND gate 431. When AND gate 431 is reset and its output becomes logic 0, the remaining AND gates 432 to 43n are reset one after another and return to their original state. By repeating the above operations, scanning of the signal generators 31 to 3n is performed.

On the other hand, if an abnormality occurs in even one of the signal generators 31 to 3n, the number of pulses given from the signal generator 3 to the monitoring circuit 4 becomes less than n,
Before reaching the final AND gate 43n,
Since the reset takes a long time, the relay driver 8 and relay 9 do not operate. Therefore, it is no longer necessary to individually view the monitoring output of each monitoring system as in the conventional case, and it is possible to know whether the signal generators 31 to 3n as a whole are normal or abnormal.

Next, fail-safe properties will be explained.

First, the fail-safe property based on the structure of the invention described in claim 1 will be explained.

The monitoring circuit 4 includes AND gates 431 to 43n corresponding to the signal generators 31 to 3n, and each of the AND gates 431 to 43n uses the output of the previous stage and the output generation from the signal generators 31 to 3n as input conditions. Since it generates an output to the next stage and also returns a part of the output to the next stage to the input side to which the output generation of the signal generators 31 to 3n is applied to form a self-holding circuit, the signal generating circuits 31 to 3n form a self-holding circuit. The output generation sequentially given from 3n is ANDed, and when all n output generation are given, the AND of the n output generation is obtained. Therefore, if the AND condition cannot be obtained in the middle, the subsequent AND cannot be obtained, so the fail-safe property is higher than the conventional method of taking AND outputs of the outputs of each flip-flop. That is, AND gates 431 to 43n
If one of them fails, and it appears to be normal when it recovers from the failure and obtains the final AND output, the AND output cannot be obtained because n ANDs cannot be obtained, and the fail-safe property becomes higher.

Since the delay circuits 441 to 44n-1 are inserted between the output side of the relevant AND gate and the input side of the next-stage AND gate, even if the delay circuit fails and the delay time is incorrect, the delay time will be delayed within a certain period of time. Since n-time AND operations cannot be obtained, the fail-safe property becomes high.

Since the AND gates 431 to 43n are reset with the final counting output of the ring counter 2, it is possible to reliably determine whether or not n times of ANDs have been obtained within a certain period of time, thereby increasing fail-safety.

Next, fail-safe properties in specific examples will be explained.

First, the AND operation oscillators _OS1 to OSn and the rectifier circuits _RC1 to which constitute the AND gates 431 to 43n
If a circuit failure occurs in RCn, no output will be generated. Therefore, the count does not advance to the AND gate 43n at the final stage, and its output has a logic value of 0, which is fail-safe.

Next, if a circuit failure occurs in the delay circuits 441 to 44n _-1 , if the delay capacitor (C ₃ in Figure 4) is a four-terminal capacitor, the delay time will not become shorter and the count will not proceed. direction and is fail-safe.

Furthermore, regarding the input circuit of each AND gate, fail-safe properties are maintained as follows.

(a) Failure of capacitors Cr, C ₁ to Cn When short-circuited, an input voltage higher than the power supply is not applied to the input terminals A ₁ to An and B ₁ , so the AND operation oscillators OS ₁ to OSn do not oscillate. Furthermore, since no pulse signal is input during an open fault, the AND operation oscillators OS ₁ to OSn do not oscillate.

(b) Failure of diodes D ₁ r, D ₁₁ to D ₁ n When a short circuit occurs, no pulse signal or lit signal is received. When the capacitors are open, there is no route for discharging the charges accumulated in the capacitors Cr, C ₁ to Cn, so pulses cannot be input.

(c) Failure of diodes D ₂ r, D ₂₁ to D ₂ n Self-holding operation is not performed when short-circuited. For example, if the diode D ₂₂ of the AND operation oscillator OS ₂ is short-circuited, a discharge current will flow from the diode D ₁₂ to the capacitor C ₂ when the input pulse disappears, so that the input terminal A ₂ will be at the potential Vs. It then stops oscillating and cannot maintain itself. Also, pulses cannot be input when it is open.

(d) Failure of resistors 451 to 45n If it is open, it will not hold itself, and if it is shorted, the capacitor C ₃ of delay circuit 441 to 44n _-1
is input in parallel to the input, so the AND operation oscillator OS ₁
No pulse signal is input to input terminal A ₁ ~An of ~OSn.

Next, in response to an abnormality in the counting function, the following operation is performed, which is fail-safe.

(E) Runaway of ring counter 2 A normal monitoring output is obtained within the tracking range, but if scanning becomes too fast, the delay circuits 441 to 44
The counter of the monitoring circuit 4 does not increment due to the delay of n _-1 .

(f) If the count is stopped, or pulses are dropped from the signal generators 31 to 3n to the monitoring circuit 4, or two or more channels simultaneously supply pulses, the number of counts in the AND gates 431 to 43n is insufficient, and the AND gate in the final stage is The output of 43n becomes zero,
It is fail safe.

(g) If a delay failure occurs in the middle of counting, the number of counts will be insufficient while the delay continues, and no output will be generated at the final stage AND gate 43n during that time. After the normal function is restored, normal monitoring operation resumes.

(H) Light emitting diode 31 of signal generators 31 to 3n
If a continuous light emission failure occurs in d to 3nd, continuous output will occur and no alternating current output will be obtained. Therefore, since the monitoring circuit 4 does not respond, the counting operation does not proceed and the output of the final stage AND gate 43n is zero, resulting in a fail-safe situation.

<Effects of the Invention> As described above, the present invention sequentially drives the n-channel signal generators by the output of the ring counter, and the pulse output of each signal generator is driven by the output of the ring counter. This pulse signal is input to one of the input terminals of the AND gate, and the signal is input to the other input terminal from the previous AND gate via the delay circuit to cause the AND gate to perform self-holding operation one after another. When all the signal generators are normal, the output is obtained from the AND gate at the final stage, and if an abnormality occurs, the counting operation will not proceed to the AND gate at the final stage. Since the signal generator is utilized to monitor the normality, abnormality, and other circuit failures of the signal generator, it is possible to provide a highly fail-safe scanner with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram of a scanner according to the present invention,
Figure 2 is an electric circuit diagram of an AND operation oscillator that can be used in the present invention, Figure 3 is an electric circuit diagram of a rectifier circuit, Figure 4 is an electric circuit diagram of a delay circuit, and Figure 5 is an electric circuit diagram of a delay circuit.
Figures a to d are time charts for explaining the operation of the scanner according to the present invention, and Figure 6 is a block diagram of a conventional scanner. 1...Pulse generator, 2...Ring counter,
3...Signal generator, 31-3n...Signal generator,
4... Monitoring circuit, 431-43n... AND gate, 441-44n _-1 ... Delay circuit.

Claims (1)

[Claims] 1. A pulse generator, a ring counter that counts pulses output from the pulse generator, a plurality of signal generators that are scanned by the output of the ring counter, and a plurality of signal generators that are scanned by the output of the ring counter. In a scanner equipped with a monitoring circuit for monitoring output, the monitoring circuit is provided in plurality corresponding to the signal generator, and outputs the output to the next stage using the output of the previous stage and the output generation from the signal generator as input conditions. an AND gate that forms a self-holding circuit by feeding back a part of the output to the next stage to the input side to which the output from the signal generator is applied; A scanner comprising: a delay circuit inserted between an input side of an AND gate of a stage, the AND gate being reset by a final count output of the ring counter. 2. The scanner according to claim 1, wherein the AND gate includes an AND operation oscillator that does not generate an output due to a circuit failure, and a rectification circuit that rectifies the output of the AND operation oscillator. . 3. The scanner according to claim 1 or 2, wherein the delay circuit is a circuit whose delay time will not be shortened due to circuit failure.