JP3077075B2 - Power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for determining the cause of a power converter when an abnormality occurs.

[0002]

2. Description of the Related Art As a conventional abnormality detection method for a power conversion device composed of semiconductor elements, for example, Japanese Patent Application Laid-Open No.
As described in JP-A-6463 and JP-A-3-218253, a gate signal supplied from a gate logic circuit to a semiconductor element is compared with a feedback signal for feeding back the state of the semiconductor element to the gate logic circuit. This is a method called non-coincidence detection in which it is determined to be abnormal when they do not match.

[0003]

There are two causes of an abnormality of the power conversion device such as a phase short-circuit due to an abnormality in a gate drive circuit or a semiconductor element and an abnormality in a gate logic circuit that outputs a gate signal. In either case, when the semiconductor element is broken as a result of the occurrence of the abnormality, the mismatch detection is activated. Therefore, the above-described abnormality detection method according to the related art has a problem that the cause of the abnormality cannot be determined. SUMMARY OF THE INVENTION An object of the present invention is to provide a power converter suitable for easily and accurately determining the cause of the occurrence of an abnormality when an abnormality occurs in the power converter.

[0004]

In order to achieve the above object, the present invention comprises first and second semiconductor elements connected in series to both terminals of a DC circuit, and the first and second semiconductor elements are connected in a conjugate relationship with each other. A power converter that is turned on and off by
A gate logic circuit for generating a gate signal for turning on and off the second semiconductor element, a gate drive circuit for driving the semiconductor element, a first transmission circuit and a gate drive circuit for transmitting the gate signal to the gate drive circuit A power converter having a second transmission circuit for transmitting a feedback signal indicating the ON / OFF state of the semiconductor element from the first and second semiconductor element gate signals transmitted to the first transmission circuit. Two failure determination circuits that take logic on each of the feedback signals of the first and second semiconductor elements transmitted to the two transmission circuits and determine an abnormality, and the occurrence of abnormality is gated based on the outputs of the two failure determination circuits. A storage device for storing the outputs of two failure determination circuits for detecting whether the signal is on the signal side or the feedback side. In addition, the first and second four semiconductor elements are connected in series to both terminals of a DC circuit having a neutral point output terminal, and the first and second semiconductor elements are connected to the neutral point output terminal of the DC circuit. Connecting the interconnection point and the interconnection point of the third and fourth semiconductor elements via diodes, respectively; and
A power converter for controlling the first and third semiconductor elements and the second and fourth semiconductor elements to be turned on and off in a conjugate relationship with each other, and a gate signal for turning on and off the first to fourth semiconductor elements. A gate logic circuit, a gate drive circuit for driving the semiconductor element, a first transmission circuit for transmitting a gate signal to the gate drive circuit, and a feedback signal indicating an on / off state of the semiconductor element from the gate drive circuit. In a power converter having a second transmission circuit, gate signals of the first to fourth semiconductor elements transmitted to the first transmission circuit and first to fourth semiconductor elements transmitted to the second transmission circuit Two failure determination circuits that determine the failure by taking the logic for each of the feedback signals of the two. And a storage device for storing the output of the two fault discriminating circuit for detecting whether there either Dobakku side of.

[0005]

According to the present invention, there are provided first and second semiconductor elements connected in series to both terminals of a DC circuit, or first to fourth semiconductor elements connected in series to both terminals of a DC circuit having a neutral point output terminal. For each of the gate signal and the feedback signal of the four semiconductor elements, there is provided a failure discriminating circuit for detecting a switching mode that is impossible for the operation of the power converter. By providing a storage device for storing the output of each failure determination circuit for detecting which side is on the feedback side, when an abnormality is detected from the failure determination circuit that receives a gate signal as an input, or at the same time When an abnormality is detected from the failure determination circuit that receives the feedback signal, an abnormality in the gate logic circuit side and the feedback signal When it is detected only from the failure discrimination circuit which receives, it is the gate drive circuit or the semiconductor device side abnormal, i.e., the cause of the abnormality such as a phase short circuit seen easily and accurately.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes a gate logic circuit that outputs a gate signal for turning on and off a semiconductor element, 2 denotes a gate drive circuit that actually drives the semiconductor element based on the gate signal, and 3 denotes a gate drive circuit that outputs a gate signal. 2, a second transmission circuit for transmitting a feedback signal indicating the ON / OFF state of the semiconductor element from the gate drive circuit 2; 5, a power converter;
Reference numeral 6 denotes a semiconductor element that constitutes the power converter, 7 denotes a failure determination circuit that takes a logic for each of the gate signal and the feedback signal and detects an abnormality, and 8 denotes a storage device that stores an output of the failure determination circuit 7. Here, as the gate signal, 1 is output when the semiconductor element is turned on, and 0 is output when the semiconductor element is turned off. The feedback signal outputs 1 when the semiconductor element is on, and outputs 0 when the semiconductor element is off. Here, one phase of an inverter circuit is shown as an example of the power converter. Normally, in the gate signal for one phase supplied from the gate logic circuit 1, both the semiconductor elements 6a and 6b are not turned on to avoid a power supply short circuit. Therefore, the output F of the gate signal failure determination circuit 7a may be obtained by ANDing the gate signals A and B of the upper and lower arms and outputting the result. The circuit shown in FIG. 3 is used as the failure determination circuit 7a. In FIG.
Is a two-input AND operator, which outputs 0 when normal and 1 when abnormal. Similarly, the circuit shown in FIG. 3 is used as the feedback signal failure determination circuit 7b.

Now, assume that an abnormal gate signal that causes a power supply short circuit is output from the gate logic circuit 1, and as a result, both the semiconductor elements 6a and 6b are turned on. At this time, the gate signals A and B input to the failure determination circuit 7a are 1 respectively, and the output F of the AND
Becomes 1, and the failure determination circuit 7a detects an abnormality. In addition, since both of the semiconductor elements 6a and 6b are turned on, the failure determination circuit 7b also detects an abnormality. The output F of the failure determination circuits 7a and 7b at this time is stored in the storage device 8. On the other hand, although a normal gate signal is output from the gate logic circuit 1, an abnormality occurs in the gate drive circuits 2a, 2b or the semiconductor elements 6a, 6b, and the semiconductor elements 6a, 6b are turned on even though the gate signal is off. Is turned on. At this time, the failure determination circuit 7b detects the abnormality, but the failure determination circuit 7a does not detect the abnormality. Similarly, the storage device 8 stores the failure determination circuits 7a, 7 at this time.
The output F of b is stored. Therefore, it is possible to easily and accurately know which part of the failure determination circuit 7a, 7b has detected the abnormality from the storage of the storage device 8 by detecting which failure determination circuit 7a, 7b has detected the abnormality. That is, when the failure determination circuit 7a detects an abnormality, it means that an abnormal gate signal is output from the gate logic circuit 1, and the gate logic circuit 1
Will have an abnormal cause. At the same time,
Since the failure determination circuit 7b also detects an abnormality, the gate logic circuit 1 can more accurately detect the abnormality by referring to the failure detection of the failure determination circuit 7b, as compared with the case where the cause of the abnormality is specified only by the failure determination circuit 7a. We can know that it is abnormal. In this case, the abnormality detection of the failure determination circuit 7b is performed by the gate drive circuits 2a and 2b and the semiconductor element 6
This means that a and 6b are normal. When only the failure determination circuit 7b detects an abnormality, the gate drive circuits 2a and 2b or the semiconductor elements 6a and 6b
This means that an abnormality has occurred in any of b.

FIG. 2 shows another embodiment in which the present invention is applied to a serial multiplex inverter. For the same objects as in Figure 1,
They have the same numbers. Before describing FIG. 2, a series multiplex inverter will be described. FIG. 4 is a configuration diagram showing a main circuit of the serial multiplex inverter, and shows a circuit for one phase of the serial multiplex inverter. Reference numeral 11 denotes a DC power supply, which connects the smoothing capacitors 12 and 13 connected in series to the DC power supply 11 in parallel. These two smoothing capacitors 1
The interconnection points 2 and 13 are used as power supply neutral points. The switching circuit includes switching elements S1 to S4, flywheel diodes D1 to D4, and clamp diodes CD1 and CD2 for clamping an output terminal U connected to a load to a neutral point potential. The switching elements S1 to S4 constituting this series multiplex inverter are:
It is turned on and off by a gate signal provided from a gate logic circuit (not shown), and its operation is performed by S1, S3 and S3.
Each of 2 and S4 is controlled to turn on and off as a set of inverters in a conjugate relationship with each other. As a result, the relationship between the ON condition and the voltage of the output terminal U is as shown in FIG. For example, when S1 and S2 are turned on (S3, S
4 is off), and the output terminal U has the potential of + E. Conversely, S3
And S4 are turned on (S1 and S2 are turned off), the output terminal U
Is the potential of -E. When S2 and S3 are turned on (S1 and S4 are turned off), the output terminal U is connected to the connection point between the smoothing capacitors 12 and 13 via S2 and S3 and the clamp diodes CD1 and CD2, and the power supply neutral point It is fixed to 0 potential. Simultaneous ON of S1 and S4 is prohibited.
As a result of this operation, the potential of the output terminal U changes between + E, 0, and -E.

Although the configuration and operation of the series multiplex inverter have been briefly described above, in detail, there is a switching mode that transiently passes when the switching mode changes, in addition to the three switching modes described above. FIG. 6 shows all the switching modes. For example, when shifting from the switching mode 1 of S1 on, S2 on, S3 off, S4 off (output terminal potential + E) to the switching mode 2 of S1 off, S2 on, S3 on, S4 off (output terminal potential 0), S1 Is turned off and then S3 is turned on.
It passes through the switching mode 4 of off, S2 on, S3 off, S4 off. This means that if S3 is turned on first, S1,
This is because S2 and S3 are turned on, and the smoothing capacitor 12 is short-circuited. Similarly, S1 off, S2 on,
When shifting from the switching mode 2 of S3 on and S4 off (output terminal potential 0) to the switching mode 3 of S1 off, S2 off, S3 on and S4 on (output terminal potential -E), turn off S2 and then turn on S4. Therefore, it passes through the switching mode 5 of S1 off, S2 off, S3 on, and S4 off on the way. The above switching modes 1 to 5 are the switching modes in the normal operation. Further, as a special switching mode, there is an all-off mode (switching mode 6) which is a state before the inverter starts operating.

There are 2 ⁴ = 16 switching modes for S1 to S4. Of these, six switching modes, mode 1 to mode 6, are permitted, and the remaining ten are prohibited. The switching mode is set. The remaining 10 prohibited switching modes are ON only in S4, S2 and S4
ON only, S2, S3 and S4 ON, S1 ON only,
Only S1 and S4 are on, only S1 and S3 are on, S1 and S3
ON only S4, ON only S1, S2 and S4, S1 and S
This is when only 2 and S3 are on and all of S1 to S4 are on. Therefore, the failure determination circuit may have a logic that outputs 1 when the switching mode is prohibited. Assuming that the logical expressions of the switching elements S1 to S4 are A to D (1 when turned on and 0 when turned off), the logical expression of the failure determination circuit can be simplified by collecting the prohibited switching modes as follows: become.

(Equation 1)

As a result, a failure judgment circuit of the serial multiplex inverter is as shown in FIG. 7, for example. In FIG. 7, 2
Reference numerals 1 and 22 denote NOT operators, 23 to 26 denote 2-input AND operators, and 27 denotes a 4-input OR operator. For example, in the case of switching mode 1 (A = 1, B = 1, C = 0, D = 0), which is a permitted switching mode in FIG. 6, the AND operation unit 23 in FIG. Therefore, the output is 0, and the input of the AND operator 24 is 1,
0, the output is 0, the AND operator 25 has an input of 1,0, the output is 0, and the AND operator 26 has an input of 1,0, the output is 0, and the OR operation is performed. The input of the container 27 becomes 0, and the output F thereof becomes 0. This indicates that it is not abnormal. Similarly, the output F becomes 0 in the switching modes 2 to 6 in FIG.
On the other hand, in modes other than the switching modes 1 to 6, for example, A = 1, B = 1, C = 1, and D = 0, the inputs of the AND operation 24 are both 1 and the output thereof is 1.
As a result, the output F of the OR operator 27 also becomes 1, indicating that an abnormality has occurred. That is, as described above, the output F becomes 1 in all 10 switching modes prohibited. Therefore, in FIG.
By using the failure determination circuit of FIG. 7 for a and 7b, when an abnormality occurs in the gate logic circuit 1, as in the embodiment shown in FIG.
At this time, the failure determination circuit 7b is simultaneously detected. On the other hand, if an abnormality occurs in the gate drive circuits 2a, 2b, 2c, 2d or the semiconductor elements 6a, 6b, 6c, 6d, only the failure determination circuit 7b detects. . Further, the storage device 8 stores all inputs to the failure determination circuits 7a and 7b. Here, both the outputs of the failure determination circuits 7a and 7b or only the output of the failure determination circuit 7b become 1, and when an abnormality is detected, the storage state of the storage device 8 is checked.
It is possible to know which part of the power converter has an abnormality.

In FIG. 2, the output F of the failure determination circuit 7a
The case when is becomes 1 will be described. For example, if the outputs of the gate logic circuit 1 are A = 1, B = 1, C = 1, and D = 0, the output of the AND operator 24 in FIG. 7 becomes 1, and the OR operator 27 outputs 1 I do. As a result, the gate logic circuit 1 outputs an abnormal gate signal, and it can be seen that an abnormal cause has occurred in the gate logic circuit 1. Next, a case where only the output F of the failure determination circuit 7b becomes 1 will be described. For example, if the inputs at this time are A = 1, B = 1, C = 1, D = 0,
From this, switching mode 1 (A = 1, B =
1, C = 0, D = 0), the semiconductor element 6C is erroneously turned on, or the switching mode 2 (A =
0, B = 1, C = 1, D = 0), the semiconductor element 6
It can be inferred that either a is abnormally turned on. Further, the input of the failure determination circuit 7a at this time is the switching mode 2 (A = 0, B = 1, C = 1, D
= 0), it is determined that the semiconductor element 6a is abnormal due to being turned on by mistake.
That is, in this case, it can be understood that the gate logic circuit 1 is normal and the gate drive circuit 2a or the semiconductor element 6a has an abnormality.

[0013]

As described above, according to the power converter of the present invention, when an abnormality occurs in the power converter,
It is possible to easily and accurately determine whether the cause is on the side of the gate logic circuit that generates the gate signal, or on the gate drive circuit or the semiconductor element.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 shows another embodiment of the present invention.

FIG. 3 shows an example of an inverter failure determination circuit.

FIG. 4 is a configuration diagram showing a main circuit of a series multiplex inverter.

FIG. 5 is a diagram illustrating an output voltage corresponding to an ON state of a switching element of a series multiple inverter.

FIG. 6 shows switching modes permitted in a series multiplex inverter.

FIG. 7 shows an example of a failure determination circuit of a serial multiplex inverter.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gate logic circuit 2 gate drive circuit 3 first transmission circuit 4 second transmission circuit 5 power converter 6 semiconductor element 7 failure determination circuit 8 storage device 11 DC power supply 12, 13 smoothing capacitor S1 to S4 switching element D1 to D4 Flywheel diode CD1, CD2 Clamp diode U Output terminal 20 2-input AND operator 21, 22 NOT operator 23-26 2-input AND operator 27 4-input OR operator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 1/00 H02M 7/48 H02M 7/515

Claims (2)

(57) [Claims] A first circuit connected in series to both terminals of a DC circuit;
A power converter for controlling the first and second semiconductor elements to be turned on and off in a conjugate relationship with each other; and a gate signal for turning on and off the first and second semiconductor elements. A gate logic circuit to be generated, a gate drive circuit for driving the semiconductor element, a first transmission circuit for transmitting the gate signal to the gate drive circuit, and feedback indicating the on / off state of the semiconductor element from the gate drive circuit. In a power converter having a second transmission circuit for transmitting a signal, the gate signal of the first and second semiconductor elements transmitted to the first transmission circuit and the gate signal transmitted to the second transmission circuit Two failure determination circuits that determine the abnormality by taking a logic for each of the feedback signals of the first and second semiconductor elements; A power storage device for storing an output of the two failure determination circuits for detecting whether an abnormality has occurred on the gate signal side or the feedback side from the output. 2. A semiconductor device comprising: four first to fourth semiconductor elements connected in series to both terminals of a DC circuit having a neutral point output terminal, wherein the first and fourth terminals are connected to a neutral point output terminal of the DC circuit. Connecting the interconnection point of the second semiconductor element and the interconnection point of the third and fourth semiconductor elements via diodes,
And the first and third semiconductor elements and the second and fourth semiconductor elements.
A power converter for turning on and off the semiconductor elements according to a conjugate relationship with each other, a gate logic circuit for generating a gate signal for turning on and off the first to fourth semiconductor elements, and a gate drive for driving the semiconductor elements A power converter having a circuit, a first transmission circuit for transmitting the gate signal to a gate drive circuit, and a second transmission circuit for transmitting a feedback signal indicating an ON / OFF state of the semiconductor element from the gate drive circuit; The logic is applied to each of the gate signals of the first to fourth semiconductor elements transmitted to the first transmission circuit and the feedback signal of the first to fourth semiconductor elements transmitted to the second transmission circuit. Two failure determination circuits for determining an abnormality, and determining whether an abnormality has occurred based on the output of the two failure determination circuits on the gate signal side or the feedback. A storage device for storing the outputs of the two failure determination circuits for detecting which of the two is on the side of the power converter.