JP2757691B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter capable of outputting the contents of an abnormality to an output device such as a display device when an abnormality occurs.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional inverter device. In the figure, 1 is a commercial power supply, 2 is a forward conversion circuit for rectifying and converting AC supplied from the commercial power supply 1 to DC, 3 is a capacitor for smoothing the rectified output of the forward conversion circuit 2, and 4 is a DC modulated PWM. A reverse conversion circuit for converting into an alternating current of any frequency and voltage within a predetermined range, a microprocessor 5 for generating a signal for switching a semiconductor element of the reverse conversion circuit 4, and a amplifier 6 for amplifying a signal generated by the microprocessor 5. And an amplifier circuit for sending the signal to the inverse conversion circuit 4.

[0003] Reference numeral 7 denotes a motor as a load, 8 denotes a variable resistor for setting a speed, and 9-1 and 9-2 denote start switches for respectively specifying the rotation direction of the motor 7. Reference numeral 10 denotes a display for displaying the output frequency of the inverter device and the content of the abnormality, and 11 denotes a key for setting the frequency, the content of the display, and the like. Reference numeral 12 denotes an EEROM for storing an output frequency when an abnormality occurs, and reference numerals 13-1 and 13-2 denote current detectors for detecting an output current. It is assumed that the inverter unit 100 includes the forward conversion circuit 2, the capacitor 3, the inverse conversion circuit 4, the microprocessor 5, and the amplification circuit 6. The display unit 200 includes the display 10 and the keys 11.

Next, the operation will be described with reference to the flowchart of FIG. FIG. 5 shows an operation flow executed by the microprocessor 5 every predetermined time. When the inverter starts operating, the process proceeds from the start step S0 to step S1 in the figure at predetermined time intervals. In step S1, it is determined whether or not the value of the output current detected by the current detectors 13-1 and 13-2 is equal to or greater than a predetermined value. If it is equal to or more than the predetermined value, it is determined that an excessive output current is flowing, and the process proceeds to the next step 2. If the output current is not equal to or more than the predetermined value, the output current is determined to be normal and the process proceeds to end step S5.

[0005] In step S2, the output of the inverter section 100 is cut off, and the process proceeds to the next step S3. Step S3
In ERO, the output was cut off due to overcurrent.
Then, the process proceeds to the next step S4. In step S4, the frequency output at the time of occurrence of the abnormality is stored in the EEPROM 12, and the process proceeds to the next end step S5. After the occurrence of the abnormality, the contents of the abnormality and the output frequency at the time of occurrence of the abnormality can be displayed on the display 10 of the display unit 200 by operating the key 11 based on the stored contents of the EEPROM 12.

[0006]

Since the conventional inverter device is configured as described above, it is possible to display the contents of the abnormality and the output frequency at the time of the occurrence of the abnormality after the occurrence of the abnormality. The progress reached could not be displayed. Therefore, when investigating the cause of the abnormality,
After the connection of the general-purpose failure analysis device and the like, it was necessary to operate the inverter device until the abnormality occurred again to reproduce the process of the occurrence of the abnormality.

[0007] In addition, there is a problem that it may take time until the abnormality occurs again, and it takes time to investigate the cause of the abnormality. Further, in order to reproduce the abnormality, there is a problem that stress is again applied to the device, and in some cases, the semiconductor element or the like may be damaged. Also,
When a general-purpose failure analysis device is connected or the like, the inverter device has data that cannot be easily detected by the general-purpose failure analysis device, such as the internal status of the inverter unit 100, which hinders easy investigation of the cause of the abnormality. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When an abnormality occurs, it is possible to output the progress of the abnormality to an output device such as a display device. The purpose of the present invention is to obtain an inverter device which can be easily inspected for its cause.

[0009]

SUMMARY OF THE INVENTION An inverter device according to the present invention is an inverter unit for converting commercial alternating current into alternating current of a predetermined frequency and voltage subjected to PWM modulation, a storage unit having a predetermined storage capacity, and an inverter unit. Abnormality detecting means for detecting an abnormal operation of the inverter, and data indicating the operation state of the inverter section are written into the storage means at predetermined time intervals so that the contents written later in time are historically stored and held. And writing means for stopping the writing operation to the storage means based on the detection of the operation abnormality of the inverter unit by the abnormality detection means.

In addition, the apparatus has a connection portion which can electrically connect or disconnect an external output device, and can read out the read contents from the storage means to the external output device via the connection portion. It was done.

[0011]

In the inverter device according to the present invention,
Data indicating the operation state of the inverter unit is written into the storage means at predetermined time intervals by the writing means so that the contents written later in time are historically stored and held by the writing means. The writing operation to the storage unit is stopped based on the detection of the operation abnormality of the inverter unit.

[0012] Further, the apparatus has a connection portion capable of electrically connecting or disconnecting an external output device, and the read content read from the storage means is output to the external output device via the connection portion.

[0013]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 5, 7, 8, 9-1, 9-2, 10, 11, 13-1, 13-2, and the display unit 200 are the same as those in FIG. Description is omitted. Reference numeral 300 denotes an external output device, for example, a personal computer. The personal computer 300 includes a display screen unit 30 and a personal computer main body 31, and can display information based on an input signal on the display screen unit 30.

15 is a first microprocessor, 20 is a second microprocessor, 21 is storage means, for example,
Memory. Note that the first microprocessor 15
Is a microprocessor 5 shown in FIG.
The program stored in a built-in memory (not shown) is slightly different from that of the first embodiment in order to realize the functions of the present invention. The inverter unit 1
000 comprises a forward conversion circuit 2, a capacitor 3, an inverse conversion circuit 4, a first microprocessor 15, and an amplification circuit 6. In addition, the abnormality detecting means includes:
The current detectors 13-1 and 13-2 and the first microprocessor 15 are assumed.

A selector 22 switches between connecting the second microprocessor 20 and the memory 21 or connecting the memory 21 and the personal computer 300. The second microprocessor 20 is connected to the first microprocessor 15 via a bus.
The data indicating the operating state of the inverter unit 1000, which includes the internal status indicating the internal state of the inverter 1000, the output frequency, the output current, the output voltage, and the like, can be called from the first microprocessor 15 and transferred to the memory 21.

Reference numeral 23 denotes a switch for instructing the second microprocessor 20 whether or not to start the storage operation in the memory 21. Note that the second microprocessor 20,
It is assumed that the operation state data processing unit 400 is configured by the memory 21, the selector 22, and the switch 23. Further, the personal computer 300 is connected to a connection unit, for example, the operation state data processing unit 4 via a connector 301.
00 is connected.

FIG. 2 is an explanatory diagram showing the configuration of the memory 21 shown in FIG. As shown in FIG. 2, a column 201 for storing an error mark for each address of the memory 21, a column 202 for storing time, a column 203 for storing an output frequency of the inverter unit 1000, a column 204 for storing current, A storage section 205 and an internal status storage section 206 are provided.

Then, the time, the output frequency of the inverter unit 1000, the output current, the output voltage, and the internal status are written by the second microprocessor 20 at predetermined time intervals, and the abnormality of the abnormality detecting means is described. Upon detection, an error mark “E” is written in the column 201 and the above-described writing operation is stopped. The writing means is embodied by the function of the second microprocessor 20.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the flowchart shown in FIG. In step T1, it is determined whether or not the state of the switch 23 is in the OFF state.
If it stays at 1 and becomes OFF, it proceeds to step T2.
In step T2, it is determined whether or not the state of the switch 23 is ON. If the switch 23 is not ON, the process remains at step T2. If the switch 23 is ON, the process proceeds to step T3.
That is, in steps T1 and T2, when the switch 23 changes from the OFF state to the ON state, the process proceeds to step T3.

In step T3, the current time is stored in the memory 21.
Then, the process proceeds to writing step T4. In step T4, the frequency is written in the memory 21, and the process proceeds to step T5. In step T5, the output current is written into the memory 21 and in step T6
Proceed to. In step T6, the output voltage is written in the memory 21, and the process proceeds to step T7. In step T7, the status is written in the memory 21, and the process proceeds to step T8.

In step T8, if the abnormality detecting means has not detected an abnormality, the flow proceeds to step T9, and if it has detected an abnormality, the flow proceeds to step T10. In step T9, an address pointer (not shown) of the memory 21
And returns to step T3, and again from step T3 to
Step T8 is repeatedly executed. In step 10,
The error mark “E” is written into the memory 21 and remains at step T10.

[0022] address a ₀ ~ by the operation shown in FIG. 3
The memory 21 having the address a _n-1 stores n pieces of latest information. That is, the address pointer of the memory 21 returns to a _{0 when} it reaches a _n−1 , and repeats the storage operation. Next, during the above-described storage operation, when the abnormality detecting means detects an abnormality, the process proceeds from step T8 to step T10, where the error mark “E” is written to the memory 21 and the operation of writing data to the memory 21 is performed. Stopped.

As described above, the memory 21 after the abnormality is detected stores n latest data items until the abnormality is detected. The contents stored in the memory 21 are transferred to the personal computer 300 of FIG.
, It is possible to know the progress of the inverter unit 1000 up to the abnormality in detail after the occurrence of the abnormality.

Since the inverter unit 1000 does not turn off the power even when an abnormality occurs, or does not turn off the power of a control circuit such as the first microprocessor 15 even when the power is turned off. There is no need to provide a separate backup power supply for the memory 21. Also,
The operating state data processing unit 400 including the memory 21 and the second microprocessor 20 can be configured at relatively low cost. In other words, the inverter device shown in FIG. 1 can be configured to be much smaller and inexpensive than the case where the inverter device shown in FIG.

Embodiment 2 FIG. In the first embodiment, the contents read out from the storage unit are output to a display device connected to the outside via the connector 301. However, the present invention is not limited to this, and the display device may be provided inside the inverter device. Good. Further, the output may be made to an output device such as a printer instead of the display device. In the first embodiment,
Although the two microprocessors of the first and second microprocessors are used, the present invention is not limited to this.
Can have the function of the second microprocessor. Further, the memory 21 may use a memory built in the first microprocessor 15. Further, in the first embodiment, the abnormality detecting means is provided by the first microprocessor 15 and the current converters 13-1 and 13-1.
, But not limited thereto, the second microprocessor 20 and the current converters 13-1 and 13-1.
-2, and the outputs of the current converters 13-1 and 13-2 may be connected to the second microprocessor 20. In this case, the abnormal progress when the first microprocessor 15 operates abnormally can be stored in the memory 21.

[0026]

As described above, according to the present invention, the data indicating the operation state of the inverter section is stored at a predetermined time interval so that the contents written later in time are stored and retained in history. In addition, since the above-described writing operation is stopped based on the detection of the operation abnormality of the inverter unit by the abnormality detection unit, the abnormality occurs based on the stored contents of the storage unit after the abnormality occurs. The progress can be output to an output device such as a display device, which has the effect of facilitating the investigation of the cause of the abnormality.

[0027] Also, since there is provided a connecting portion capable of electrically connecting or disconnecting an external output device, the read contents read from the storage means can be output to the external output device via this connecting portion. In addition, there is an effect that the inverter device that can easily investigate the cause of the abnormality can be configured at a low cost and in a small size.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a memory that stores data indicating an operation state of an inverter unit of the inverter device according to one embodiment of the present invention;

FIG. 3 is a flowchart showing an operation of the second microprocessor shown in FIG. 1;

FIG. 4 is a block diagram showing a conventional inverter device.

FIG. 5 is a flowchart showing an operation of the conventional inverter device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Commercial power supply 2 Forward conversion circuit 3 Capacitor 4 Inversion circuit 5 Microprocessor 6 Amplification circuit 7 Motor 8 Variable resistor 9-1 Start switch 9-2 Start switch 10 Display 11 Key 12 EEPROM 13-1 Current detector 13- 2 Current Detector 15 First Microprocessor 20 Second Microprocessor 21 Memory 22 Selector 23 Switch 30 Display Screen 31 Personal Computer 100 Inverter 200 Display 300 Personal Computer 301 Connector 400 Operating State Data Processor 1000 Inverter

Claims (2)

(57) [Claims] An inverter for converting a commercial alternating current into a predetermined frequency and voltage alternating current subjected to PWM modulation; a storage unit having a predetermined storage capacity; an abnormality detecting unit for detecting an operation abnormality of the inverter unit; Data indicating the operation state of the inverter unit is written into the storage unit at predetermined time intervals so that the contents written later in time are stored and retained in history, and the inverter is detected by the abnormality detection unit. A writing unit for stopping a writing operation to the storage unit based on detection of an operation abnormality of the unit. 2. An apparatus according to claim 1, further comprising: a connection portion capable of electrically connecting or disconnecting an external output device, wherein the read content read from the storage means can be output to the external output device via the connection portion. The inverter device according to claim 1, wherein: