JPH0656952B2 - counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention is such that a count command generates a count output after a predetermined time, and a count output does not occur at the time of a circuit failure, or a count delay occurs. For fail-safe counters. Such a counter is used, for example, in a railroad crossing warning device as a timer for stopping ringing after a predetermined time.

<Prior Art and its Problems> As a conventional counter of this type, Japanese Patent Laid-Open No. 57-417 has been used.
The one disclosed in No. 02 publication is known. However, this prior art has a steering circuit and requires a three-valued input, which tends to complicate the circuit configuration.

<Object of the Invention> It is an object of the present invention to provide a counter capable of having an asymmetric error characteristic with respect to an output voltage and a counting time without requiring a steering circuit and a three-valued input.

<Structure of the Invention> In order to achieve the above object, a counter according to the present invention has a plurality of self-holding circuits and a delay circuit, and the self-holding circuit of the next stage is subject to the output generation of the self-holding circuit of the previous stage. The self-holding circuit has a logical product operation oscillator, a rectifier circuit, another delay circuit, and a feedback circuit, and the logical product operation oscillator is at least It has two input terminals, one of the input terminals is provided with a counting pulse signal whose pulse width is not extended due to a failure, and the other of the input terminals is provided with a counting command signal. When the counting command signal is at a potential outside the power supply frame, an oscillating operation is performed to generate a logical product output of the counting pulse signal and the counting command signal, and a circuit in which an output does not occur due to a circuit failure, the rectifier circuit is Logical product Rectified and output the AND output provided in the subsequent stage of the arithmetic oscillator, a circuit that does not generate a rectified output due to a circuit failure, the other delay circuit is provided in the subsequent stage of the rectifier circuit,
A circuit in which a delayed output is generated with a predetermined time delay with respect to the time when the rectified output is given from the rectifier circuit, and the delayed output is not output early at the time of a failure, and the feedback circuit is the other circuit. A circuit for feeding back a signal obtained through a delay circuit to one of the input terminals of the logical product operation oscillator to cause the logical product operation oscillator to perform a self-holding operation, wherein the delay circuit is a stage between the self-holding circuits. Connected to the
A circuit that is delayed by a predetermined time from the time of input and has a delay time such that a delayed output is produced after the counting pulse signal disappears, and the delayed output is not output early in time at the time of failure. In the self-holding circuit, the logical product operation oscillator constituting the first-stage self-holding circuit, the counting instruction signal is given from the outside, the logical product operation oscillator constituting another self-holding circuit, The counting command signal is supplied to the other of the input terminals from the self-holding circuit of the preceding stage through the delay circuit.

<Operation> In the first-stage self-holding circuit, with the count command signal externally applied to the other input terminal of the AND operation oscillator, the first count operation is applied to one of the input terminals of the AND operation oscillator. When a pulse signal is input, the AND operation oscillator
When the input logic is established, an oscillation operation is performed and a logical product output is generated. The logical product output is rectified by the rectifier circuit. The rectified output is given to another delay circuit included in the self-holding circuit. The other delay circuit included in the self-holding circuit produces a delayed output with a predetermined time delay with reference to the time when the rectified output is given from the rectifying circuit. The delayed output signal of the other delay circuit included in the self-holding circuit is fed back to one of the input terminals of the logical product operation oscillator via the feedback circuit. As a result, the AND operation oscillator is self-holding, and even after the count pulse signal input to one of the input terminals disappears, the AND operation oscillator continues to oscillate and the AND output is supplied to the rectifier circuit. Then, the rectified output is output from the rectifier circuit.
Then, from the delay circuit connected between the stages of the self-holding circuit, the delayed output serving as the count command signal is continuously supplied to the other input terminal of the AND operation oscillator constituting the self-holding circuit of the next stage. .

The delay circuit connected after the first-stage self-holding circuit has a delay time such that the output is output after the count pulse signal is not input to the other input end Even if a delayed output serving as a count command signal is given to the other input terminal of the logical product operation oscillator constituting the circuit, the logical product operation oscillator does not start the oscillation operation.

In the self-holding circuit of the next stage, at the timing when the counting pulse signal is input to one of the input ends, between the delay output signal given as the count command signal from the self-holding circuit of the previous stage to the other of the input ends, The input logic of the logical product operation oscillator is established, the logical product operation oscillator starts oscillating operation, and a logical product output is generated. Then, this logical product output is rectified by the rectifier circuit, performs self-holding operation through another delay circuit included in the self-holding circuit, and counts to the self-holding circuit of the next stage through the delay circuit connected between the stages. A delayed output signal as a command signal is supplied.

This operation is repeated by the number of stages of the self-holding circuit each time the counting pulse signal is generated, and finally the n-th counting pulse signal corresponding to the number n corresponding to the number of stages of the self-holding circuit is counted and output. You get a counter. As a result, a counter having a simple circuit configuration that does not require a steering circuit or three-valued input can be obtained.

Since the AND operation oscillator is a circuit that does not generate output due to a circuit failure, it does not oscillate when a circuit failure occurs,
No output is generated. Therefore, since the count command signal cannot be supplied to the self-holding circuit of the next stage, the output of the last stage is not output,
Or the output of the final stage is delayed in time, so it is a fail safe.

Since the rectifier circuit is a circuit that does not generate a rectified output due to a circuit failure, the count command signal cannot be supplied to the self-holding circuit in the next stage. Therefore, when a circuit failure occurs in the rectifier circuit, the output of the final stage is not output or the output of the final stage is delayed in time, which is fail safe.

The delay circuit connected between the stages of the self-holding circuit and the other delay circuits included in the self-holding circuit are circuits in which the delay output is not output earlier in time at the time of failure, so a circuit failure occurs. In this case, there is no output, and the failure mode in which the delay time becomes long is set, and thus fail safe.

For this reason, with a simple circuit configuration that does not require a steering circuit or ternary input, in the event of a failure, the self-holding circuit has an asymmetric error output characteristic on the amplitude axis, and the delay circuit and the input pulse are asymmetric on the time axis. It has an error output characteristic,
An asymmetric error characteristic can be provided for the output voltage and the counting time.

With respect to the pulse input to each self-holding circuit, the fail-safe property is maintained because the counting pulse signal whose pulse width is not extended due to the failure is given.

<Example> FIG. 1 is an electrical circuit connection diagram of a counter according to the present invention. The portion shown by the envelope F in FIG. 1 shows the counter of the present invention. In this embodiment, the one operating with a positive power supply is shown, but a circuit configuration operating with a negative power supply may be used.

OSC _{1 to} OSC ₃ are AND logical operation oscillators, RC _{1 to} RC
₃ is a rectifier circuit connected to the respective outputs of the logical product computing oscillator _OSC 1 _{~OSC 3.}

The logical product operation oscillators OSC _{1 to} OSC ₃ have at least 2
Input terminals A _{1 to} A ₃ and B _{1 to} B ₃
A count pulse signal is given to _{1 to} A ₃ , and input terminals B _{1 to} B 3
₃ is given a count command signal, and when the count pulse signal and the count command signal are at the potential outside the power supply frame, an oscillating operation is performed to produce a logical product output of the count pulse signal and the count command signal, and an output is generated due to a circuit failure. It is a circuit that does not. The counting pulse signal is given as a signal whose pulse width is not extended due to a failure.

RC ₁ to RC ₃ logical product computing oscillator _OSC 1 _{~OSC 3}
Is a rectifier circuit connected to each of the outputs, and forms a circuit that does not generate a rectified output due to a circuit failure by rectifying and outputting the logical product output.

DE ₁₁ and DE ₂₁ are delay circuits connected to the respective subsequent stages of the rectifier circuits RC ₁ and RC ₂ . Each of the delay circuits DE ₁₁ and DE ₂₁ produces a delayed output with a predetermined time delay with reference to the time when the rectified output is given from the rectifying circuits RC ₁ and RC ₂ . Each of the delay circuits DE ₁₁ and DE ₂₁ is configured as a circuit in which a delayed output is not output earlier in time when a failure occurs.

f ₁ and f ₂ are feedback circuits. Feedback circuits f ₁ and f ₂
Of each of the outputs of the delay circuits DE ₁₁ and DE ₂₁ , the input terminals A of the AND operation oscillators OSC ₁ and OSC _2.
1 and A ₂ are respectively fed back to the delay circuit DE ₁₁
And delay time of DE ₂₁
When the pulse width input to the input terminals A ₁ and A ₂ of C ₁ and OSC ₂ is large, the AND operation oscillators OSC ₁ and OSC ₂
Each self-holds. That is, the input terminals B ₁ , B ₂ ,
As long as the count command signal is input to each of B ₃ ,
Even if the counting pulse signals input to the input terminals A ₁ , A ₂ , and A ₃ disappear, the AND operation oscillators OSC ₁ and OS
C ₂ and OSC ₃ continue to oscillate.

Even if the delay circuits DE ₁₁ and DE ₂₁ are not provided, the self-holding operation is performed if the feedback circuits f ₁ and f ₂ are provided, but in this case, the AND operation oscillators OSC ₁ and OSC ₂ are erroneously self-holding due to noise. There is a risk of operation. Delay circuit DE
_{With 11} and DE ₂₁ , it is possible to prevent malfunction of self-holding due to noise. The delay circuits DE ₁₁ and DE ₂₁ can be provided in the loop of the feedback circuits f ₁ and f ₂ .

The delay circuits DE ₁₂ and DE ₂₂ are connected between the stages of the self-holding circuit, and output the output of each self-holding circuit after a certain delay time to the input terminals of the AND operation oscillators OSC ₂ and OSC ₃ of the next stage. Input into B ₂ and B ₃ , respectively. Delay circuit DE
₁₂ and DE ₂₂ are AND operation oscillators OSC ₂ and OSC
₃ is inserted into each of the input terminals A ₂ and A ₃ of the circuit ₃ so that the counter does not run away by the count pulse signals input in parallel, and its delay time is longer than the delay time of the delay circuits DE ₁₁ and DE _12. Selected as a value. Delay circuit D
E ₁₂ and DE ₂₂ also have a delay time such that an output is produced after the count pulse signal input to the input terminal A ₁ or A ₂ is lost.

Of the self-holding circuit, the AND operation oscillator OSC ₁ that constitutes the first-stage self-holding circuit is externally supplied with a count command signal for the input terminal B ₁ . In the AND operation oscillators OSC ₂ and OSC ₃ forming another self-holding circuit, the count command signal is input from the self-holding circuit of the previous stage through the delay circuits DE ₁₂ and DE ₂₂ . The delay circuits DE ₁₂ and DE ₂₂ are
The output of each self-holding circuit is provided with a certain delay time, and the input terminal B of the AND operation oscillators OSC ₂ and OSC _{3 at} the next stage is set.
₂ and B ₃ , respectively. The delay circuits DE ₁₁ , DE ₁₂ , DE _21, and DE ₂₂ , which serve as the count command signal for the next stage, are configured as circuits that do not accelerate the time for producing a delayed output when a failure occurs. Such a delay circuit can be constructed by using the technique disclosed in Japanese Patent Application Laid-Open No. 57-157623 of the applicant of the present application. However, when a delay of too long time is not required, four terminals are used. It can also be configured using a capacitor.

Next, the operation will be described with reference to the time chart of FIG. High levels of FIG. 2 (a) to l) (hereinafter referred to as H level) is a potential that potential or oscillation can oscillate logical product computing oscillator OSC ₁ ~OSC _3, referred to as low level (hereinafter L level ) Is an AND operation oscillator OSC _{1 to} OS
C ₃ indicates a potential which is not potential or oscillation can not oscillate.

First, as shown in FIG. 2 (a), the power is turned on at t ₀ , and the count command signal Vb is applied to the input terminal B ₁ of the logical product operation oscillator OSC ₁ . The count command signal Vb is an H-level potential that can be oscillated by the logical product operation oscillator OSC ₁ .

Next, as shown in FIG. 2 (b), at time t _{1, the} pulse width T ₃
The first counting pulse signal P ₁ of
It is given in parallel to the respective input terminals A _{1 to} A ₃ of SC _{1 to} OSC ₃ . Here, the AND operation oscillators OSC ₂ and OSC ₃
Since the input terminals B ₂ and B ₃ of the above do not operate, these do not operate, but since the counting instruction signal Vb is input to the input terminal B ₁ of the AND logical operation oscillator OSC ₁ , this does not work. counting the pulse signal _{P 1} of the H level applied to a ₁
Causes the AND operation oscillator OSC ₁ to start oscillating,
A logical product output is generated as shown in FIG. 2 (c). This logical product output is rectified by the rectifier circuit RC ₁ connected to the logical product operation oscillator OSC ₁ to generate an H level rectified output as shown in FIG. 2 (d). Then, after the rectified output, the delay circuit DE _{11 is} delayed by a delay time T _1.
Then, the output shown in Fig. 2 (e) is generated. A part of the output of the delay circuit DE ₁₁ is input to the input terminal A ₁ of the logical product operation oscillator OSC ₁ through the feedback circuit f ₁ . Here, the delay time T ₁ is the pulse width T of the counting pulse signal P _1.
Since the relation of _T 3> _{T 1} with respect to _3, the logical product computing oscillator OSC ₁ is self-holding.

The output of the delay circuit DE ₁₁ is input to the input terminal B ₂ of the logical product operation oscillator OSC ₂ which constitutes the self-holding circuit of the next stage through the delay circuit DE ₁₂ . This signal serves as a count command signal for the logical product operation oscillator OSC ₂ which constitutes the self-holding circuit of the next stage. Delay circuit DE _12, as shown in FIG. 2 (f), since having a delay time T2 as output exits gone counting pulse signals input to the input terminal A _2, the logical product from the delay circuit DE ₁₂ It is given the delayed output to the arithmetic oscillator OSC ₂ is, the logical product computing oscillator OSC ₂ output is not generated.

Next, when the second count pulse signal P ₂ is generated at t ₂ , the output from the delay circuit DE ₁₂ continues to serve as the count command signal due to the self-holding operation of the logical product operation oscillator OSC _1. since the input to the B _2, logical product computing oscillator OSC ₂ starts oscillation operation, produces a logical product output as shown in FIG. 2 (g). This logical product output is rectified by the rectifier circuit RC ₂ , and an H level rectified output is generated as shown in FIG. 2 (h). That is, the logical product operation oscillator OSC ₂ counts the occurrence of the second pulse. The logical product operation oscillator OSC ₂ self-holds the count pulse signal P ₂ by the feedback signal input to the input terminal A ₂ through the delay circuit DE ₂₁ and the feedback circuit f ₂ .

The above operation is repeated by the number n of stages of the self-holding circuit, and the AND operation oscillator OSC _n at the final stage obtains a counter for counting the nth pulse. Since the number of stages is three in this embodiment, after the delayed outputs of FIGS. 2 (i) and 2 (j) are generated, the logical product operation oscillator OSC _{3 at} the final stage has the logic as shown in FIG. 2 (k). A product output is produced, and this logical product output is rectified by the rectifier circuit RC ₃ to obtain a rectified output as shown in FIG. This rectified output corresponds to counting the _third counting pulse signal P ₃ .

Next, fail-safety will be described.

First, since the logical product operation oscillators OSC _{1 to} OSC ₃ are circuits in which no output is generated due to a circuit failure, when the circuit failure occurs, the oscillation operation is not performed and no output is generated. Therefore, since the count command signal cannot be supplied to the self-holding circuit of the next stage, the output of the final stage is not output, or the output of the final stage occurs with a delay in time, which is fail safe.

The rectifier circuits RC _{1 to} RC ₃ are circuits that do not generate a rectified output due to a circuit failure, and therefore cannot output to the self-holding circuit of the next stage. Therefore, the output of the final stage is not output, or the output of the final stage occurs with a time delay, which is a fail safe.

Delay circuits DE ₁₁ , DE ₂₁ and delay circuits DE ₁₂ , DE
₂₂ is a circuit in which a delayed output is not output earlier in time at the time of failure, so if a circuit failure occurs, there is no output and the failure mode becomes longer because of the delay time.
It is a fail safe.

With respect to the pulse input to each self-holding circuit, the fail-safe property is maintained because the counting pulse signal whose pulse width is not extended due to the failure is given.

Next, when a circuit failure occurs in the delay circuits DE ₁₁ , DE ₁₂ , DE ₂₁ and DE ₂₂ , a failure mode in which there is no output and the delay time is long is provided, so fail safe.

AND logical operation oscillators OSC _{1 to} OSC ₃ and rectifier circuit RC
_{As for 1 to} RC ₃ , it is desirable to use those known in Japanese Utility Model Publication No. 57-4764 and Japanese Patent Publication No. 51-38211. One of the logical product operation oscillators known in the above-mentioned publicly known documents uses an RC miles vibrator,
A circuit that oscillates only when the potentials at both input terminals are higher than the power supply potential Vs of the logical product operation oscillator (referred to as a potential outside the power supply frame) to generate a logical product output and not output due to a circuit failure. Are configured.

In FIG. 1, the circuits on the left side of the counter of the present invention displayed by the envelope F are the logical product operation oscillators OSC ₁ and OS.
As C ₂ and OSC ₃ , an input circuit suitable when the one described in the above-mentioned publicly known document is used is shown. The logical product operation oscillators OSC _{1 to} OSC ₃ operate by being supplied with the power supply voltage Vs. The power supply voltage Vs is a voltage obtained by stepping down the input voltage Vb serving as the count command signal by the resistor R ₁ .
The voltage is lower than the count command signal Vb. The logical operation oscillators OSC ₁ , OSC ₂ and OSC ₃ have input terminals A _{1 to} A _{3 respectively.}
And the potentials of B _{1 to} B ₃ are oscillated only when the potential outside the power supply frame is higher than the power supply potential Vs to generate a logical product output.

1 is a pulse generator. The pulse generator 1 includes input terminals B ₁ to of the logical operation oscillators OSC ₁ , OSC ₂ and OSC _3.
3 is provided for supplying the count pulse signals P _{1 to} P ₄ to the input voltage Vb applied through the resistor R _1.
It operates by (count command signal). The pulse generator 1 is configured by a pulse generator whose pulse width is not extended at the time of failure, or a pulse generator which has a characteristic of not generating a pulse.

FIG. 3 shows a concrete example of such a pulse generator 1, which is a unijunction. It is a relaxation oscillator circuit that uses the Tronista UJT. R _{2 to} R ₄ are resistors,
C ₁ is a capacitor. The pulse generator shown in FIG. 3 stops oscillation when a circuit failure occurs, so that no output pulse is generated at the time of failure. That is, the pulse width is not extended at the time of failure. In FIG. 3, the circuit configuration uses the terminal voltage of the resistor R ₄ as a pulse output, but an amplifier may be provided at the subsequent stage.

Next, the AND operation oscillators OSC ₁ , OSC ₂ and OSC
The counting pulse signal input circuit of No. ₃ connects the capacitor C ₃ and the diode D ₃ in series, and clamps the diode D _{4 at} the connection point of the capacitor C ₃ and the diode D _3.
Are connected. The diode D ₄ is connected to the power supply potential Vs of the AND operation oscillators OSC ₁ , OSC ₂ and OSC ₃ . Therefore, if there is no counting pulse signals input from the oscillator 1, the clamping action of the diode D _4, the potential at the connection point between the capacitor C ₃ and the diodes D ₃ and D ₄ is clamped to the power supply potential Vs, the input terminal A _1, The potentials of A ₂ and A ₃ are also clamped to the power source potential Vs.

While the potentials of the input terminals A ₁ , A ₂ and A ₃ are clamped by the power source potential Vs, the AND operation oscillators OSC ₁ and OSC
₂ and OSC ₃ do not oscillate, but when the count pulse signal is amplified from the oscillator 1 and is output at a voltage higher than the power supply frame potential, this count pulse signal is transmitted via the capacitor C ₃ to the capacitor C ₃ and the diode D ₃ . Is added to the clamp potential (power supply potential Vs) at the connection point of the input points A ₁ and A ₂
And the potential of A ₃ is kept at the potential outside the power supply frame. For this reason,
Each of the logical product operation oscillators OSC ₁ , OSC _2, and OSC ₃ oscillates on condition that the count command signal input of the power-source-outside-potential is input to each of the input terminals B ₁ , B ₂ , and B ₃ .

Next, as the logical product operation oscillators OSC _{1 to} OSC ₃ and the rectifier circuits RC _{1 to} RC ₃ , those known in Japanese Utility Model Application Laid-Open No. 57-4764 and Japanese Patent Publication No. 51-38211 are used and shown in FIG. The fail-safety when the input circuit as shown in FIG. 1 is configured using the pulse generator 1 as shown will be described.

First, since the pulse width of the pulse generator 1 is not extended at the time of failure, for example, the outputs of the delay circuits DE ₁₂ and DE ₂₂ are overlapped with the counting pulse signal signal given before,
There is no possibility that the counting will go wrong. Therefore,
It is fail-safe because the time until the output of the final stage is not shortened.

Further, with respect to the pulse input circuit from the pulse generator 1 to each self-holding circuit, the fail-safe property is maintained as follows.

(B) Failure of the capacitor C _{3 At} the time of short circuit, the potentials at the input terminals A ₁ , A ₂ and A ₃ cannot be kept at the potential outside the power supply frame, so that the AND operation oscillators OSC _{1 to} OSC ₃ do not oscillate. In addition, since the pulse from the pulse generator 1 is not input at the time of open failure,
The logical product operation oscillators OSC _{1 to} OSC ₃ do not oscillate.

(B) Failure of diode D _{4 At} the time of short circuit, the pulse generator 1 is connected to the input terminals A ₁ , A ₂ and A _2.
No pulse input for ₃ . When it is opened, there is no route for discharging the accumulated charge of the capacitor C ₃ , so that a pulse cannot be input.

(C) Failure of diode D ₃ Self-holding operation is not performed at the time of short circuit. For example, if the diode D _{3 of} the logical product operation oscillator OSC ₁ is short-circuited, a discharge current flows from the diode D ₄ to the capacitor C ₃ when the input pulse disappears (becomes L level). The end A ₁ becomes the potential Vs, stops oscillation, and cannot hold itself. In addition, no pulse is input when opened.

In other words, in the case of any failure such as disconnection or short circuit, there is no output or the time when the final output is generated is delayed, so that it is fail safe.

<Effects of the Invention> As described above, according to the present invention, the following effects can be obtained.

(A) With a simple circuit configuration that does not require a steering circuit or three-value input, it is possible to provide a counter that counts and outputs the n-th counting pulse signal corresponding to the number n corresponding to the number of stages of the self-holding circuit.

(B) With a simple circuit configuration that does not require a steering circuit or ternary input, in the event of a failure, the self-holding circuit has an asymmetric error output characteristic on the amplitude axis, and the delay circuit and the input pulse are asymmetric on the time axis. It is possible to provide a fail-safe counter having an error output characteristic and an asymmetric error characteristic with respect to the output voltage and the counting time.

(C) With respect to the pulse input to each self-holding circuit, the fail-safe property is maintained because the counting pulse signal whose pulse width is not extended due to the failure is given.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electric circuit diagram of a counter according to the present invention, FIG. 2 is a time chart for explaining the operation of the counter according to the present invention, and FIG. 3 is a pulse that can be used in the present invention. It is an electric circuit diagram of a generator. 1 ... Pulse generator OSC _{1 to} OSC ₃ …… AND operation oscillator RC _{1 to} RC ₃ …… Rectifier circuit DE ₁₁ , DE ₁₂ , DE ₂₁ , DE ₂₂ …… Delay circuit

Claims (1)

[Claims] 1. A counter having a plurality of self-holding circuits and a delay circuit, wherein the counter output of the next-stage self-holding circuit is generated on condition that the output of the preceding self-holding circuit is generated. The circuit has an AND operation oscillator, a rectifier circuit, another delay circuit, and a feedback circuit, and the AND operation oscillator has at least two input terminals, and one of the input terminals has a failure. , A counting pulse signal whose pulse width is not extended is given, a counting command signal is given to the other of the input terminals, and the oscillation operation is performed when the counting pulse signal and the counting command signal are at the potential outside the power supply frame. Then, a logical product output of the counting pulse signal and the counting command signal is generated, and an output does not occur due to a circuit failure, the rectifier circuit is provided in a subsequent stage of the logical product operation oscillator, and outputs the logical product output. Rectified Output, a circuit which does not cause a rectified output at circuit failure, the other delay circuit is provided in a subsequent stage of the rectifier circuit,
A delay output is generated with a predetermined time delay with respect to the time when the rectified output is given from the rectifier circuit, and the delayed output is a circuit that is not output in time early in the event of a failure, and the feedback circuit is A circuit for feeding back a signal obtained through the other delay circuit to one of the input terminals of the logical product operation oscillator to cause the logical product operation oscillator to perform a self-holding operation, wherein the delay circuit is the self-holding circuit. Connected between the stages of
A circuit that is delayed by a predetermined time from the time of input and has a delay time such that a delayed output is produced after the counting pulse signal disappears, and the delayed output is not output early in time at the time of failure. In the self-holding circuit, the logical product operation oscillator constituting the first-stage self-holding circuit, the counting instruction signal is given from the outside, the logical product operation oscillator constituting another self-holding circuit, The counter, wherein the counting command signal is supplied to the other of the input terminals from the self-holding circuit of the preceding stage through the delay circuit.