JPH0584883B2 - - Google Patents

Info

Publication number
JPH0584883B2
JPH0584883B2 JP61222597A JP22259786A JPH0584883B2 JP H0584883 B2 JPH0584883 B2 JP H0584883B2 JP 61222597 A JP61222597 A JP 61222597A JP 22259786 A JP22259786 A JP 22259786A JP H0584883 B2 JPH0584883 B2 JP H0584883B2
Authority
JP
Japan
Prior art keywords
gate
liquid crystal
electrode
gate pulse
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61222597A
Other languages
Japanese (ja)
Other versions
JPS6377031A (en
Inventor
Yutaka Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP61222597A priority Critical patent/JPS6377031A/en
Publication of JPS6377031A publication Critical patent/JPS6377031A/en
Publication of JPH0584883B2 publication Critical patent/JPH0584883B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は、アクテイブマトリクス型の液晶表示
装置の駆動方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for driving an active matrix type liquid crystal display device.

(ロ) 従来の技術 アクテイブマトリクス型の液晶表示装置は三洋
電機技報Vol16,No.2,1984に示されており、そ
の構成は第3図に示す如く複数本のゲート電極2
ラインとそれらと直交する複数本のドレイン電極
1ライン及びそれらの交点に1個のアモルフアス
シリコン(a−Si)のTFTを形成して画素電極
を結合した基板に対向電極が相対しその間に液晶
を挟持するものである。
(b) Prior art An active matrix type liquid crystal display device is disclosed in Sanyo Electric Technical Report Vol. 16, No. 2, 1984, and its configuration is as shown in FIG.
An amorphous silicon (a-Si) TFT is formed on one line and a plurality of drain electrodes perpendicular to the lines and one amorphous silicon (a-Si) TFT is formed at the intersection of the lines and a pixel electrode is bonded to the substrate.A counter electrode faces the substrate, and a liquid crystal It is meant to hold the

斯様なTFTは、第4図の平面パターン図及び
第5図の断面図に示す如く、基板4上にゲート電
極2、絶縁膜9、a−Si膜8、ドレイン電極1並
びにソース電極7、画素電極3を順次形成したも
のである。
Such a TFT has a gate electrode 2, an insulating film 9, an a-Si film 8, a drain electrode 1, a source electrode 7, The pixel electrodes 3 are sequentially formed.

しかし、このような構造においては、TFTの
a−Si膜8の移動度が小さいためチヤンネル幅W
を大きくし、ON電流を増やし画素電極と対向電
極の作る容量に十分充電されるような手法が取ら
れている。
However, in such a structure, the channel width W is small because the mobility of the a-Si film 8 of the TFT is small.
A method is used to increase the ON current and sufficiently charge the capacitance created by the pixel electrode and counter electrode.

(ハ) 発明が解決しようとする問題点 しかしながら、上述の如き構造では、ゲート電
極2とソース電極7の重なり面積が大きくなり、
第5図の10に示すTFTの寄生容量が大きくな
る。そのため、対向電極6と画素電極3の作る容
量に充電された電圧がゲートパルスの立ち下がり
時に降下し、それにより、液晶に加わる直流成分
が大きくなり、液晶の劣化及びコントラストに悪
影響を与える。
(c) Problems to be solved by the invention However, in the structure described above, the overlapping area of the gate electrode 2 and the source electrode 7 becomes large.
The parasitic capacitance of the TFT shown at 10 in FIG. 5 increases. Therefore, the voltage charged in the capacitance formed by the counter electrode 6 and the pixel electrode 3 drops at the fall of the gate pulse, thereby increasing the DC component applied to the liquid crystal, which adversely affects the deterioration of the liquid crystal and the contrast.

また、ゲート電極2とソース電極7の重なり部
の面積がフオトリソグラフイでのパターンずれ、
サイドエツチングの不均一などによつてばらつ
き、寄生容量が大きいため、液晶にかかる電圧の
降下分の差が大きくなり、それが中間調表示をす
る場合ムラとなり階調が大きくできないという問
題点があつた。
In addition, the area of the overlapping portion of the gate electrode 2 and the source electrode 7 may be due to pattern deviation in photolithography.
Due to variations due to non-uniform side etching and large parasitic capacitance, the difference in voltage drop applied to the liquid crystal becomes large, which causes unevenness when displaying halftones, making it impossible to increase the gradation. Ta.

(ニ) 問題を解決する手段 本発明の液晶表示装置の駆動方法は、ゲートパ
ルスの立ち上がりのタイミングを1あるいは数ゲ
ートパルス時間だけ早くし、パルスの立ち下がり
タイミングはそのままでパルス幅を拡大したもの
である。
(d) Means for solving the problem In the method for driving a liquid crystal display device of the present invention, the rising timing of the gate pulse is advanced by one or several gate pulse times, and the pulse width is expanded while the falling timing of the pulse remains unchanged. It is.

(ホ) 作用 本発明によれば、ゲートラインに印加されるゲ
ートパルスのタイミングの当該の画素電極への書
き込みタイミングより前で、画素電極と対向電極
の作る容量、即ち液晶に充電されはじめ、当該の
ゲートパルスのタイミングでさらに充電されるた
め、TFTのチヤンネル幅が短かくできゲート電
極とソース電極の重なり面積が小さくなる。その
ことにより液晶の劣化が少なく、コントラストも
向上し、高階調が可能となる。
(E) Effect According to the present invention, the capacitance created by the pixel electrode and the counter electrode, that is, the liquid crystal, starts to be charged before the timing of the gate pulse applied to the gate line is written to the corresponding pixel electrode, and the corresponding pixel electrode begins to be charged. Since the TFT is further charged at the timing of the gate pulse, the channel width of the TFT can be shortened, and the overlapping area of the gate electrode and source electrode can be reduced. This reduces deterioration of the liquid crystal, improves contrast, and enables high gradation.

(ヘ) 実施例 第1図は本考案の駆動方法に用いる駆動信号の
ゲートパルスをタイミング別に表わしたものであ
る。尚、第2図は対比の為に示した従来のゲート
パルスである。
(F) Embodiment FIG. 1 shows the gate pulses of the drive signal used in the drive method of the present invention by timing. Incidentally, FIG. 2 shows a conventional gate pulse for comparison.

而して、液晶の劣化を考えると交流駆動をさせ
る必要があり、したがつて液晶TVを駆動させる
ためには、1フイールドごとにドレイン信号を反
転させて駆動させている。また、1/60秒ぐらいで
1フイールドを作つているため第2図の如き従来
のゲートパルスでは250本のゲート本数とすると
ゲートパルス幅は(1/60)/250=66.7μSとなる。
その66.7μSのパルス幅の間に、ドレイン電圧を±
4V(1フイールド16.7mSで反転させている)と
すると交流駆動のため画素電極3対向電極6間に
8Vの充電を行う必要がある。もしあるチヤンネ
ル幅で80%の充電率がある場合には、従来の場合
8×0.8=6.4Vとなり、1.6Vも未充電になつてし
まう。
Considering the deterioration of the liquid crystal, it is necessary to use AC drive. Therefore, in order to drive a liquid crystal TV, the drain signal is inverted for each field. Also, since one field is created in about 1/60 seconds, in the conventional gate pulse as shown in Fig. 2, if the number of gates is 250, the gate pulse width will be (1/60)/250 = 66.7 μS.
During that 66.7μS pulse width, the drain voltage is ±
When the voltage is 4V (inverted at 16.7mS per field), there is a voltage between the pixel electrode 3 and the opposing electrode 6 due to AC drive.
Requires 8V charging. If there is a charging rate of 80% with a certain channel width, in the conventional case, the voltage would be 8 x 0.8 = 6.4V, and 1.6V would be uncharged.

これに対して本発明方法ではもしj+1番目の
ゲートのパルスがONするとj番目の書き込み時
間WjでTFTがONし、1つ前のタイミングの映
像信号でj+1番目のゲートにつながるTFTを
介して画素電極3に充電が行われ、80%の充電率
で充電される。そしてこのTFTのゲートがONし
たままで次のタイミングWj+1に移り本来その
ラインに入力される信号が印加されるが、この時
本来の信号は当然、1つ前の映像信号と同符号の
ため本来の信号と1つ前のものとの電位差はたか
が2Vぐらいのものであり、結果的にゲートのON
している間に本来の信号に対して80%充電率から
考えて、2×0.8=1.6Vとなり0.4Vほどの電位差
しかないところまで充電される。
On the other hand, in the method of the present invention, if the pulse of the j+1th gate is turned on, the TFT is turned on at the jth writing time Wj, and the pixel is Electrode 3 is charged to a charging rate of 80%. Then, while the gate of this TFT remains ON, the next timing Wj+1 is reached and the signal that was originally input to that line is applied, but at this time, the original signal is of course the same sign as the previous video signal, so it was originally The potential difference between this signal and the previous one is only about 2V, and as a result, the gate is turned on.
During this time, considering the 80% charge rate for the original signal, it will be charged to a point where there is only a potential difference of 0.4V, which is 2 x 0.8 = 1.6V.

そこで、従来の方法で同じぐらいの充電電圧を
得ようとすると、チヤンネル幅を長くする必要が
でてくるが、本発明ではチヤンネル幅の延長は不
要である。それによつて本発明ではゲート・ソー
ス間の重なり面積が小さくなり、ゲート・ソース
間の寄生容量を小さくできる。それによつて、液
晶にかかる電圧が対極に対して非対称となるのを
防止でき、コントラストの低下、中間調表示の表
示ムラ、劣化の抑制ができる。
Therefore, in order to obtain the same charging voltage using the conventional method, it is necessary to lengthen the channel width, but in the present invention, there is no need to lengthen the channel width. As a result, in the present invention, the overlapping area between the gate and the source can be reduced, and the parasitic capacitance between the gate and the source can be reduced. Thereby, it is possible to prevent the voltage applied to the liquid crystal from becoming asymmetrical with respect to the opposite electrode, and it is possible to suppress a decrease in contrast, display unevenness in halftone display, and deterioration.

以上述べた例は1タイミング前ゲートをONさ
せる事を示したが数タイミング前からゲートを
ONせしめその分ゲートのパルス幅を拡げること
についても同様である。
The above example shows that the gate is turned on one timing before, but the gate is turned on several timings ago.
The same goes for increasing the pulse width of the gate by turning it ON.

(ト) 発明の効果 本発明は、ゲートパルスの立ち下がりタイミン
グを変えずに立ち上がりタイミングのみ/あるい
は数タイミング前によつてパルス幅を拡げた駆動
信号で駆動させることにより1つ前の映像信号か
ら表示電極と対向電極の間の容量に充電させるこ
とができるため、従来よりも充電能力が向上しそ
のためa−SiTFTのチヤンネル幅を短くできる。
このチヤンネル幅を短くできることによりTFT
のゲート電極とソース電極の重なり面積が小さく
なり、寄生容量が減少し液晶の劣化の防止、コン
トラストの向上、高階調が実現できる。
(G) Effects of the Invention The present invention enables driving with a drive signal whose pulse width is expanded by only the rising timing of the gate pulse without changing the falling timing of the gate pulse, or by several timings earlier, so that the signal can be changed from the previous video signal. Since the capacitance between the display electrode and the counter electrode can be charged, the charging capacity is improved compared to the conventional method, and therefore the channel width of the a-SiTFT can be shortened.
By shortening this channel width, TFT
The overlapping area of the gate electrode and source electrode is reduced, reducing parasitic capacitance, preventing liquid crystal deterioration, improving contrast, and achieving high gradation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の液晶表示装置の駆動方法に係
るゲート信号のタイミング図、第2図は従来方法
に係るゲート信号のタイミング図、第3図、第4
図、及び第5図は夫々液晶表示装置の一部切欠斜
視図、要部平面パターン図、及び断面図である。 1……ドレイン電極、2……ゲート電極、3…
…画素電極、6……対向電極、7……ソース電
極、8……a−Si膜。
FIG. 1 is a timing diagram of a gate signal according to the method of driving a liquid crystal display device of the present invention, FIG. 2 is a timing diagram of a gate signal according to a conventional method, and FIGS.
1 and 5 are a partially cutaway perspective view, a plane pattern diagram of a main part, and a cross-sectional view of a liquid crystal display device, respectively. 1...Drain electrode, 2...Gate electrode, 3...
...Pixel electrode, 6...Counter electrode, 7...Source electrode, 8...A-Si film.

Claims (1)

【特許請求の範囲】[Claims] 1 複数本のゲートラインと複数本のドレインラ
インとが交差し、その各交差点に薄膜トランジス
タを設け、該各薄膜トランジスタのソースに夫々
画素電極を形成してなる第1の基板と、全面に共
通電極を形成してなる第2の基板との間に液晶物
質を挟持した構造のアクテイブマトリクス型液晶
表示装置の駆動方法に於いて、ゲートラインに印
加するゲートパルス幅を1ライン分の書き込み時
間より長くすると共に、ゲートパルスの立上がり
タイミングを画素電極への書き込み開始タイミン
グより少なくとも1つ前のゲートパルスの立上が
り時に設定したことを特徴とする液晶表示装置の
駆動方法。
1. A first substrate in which a plurality of gate lines and a plurality of drain lines intersect, a thin film transistor is provided at each intersection, and a pixel electrode is formed at the source of each thin film transistor, and a common electrode is provided on the entire surface. In a method for driving an active matrix type liquid crystal display device having a structure in which a liquid crystal material is sandwiched between a second substrate and a second substrate, the width of a gate pulse applied to a gate line is made longer than the writing time for one line. Further, a method for driving a liquid crystal display device, characterized in that the rising timing of the gate pulse is set at the rising timing of the gate pulse at least one time before the writing start timing to the pixel electrode.
JP61222597A 1986-09-19 1986-09-19 Driving method for liquid crystal display device Granted JPS6377031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61222597A JPS6377031A (en) 1986-09-19 1986-09-19 Driving method for liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61222597A JPS6377031A (en) 1986-09-19 1986-09-19 Driving method for liquid crystal display device

Publications (2)

Publication Number Publication Date
JPS6377031A JPS6377031A (en) 1988-04-07
JPH0584883B2 true JPH0584883B2 (en) 1993-12-03

Family

ID=16784965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61222597A Granted JPS6377031A (en) 1986-09-19 1986-09-19 Driving method for liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS6377031A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02168229A (en) * 1988-12-22 1990-06-28 Toshiba Corp Driving system for liquid crystal display device
KR100764049B1 (en) * 2001-01-06 2007-10-08 삼성전자주식회사 Gate line driving device and driving method for thin film transistor liquid crystal display
KR101166819B1 (en) 2005-06-30 2012-07-19 엘지디스플레이 주식회사 A shift register
KR101240645B1 (en) * 2005-08-29 2013-03-08 삼성디스플레이 주식회사 Display device and driving method thereof
US20120120044A1 (en) * 2009-06-22 2012-05-17 Sharp Kabushiki Kaisha Liquid crystal display device and method for driving the same
JP2012053173A (en) * 2010-08-31 2012-03-15 Toshiba Mobile Display Co Ltd Liquid crystal display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5845034A (en) * 1981-09-10 1983-03-16 Toshiba Corp Matrix for producing press mold
JPS59221183A (en) * 1983-05-31 1984-12-12 Seiko Epson Corp Driving system of liquid crystal display type picture receiver
JPS6057391A (en) * 1983-09-08 1985-04-03 シャープ株式会社 Driving of liquid crystal display unit
JPS61116392A (en) * 1984-11-09 1986-06-03 三洋電機株式会社 Driving of liquid crystal desplay unit
JPS61117599A (en) * 1984-11-13 1986-06-04 キヤノン株式会社 Switching pulse for video display unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5845034A (en) * 1981-09-10 1983-03-16 Toshiba Corp Matrix for producing press mold
JPS59221183A (en) * 1983-05-31 1984-12-12 Seiko Epson Corp Driving system of liquid crystal display type picture receiver
JPS6057391A (en) * 1983-09-08 1985-04-03 シャープ株式会社 Driving of liquid crystal display unit
JPS61116392A (en) * 1984-11-09 1986-06-03 三洋電機株式会社 Driving of liquid crystal desplay unit
JPS61117599A (en) * 1984-11-13 1986-06-04 キヤノン株式会社 Switching pulse for video display unit

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Publication number Publication date
JPS6377031A (en) 1988-04-07

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