JPH0583924B2 - - Google Patents

Description

[Detailed description of the invention]

[Purpose of the Invention] (Industrial Application Field) The present invention relates to a power supply voltage drop circuit that generates an intermediate potential by lowering the power supply voltage applied from the outside. This is to maintain reliability by supplying an intermediate potential to minute elements. (Prior Art) An example of a conventional power supply voltage drop circuit is shown in FIG. That is, P ₁ , ..., P ₅ are each P-channels
It is a MOS FET, and the source and back gate of the _P1 are connected to the power supply voltage (V _CC ) application terminal _T1 , and the _P2
The source and backgate of P3 are connected to the gate and drain of _P1 , the source and backgate of _P3 are connected to the gate and drain of _P2 , and the gate and drain of _P3 are grounded. Further, the source and back gate of _P4 are connected to the power supply voltage application terminal _T1 ,
a gate is connected to the gate and drain of the P ₂ , a source and a back gate of the P ₅ are connected to the drain of the P ₄ , respectively;
The gate and drain of _P4 are grounded.
Further, the drain of P ₄ is connected to the intermediate potential (V _MM ) output terminal T ₂ . Next, the operation of the conventional power supply voltage drop circuit shown in FIG. 2 will be explained. If the threshold value of P-channel MOS FET is |V _TP |, then the power supply voltage V _CC is 3
When a voltage higher than |V _TP | is applied, the P−
Channel MOS FETP ₁ , P ₂ , P ₃ are all on.
The drain of P ₂ , that is, the gate of P ₄ is stabilized at a potential _VO determined by the equivalent resistance of P ₁ , P ₂ , and P ₃ . At this time, the inequality 0<V _O <V _CC −2 |V _TP | holds true.
Therefore, the gate-source voltage of P ₄ exceeds 2|V _TP |, P ₄ is turned on, and an intermediate potential V _MM determined by the equivalent resistance of P ₄ and P ₅ is generated at the terminal T ₂ . Furthermore, for example, by setting the equivalent resistance value of P ₃ to be much larger than that of P ₁ and P ₂ ,
The value of V _O is set to a value approximately equal to V _CC −2 | V _TP |, so the gate-source voltage of P ₄ is
It can be set to approximately 2 |V _TP |. At this time, let the source-drain currents of P ₄ and P ₅ be I and I', respectively, and when the condition of V _CC ≧V _MM + |V _TP | is satisfied, the above I and I' become P ₄ and Using constants β ₁ and β ₂ respectively determined by P ₅ , I
≒β ₁ /2 | V _TP | ² , I′≒β ₂ /2 (V _MM − |V _TP |) ² . Since the source-drain currents of P ₄ and P ₅ are equal, β ₁ /2 | V _TP | ² = β ₂ /2 (V _MM − | V _TP |
) ² equations are established,

[Formula] |V _TP | is the intermediate potential when the value of V _CC is

[Expression] Occurs when the above occurs. (Problems to be Solved by the Invention) In the conventional power supply voltage drop circuit described with reference to FIG. Otherwise it won't work. It also consists of MOS FETs
To generate an intermediate potential depending on the threshold of
For example, if the threshold value of the MOS FET changes due to changes in the manufacturing process, there is a problem in that the desired intermediate potential cannot be generated. The present invention was made in view of the above points, and is a more stable circuit that operates even in a lower range of external power supply voltage than conventional power supply voltage drop circuits, and is less affected by fluctuations in process conditions. An object of the present invention is to provide a power supply voltage drop circuit that can generate an intermediate potential. [Structure of the Invention] (Means and Effects for Solving the Problems) In order to achieve the above object, the present invention includes a first P-channel MOS FET whose source and back gate are connected to a power supply voltage, a third P-channel MOS FET, and a third P-channel MOS FET whose source and back gate are connected to a power supply voltage. -channel
MOS FET and 4th P-channel MOS
The FET, source and back gate are
the gate and drain of the P-channel MOS FET and the gate of the third P-channel MOS FET;
Drain of FET and 4th P-channel MOS
a second P-channel MOS FET whose gate and drain are respectively connected to ground potential;
The source and back gate are connected to the ground potential, the gate is connected to the power supply voltage, and the drain is connected to the second P-channel MOS FET and the fourth P-channel MOS FET.
A first N-channel MOS FET is connected to the gate of the MOS FET and the drain of the third P-channel MOS FET, the gate and drain are connected to the ground potential, and the source and back gate are connected to the fourth P-channel MOS FET. a fifth P-channel connected to the drain of each FET;
It is characterized by being composed of MOS FET. That is, the power supply voltage drop circuit of the present invention has a power supply voltage that is applied from the outside.
By omitting channel ion implantation for all or some of the MOS FETs that constitute the MOS FET, a more stable intermediate potential that is less affected by fluctuations in process conditions can be achieved. It is characterized by being able to generate. (Embodiment) FIG. 1 shows an embodiment of a power supply voltage drop circuit according to the present invention. That is, N ₂₁ is N-channel MOS
FET, P ₂₁ ,…, P ₂₅ are each P-channel
It is a MOS FET. The source and back gate of _P21 are connected to the power supply voltage (V _CC ) application terminal _T3 .
The source and back gate of _P22 are connected to the gate and drain of _P21 , respectively, and the drain of _P22 is grounded. The source and back gate of _P23 are connected to the voltage application terminal _T3 ,
The gate of P ₂₃ is connected to the gate and drain of P ₂₁ ,
The drain of the _N21 is connected to the gate of the _P22 and the drain of the N21.
The drain of _P23 and the gate of _N21 are connected to the power supply voltage application terminal _T3 , respectively, and the source and back gate of _N21 are grounded. Further, the source and back gate of _P24 are connected to the power supply voltage application terminal _T3 , the gate of _P24 is connected to the drain of _P23 , and the source and back gate of _P25 are connected to the drain of _P24 . The gate and drain of _P25 are grounded.
Furthermore, the drain of P ₂₄ is at an intermediate potential (V _MM ′)
Connected to output terminal T ₄ . Next, the operation of the power supply voltage drop circuit according to the present invention described above will be explained using FIG. Power-supply voltage
When V _CC is 2 | V _TP | or more, by setting the threshold of N ₂₁ to 2 | V _TP | or less, N ₂₁ is turned on, and the drain potential of N ₂₁ , that is, the gate potential of P ₂₂ In order to lower V _CC −2 | V _TP | or less and turn on both P ₂₁ and P ₂₂ , the gate-source voltage of P ₂₁ , that is, P ₂₃ , becomes greater than |V _TP |.
P ₂₃ turns on. Therefore the drain voltage of P ₂₃ , i.e.
The gate potential of _P24 is stabilized at an intermediate potential between the power supply potential and V _CC -2|V _TP |. Since _P24 is turned on at this time, an intermediate potential V _MM ' determined by the equivalent resistance of _P24 and _P25 is generated at the drain of _P24 , that is, at the output terminal _T4 . Furthermore, for example, by setting the equivalent resistance of N ₂₁ very large, the drain of N ₂₁ , that is, P ₂₄
The gate potential of can be set to a value approximately equal to V _CC -2|V _TP |. Therefore, just like the power supply voltage drop circuit in the conventional example, by the constants β ₂₁ and β ₂₂ determined by P ₂₄ and P ₂₅ , respectively,

[Formula] The intermediate potential that becomes the value of V _CC is

[Expression] Occurs when the above occurs. Note that the value of |V _TP | is normally influenced and fluctuated by fluctuations in channel ion implantation process conditions, and the generated intermediate potential changes. Therefore, by using P-channel MOS FETs in which channel ion implantation is omitted as P-channel MOS FETP ₂₁ to P ₂₅ , changes in intermediate potential can be eliminated. [Effect of the invention] The power supply voltage effect circuit according to the present invention described above has the following effects:
It is possible to operate and generate an intermediate potential when the externally applied power supply voltage is lower than the conventional power supply voltage drop circuit. Furthermore, the value of |V _TP | is normally affected by fluctuations in the channel ion implantation process conditions and fluctuates, causing changes in the generated intermediate potential, but this change can be eliminated by omitting channel ion implantation. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a power supply voltage drop-down circuit device according to the present invention, and FIG. 2 is a circuit diagram showing a specific example of a conventional power supply voltage drop-down circuit. P ₁ , ~, P ₅ ...P-channel MOS FET,
P ₂₁ , ~, P ₂₅ ...P-channel MOS FET, N ₂₁
...N-channel MOS FET, V _CC ...Power supply voltage applied externally, V _MM ...Intermediate potential generated from the conventional example, V _MM ′ ...Intermediate potential generated from the power supply voltage drop circuit of the present invention potential.

Claims (1)

[Scope of Claims] 1. A first P-channel MOS FET, a third P-channel MOS FET, and a fourth P-channel MOS FET whose source and back gate are connected to a power supply voltage; at the gate and drain of the first P-channel MOS FET and at the gate of the third P-channel MOS FET;
The gate is the drain of the third P-channel MOS FET and the fourth P-channel MOS FET.
a second P-channel MOS FET whose source and back gate are connected to the ground potential, whose gate is connected to the power supply voltage, and whose drain is connected to the second P-channel MOS FET;
Channel MOS FET and 4th P-channel
A first N-channel MOS FET is connected to the gate of the MOS FET and the drain of the third P-channel MOS FET, the gate and drain are connected to the ground potential, and the source and back gate are connected to the fourth P-channel MOS FET.
The fifth P connected to the drain of each FET
- A power supply voltage drop circuit characterized by comprising a channel MOS FET. 2 1st P-channel MOS FET ~ 5th P
- The power supply voltage drop circuit according to claim 1, characterized in that a P-channel MOS FET in which channel ion implantation is omitted is used as the channel MOS FET.