JPH0622320B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0622320B2 JPH0622320B2 JP60266408A JP26640885A JPH0622320B2 JP H0622320 B2 JPH0622320 B2 JP H0622320B2 JP 60266408 A JP60266408 A JP 60266408A JP 26640885 A JP26640885 A JP 26640885A JP H0622320 B2 JPH0622320 B2 JP H0622320B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- misfet
- electrode
- signal
- input
- Prior art date
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に相補型ＭＩＳＦＥＴで
構成された入力及び電源の兼用端子周辺の半導体装置に
関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device around a dual-purpose input / power terminal composed of complementary MISFETs.
従来、入力及び電源の兼用端子周辺の半導体装置は、第
３図に示すように、入力信号か、又は入力信号よりも高
電位の第１の電源電圧ＶPPが印加される入力端子１と、
入力信号を受信するための入力回路２と、第１の電源電
圧ＶPPを出力する出力端子３と、ドレイン電極が入力端
子１に接続されゲート電極が第１の信号端子４に接続さ
れソース電極が出力端子３に接続され基板電極が接地端
子に接続されるＮチャネル・エンハンストメント型のＭ
ＩＳＦＥＴＱ１とを含んで構成される。Conventionally, as shown in FIG. 3, a semiconductor device around a dual-purpose input and power supply terminal has an input terminal 1 to which an input signal or a first power supply voltage V PP higher in potential than the input signal is applied.
An input circuit 2 for receiving an input signal, an output terminal 3 for outputting a first power supply voltage V PP , a drain electrode connected to the input terminal 1, a gate electrode connected to the first signal terminal 4 and a source electrode. Is connected to the output terminal 3 and the substrate electrode is connected to the ground terminal, which is an N-channel enhancement type M
And ISFET Q 1 .
第３図において、入力端子１に入力信号が印加された場
合は、入力回路２で入力信号を受信すると共に信号端子
４から低電位がＭＩＳＦＥＴＱ１に供給されてＭＩＳＦ
ＥＴＱ１が非導通状態となり、入力端子１と出力端子３
とが電気的に遮断され、一方、入力端子１に第１の電源
電圧ＶPPが印加された場合には、信号端子４からチャー
ジポンプ等で昇圧された高電圧がＭＩＳＦＥＴＱ１に印
加されてＭＩＳＦＥＴＱ１が導通状態となり、入力端子
１と出力端子３とが電気的に接続され、出力端子３から
第１の電源電圧ＶPPが出力される。In FIG. 3, when an input signal is applied to the input terminal 1, the input circuit 2 receives the input signal and a low potential is supplied from the signal terminal 4 to the MISFET Q 1 to cause a MISF.
ETQ 1 becomes non-conductive, input terminal 1 and output terminal 3
When the first power supply voltage V PP is applied to the input terminal 1, the high voltage boosted by the charge pump or the like is applied from the signal terminal 4 to the MISFET Q 1 and the MISFET Q 1 is electrically disconnected. 1 becomes conductive, the input terminal 1 and the output terminal 3 are electrically connected, and the output terminal 3 outputs the first power supply voltage V PP .
上述した従来の半導体装置は、バックゲートバイアスが
印加されたＭＩＳＦＥＴを介して出力端子に接続された
負荷に電流を供給し、しかもこのＭＩＳＦＥＴでの電圧
降下をできるだけ小さくするために、ＭＩＳＦＥＴのチ
ャネル幅を非常に大きく設定する必要があり、占有面積
が大きくなるという問題点があり、更に、ＭＩＳＦＥＴ
のゲート電位を昇圧するためのチャージポンプも非常に
大きな占有面積を占めるという問題点がある。The above-described conventional semiconductor device supplies the current to the load connected to the output terminal through the MISFET to which the back gate bias is applied, and further, in order to minimize the voltage drop in this MISFET, the channel width of the MISFET is reduced. Has to be set to a very large value, resulting in a large occupied area.
There is also a problem that the charge pump for boosting the gate potential of occupies a very large occupied area.
本発明の目的は、入力及び電源兼用端子の周辺回路を小
さな占有面積で形成できる半導体装置を提供することに
ある。It is an object of the present invention to provide a semiconductor device capable of forming a peripheral circuit for an input / power supply terminal with a small occupied area.
本第１の発明の半導体装置は、入力信号又は該入力信号
とは異なる電位の第１の電源電圧のいずれか一方が印加
される入力端子と、前記入力信号を受信する入力回路
と、前記第１の電源電圧を出力する出力端子と、ドレイ
ン電極が前記入力端子に接続されゲート電極が第１の信
号端子に接続され基板電極が接地端子に接続される一導
電型のチャネルを有するエンハンストメント型の第１の
ＭＩＳＦＥＴと、ドレイン電極が第２の電源電圧供給端
子に接続されゲート電極が第２の信号端子に接続されソ
ース電極が前記第１のＭＩＳＦＥＴのソース電極に接続
され基板電極が接地端子に接続される前記第１のＭＩＳ
ＦＥＴと同一導電型のチャネルを有するテプレション型
の第２のＭＩＳＦＥＴと、ドレイン電極が前記出力端子
に接続されゲート電極が前記第２の電源電圧供給端子か
前記第２の信号端子か若くは第３の信号端子のいずれか
１つに接続されソース電極が前記入力端子に接続され基
板電極が前記第１のＭＩＳＦＥＴのソース電極に接続さ
れる前記第１のＭＩＳＦＥＴと逆導電型のチャネルを有
するエンハンストメント型の第３のＭＩＳＦＥＴとを含
んで構成される。A semiconductor device according to the first invention is an input terminal to which either an input signal or a first power supply voltage having a potential different from the input signal is applied, an input circuit for receiving the input signal, and Enhancement type having an output terminal for outputting a power supply voltage of 1, and a channel of one conductivity type in which a drain electrode is connected to the input terminal, a gate electrode is connected to a first signal terminal, and a substrate electrode is connected to a ground terminal The first MISFET, the drain electrode is connected to the second power supply voltage supply terminal, the gate electrode is connected to the second signal terminal, the source electrode is connected to the source electrode of the first MISFET, and the substrate electrode is the ground terminal. Connected to the first MIS
A second MISFET of a tepletion type having a channel of the same conductivity type as the FET, and a drain electrode connected to the output terminal and a gate electrode being the second power supply voltage supply terminal, the second signal terminal, or the third. Of the first MISFET, the source electrode of which is connected to any one of the signal terminals of the first MISFET and the substrate electrode of which is connected to the source electrode of the first MISFET. A third type MISFET.
本第２の発明の半導体装置は、入力信号又は該入力信号
とは異なる電位の第１の電源電圧のいずれか一方が印加
される入力端子と、前記入力信号を受信する入力回路
と、前記第１の電源電圧を出力する出力端子と、ドレイ
ン電極が前記入力端子に接続されゲート電極が第１の信
号端子に接続され基板電極が接地端子に接続される一導
電型のチャネルを有するエンハンストメント型の第１の
ＭＩＳＦＥＴと、ドレイン電極が第２の電源電圧供給端
子に接続されゲート電極が第２の信号端子に接続されソ
ース電極が前記第１のＭＩＳＦＥＴのソース電極に接続
され基板電極が接地端子に接続される前記第１のＭＩＳ
ＦＥＴと同一導電型のチャネルを有するデプレション型
の第２のＭＩＳＦＥＴと、ドレイン電極が前記出力端子
に接続されゲート電極が前記第２の電源電圧供給端子か
前記第２の信号端子か若くは第３の信号端子のいずれか
１つに接続されソース電極が前記入力端子に接続され基
板電極が前記第１のＭＩＳＦＥＴのソース電極に接続さ
れる前記第１のＭＩＳＦＥＴと逆導電型のチャネルを有
するエンハンストメント型の第３のＭＩＳＦＥＴと、ド
レイン電極が前記第２の電源電圧供給端子に接続されゲ
ート電極が前記第２の信号端子に接続されソース電極が
前記出力端子に接続され基板電極が接地端子に接続され
る前記第１のＭＩＳＦＥＴと同一導電型のチャネルを有
するテプレション型の第４のＭＩＳＦＥＴとを含んで構
成される。A semiconductor device according to the second invention is an input terminal to which either an input signal or a first power supply voltage having a potential different from the input signal is applied, an input circuit for receiving the input signal, and Enhancement type having an output terminal for outputting a power supply voltage of 1, and a channel of one conductivity type in which a drain electrode is connected to the input terminal, a gate electrode is connected to a first signal terminal, and a substrate electrode is connected to a ground terminal The first MISFET, the drain electrode is connected to the second power supply voltage supply terminal, the gate electrode is connected to the second signal terminal, the source electrode is connected to the source electrode of the first MISFET, and the substrate electrode is the ground terminal. Connected to the first MIS
A second depletion type MISFET having a channel of the same conductivity type as that of the FET, a drain electrode connected to the output terminal, and a gate electrode connected to the second power supply voltage supply terminal, the second signal terminal, or the second signal terminal. An enhanced channel having a channel opposite in conductivity type to the first MISFET, the source electrode being connected to any one of the three signal terminals, the source electrode being connected to the input terminal, and the substrate electrode being connected to the source electrode of the first MISFET. Ment type third MISFET, a drain electrode is connected to the second power supply voltage supply terminal, a gate electrode is connected to the second signal terminal, a source electrode is connected to the output terminal, and a substrate electrode is a ground terminal. The first MISFET is connected to the fourth MISFET of the tepletion type having a channel of the same conductivity type.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本第１の発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the first invention.
第１図に示すように、半導体装置は入力信号又は入力信
号よりも高電位の第１の電源電圧ＶPPのいずれか一方が
印加される入力端子１と、入力信号を受信するための入
力回路２と、第１の電源電圧ＶPPを出力する出力端子３
と、ドレイン電極が入力端子１に接続されゲート電極が
第１の信号端子４に接続され基板電極が接地端子に接続
されるＮチャネル・エンハンストメント型の第１のＭＩ
ＳＦＥＴＱ１と、ドレイン電極が第２の電源電圧＋ＶCC
の供給端子に接続されゲート電極が第２の信号端子５に
接続されソース電極がＭＩＳＦＥＴＱ１のソース電極に
接続され基板電極が接地端子に接続されるＮチャネル・
デプレション型の第２のＭＩＳＦＥＴＱ２と、ドレイン
電極が出力端子３に接続されゲート電極が第３の信号端
子６に接続されソース電極が入力端子１に接続され基板
電極がＭＩＳＦＥＴＱ１のソース電極に接続されるＰチ
ャネル・エンハンストメント型の第３のＭＩＳＦＥＴＱ
３とを含んで構成される。As shown in FIG. 1, the semiconductor device includes an input terminal 1 to which either an input signal or a first power supply voltage V PP having a higher potential than the input signal is applied, and an input circuit for receiving the input signal. 2 and an output terminal 3 for outputting the first power supply voltage V PP
And a drain electrode is connected to the input terminal 1, a gate electrode is connected to the first signal terminal 4, and a substrate electrode is connected to the ground terminal.
SFET Q 1 and the drain electrode are the second power supply voltage + V CC
, A gate electrode connected to the second signal terminal 5, a source electrode connected to the source electrode of MISFET Q 1 , and a substrate electrode connected to the ground terminal.
The second depletion type MISFET Q 2 , the drain electrode is connected to the output terminal 3, the gate electrode is connected to the third signal terminal 6, the source electrode is connected to the input terminal 1, and the substrate electrode is the source electrode of MISFET Q 1. Connected P channel enhancement type third MISFET Q
3 is included.
第１図において、入力端子１に入力信号が印加されてい
る場合、入力回路２で入力信号を受信すると共に、第３
の信号端子６から高電位がＭＩＳＦＥＴＱ３に印加さ
れ、ＭＩＳＦＥＴＱ３が非導通状態になり入力端子１と
出力端子３とが電気的に遮断される。又、第１の信号端
子４から低電位がＭＩＳＦＥＴＱ１に印加され、ＭＩＳ
ＦＥＴＱ１が非導通状態になると共に、第２の信号端子
５からＭＩＳＦＥＴＱ２に高電位が印加されて、ＭＩＳ
ＦＥＴＱ２が導通状態となりＭＩＳＦＥＴＱ３の基板電
極が第２の電源電圧＋ＶCCと等しい電位となり、接地電
位と第２の電源電圧＋ＶCCの間で変化する入力信号が入
力端子１に印加されてもＭＩＳＦＥＴＱ３のソース電極
（Ｐ＋拡散層）が順方向バイアスされることはない。In FIG. 1, when the input signal is applied to the input terminal 1, the input circuit 2 receives the input signal and
A high potential is applied to the MISFET Q 3 from the signal terminal 6 of the above, the MISFET Q 3 becomes non-conductive, and the input terminal 1 and the output terminal 3 are electrically disconnected. Further, a low potential is applied to the MISFET Q 1 from the first signal terminal 4,
When the FET Q 1 becomes non-conductive and a high potential is applied to the MISFET Q 2 from the second signal terminal 5,
FETs Q 2 is a substrate electrode becomes MISFET Q 3 a conductive state becomes equal to the potential and the second power supply voltage + V CC, be applied to the input signal input terminal 1 changes between ground potential and the second power supply voltage + V CC The source electrode (P + diffusion layer) of MISFET Q 3 is not forward biased.
次に、出力端子３から入力端子１に印加された第１の電
源電圧ＶPPを出力する場合は、第３の信号端子６から低
電位がＭＩＳＦＥＴＱ３に印加され、ＭＩＳＦＥＴＱ３
が導通状態となり入力端子１と出力端子３とが電気的に
接続されると共に、第１の信号端子４からチャージポン
プ等で昇圧された高電圧がＭＩＳＦＥＴＱ１に印加され
てＭＩＳＦＥＴＱ１が導通状態となり、第２の信号端子
５から低電位がＭＩＳＦＥＴＱ２に印加され、ＭＩＳＦ
ＥＴＱ２が非導通状態となりＭＩＳＦＥＴＱ３の基板電
極が第１の電源電圧ＶPPと等しい電位になる。Next, when outputting the first power supply voltage V PP applied to the input terminal 1 from the output terminal 3, a low potential is applied to the MISFET Q 3 from the third signal terminal 6 and the MISFET Q 3
With but the input terminal 1 becomes conductive and the output terminal 3 is electrically connected, high voltage boosted by the charge pump or the like from the first signal terminal 4 is applied to the MISFET Q 1 MISFET Q 1 becomes conductive , A low potential is applied to the MISFET Q 2 from the second signal terminal 5,
ETQ 2 becomes non-conductive, and the substrate electrode of MISFET Q 3 has a potential equal to the first power supply voltage V PP .
ここで、ＭＩＳＦＥＴＱ３はＰチャネル型であるためバ
ックゲートバイアスも印加されず高い電流増幅率で動作
するためＭＩＳＦＥＴＱ３の占める占有面積は非常に小
さくなる。Here, since the MISFET Q 3 is a P-channel type, the back gate bias is not applied and the MISFET Q 3 operates at a high current amplification factor, so that the occupied area of the MISFET Q 3 becomes very small.
更に、バックゲートバイアスが印加されるＭＩＳＦＥＴ
Ｑ１を介して負荷電流を供給する必要がないためＭＩＳ
ＦＥＴＱ１の占める占有面積も非常に小さくすることが
できると共に、ＭＩＳＦＥＴＱ１のゲート電位を昇圧す
るためのチャージポンプも小さな占有面積で形成でき
る。Further, a MISFET to which a back gate bias is applied
MIS because there is no need to supply load current through Q 1.
Occupation area occupied by FETs Q 1 also it is possible to very small, even a charge pump for boosting the gate potential of the MISFET Q 1 can be formed with a small occupied area.
以上の説明は、ＭＩＳＦＥＴＱ３のゲート電極に、信号
端子６から第３の信号を入力してその導通状態を制御す
る例について述べたが、これ迄の説明から明らかなよう
に、第３の信号と第２の信号とは同相信号であるので、
第３の信号に換えて第２の信号をＭＩＳＦＥＴＱ３のゲ
ート電極に入力するように構成すれば、より少ない信号
で上述したと同様の効果が得られる。In the above description, an example of inputting a third signal from the signal terminal 6 to the gate electrode of the MISFET Q 3 to control the conduction state thereof has been described. However, as is apparent from the above description, the third signal And the second signal are in-phase signals,
If the second signal is input to the gate electrode of the MISFET Q 3 instead of the third signal, the same effect as described above can be obtained with a smaller number of signals.
又、ＭＩＳＦＥＴＱ３のゲート電極に、直流の第２の電
源電圧ＶCCを与えるように構成することによっても、回
路の動作制御に必要な信号を減らすことができる。すな
わち、この構成で入力端子１に第１の電源電圧ＶPPが印
加された場合、つまりＭＩＳＦＥＴＱ３のソース電極に
電圧ＶPPが与えられゲート電極に電圧ＶCCが与えられた
場合を考える。このとき、第１の電源電圧ＶPPが第２の
電源電圧ＶCCに対して、ＶPP≧ＶCC＋｜ＶTP｜（但し、
ＶTPは、ＭＩＳＦＥＴＱ３のしきい値電圧）を満足する
ような電圧であれば、良く知られているように、ＭＩＳ
ＦＥＴＱ３にはチャネルが形成されこのＦＥＴは導通状
態となる。つまり、ＭＩＳＦＥＴＱ３は、入力端子１へ
の第１の電源電圧ＶPPの印加に伴って自動的に導通状態
となり、出力端子３から電圧ＶPPが出力される。一方、
入力端子１に第１の信号が入力されているとき、その振
幅は前述したように接地電位と第２の電源電圧ＶCCとの
間にあるので、ＭＩＳＦＥＴＱ３のソース電極の電圧は
最大でもＶCCを越えることはない。従って、上式から明
かなように、ＭＩＳＦＥＴＱ３が導通することはなく入
力端子１と出力端子３との間は遮断される。このように
して、第３の信号を不要にすることができる。Further, by configuring the gate electrode of the MISFET Q 3 to supply the DC second power supply voltage V CC , it is possible to reduce the signals necessary for controlling the operation of the circuit. That is, when the first power supply voltage V PP to the input terminal 1 in this configuration is applied, a case where that is the voltage V PP to the source electrode of the MISFET Q 3 given voltage V CC to the gate electrode is given. At this time, the first power supply voltage V PP is greater than the second power supply voltage V CC by V PP ≧ V CC + | V TP | (However,
As long as V TP is a voltage that satisfies the threshold voltage of MISFET Q 3 , it is well known that MIS
A channel is formed in the FET Q 3 and this FET becomes conductive. That is, the MISFET Q 3 automatically becomes conductive with the application of the first power supply voltage V PP to the input terminal 1, and the voltage V PP is output from the output terminal 3. on the other hand,
When the first signal is input to the input terminal 1, its amplitude is between the ground potential and the second power supply voltage V CC as described above, so the voltage of the source electrode of the MISFET Q 3 is V at the maximum. It does not exceed CC . Therefore, as is clear from the above equation, the MISFET Q 3 does not conduct, and the input terminal 1 and the output terminal 3 are disconnected. In this way, the third signal can be dispensed with.
第２図に示す実施例は、上述した第１の発明の半導体装
置にドレイン電極が第２の電源電圧＋ＶCCの供給端子に
接続されゲート電極が第２の信号端子５に接続されソー
ス電極が出力端子３に接続され基板電極が接地端子に接
続されるＮチャネル・デプレション型の第４のＭＩＳＦ
ＥＴＱ４を追加を追加接続した回路である。In the embodiment shown in FIG. 2, the drain electrode is connected to the supply terminal of the second power supply voltage + V CC , the gate electrode is connected to the second signal terminal 5 and the source electrode is connected to the semiconductor device of the first invention described above. N-channel depletion type fourth MISF connected to the output terminal 3 and the substrate electrode connected to the ground terminal
It is a circuit in which an ETQ 4 is additionally connected.
第２図に示すえように、ＭＩＳＦＥＴＱ４を追加するこ
とにより、入力端子１に入力信号が印加されている期
間、第２の信号端子５から高電位がＭＩＳＦＥＴＱ４に
印加されＭＩＳＦＥＴＱ４が導通状態となるため、入力
端子１と出力端子３とを電気的に遮断すると共に出力端
子３から第２の電源電圧＋ＶCCを出力することができ
る。As example shown in FIG. 2, by adding a MISFET Q 4, a period where the input signal to the input terminal 1 is applied, the second MISFET Q 4 high potential from the signal terminal 5 is applied to the MISFET Q 4 conductive state Therefore, the input terminal 1 and the output terminal 3 can be electrically disconnected and the second power supply voltage + V CC can be output from the output terminal 3.
以上説明したように本発明の半導体装置は、入力及び電
源兼用端子の周辺回路において、負荷電流をバックゲー
トバイアスが印加されず高い電流増幅率で動作する導電
チャネル型のＭＩＳＦＥＴを介して供給することによ
り、周辺回路を小さな占有面積で形成できるという効果
がある。As described above, in the semiconductor device of the present invention, the load current is supplied through the conductive channel type MISFET that operates at a high current amplification factor without applying the back gate bias in the peripheral circuit of the input and power supply terminal. As a result, the peripheral circuit can be formed with a small occupied area.
第１図は本第１の発明の一実施例の回路図、第２図は本
第２の発明の一実施例の回路図、第３図は従来の半導体
装置の一例の回路図である。 １……入力端子、２……入力回路、３……出力端子、
４，５，６……信号端子。FIG. 1 is a circuit diagram of an embodiment of the first invention, FIG. 2 is a circuit diagram of an embodiment of the second invention, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor device. 1 …… input terminal, 2 …… input circuit, 3 …… output terminal,
4, 5, 6 ... Signal terminals.
Claims (2)
第１の電源電圧のいずれか一方が印加される入力端子
と、 前記入力信号を受信する入力回路と、 前記第１の電源電圧を出力する出力端子と、 ドレイン電極が前記入力端子に接続されゲート電極が第
１の信号端子に接続され基板電極が接地端子に接続され
る一導電型のチャネルを有するエンハンストメント型の
第１のＭＩＳＦＥＴと、 ドレイン電極が第２の電源電圧供給端子に接続されゲー
ト電極が第２の信号端子に接続されソース電極が前記第
１のＭＩＳＦＥＴのソース電極に接続され基板電極が接
地端子に接続される前記第１のＭＩＳＦＥＴと同一導電
型のチャネルを有するデプレション型の第２のＭＩＳＦ
ＥＴと、 ドレイン電極が前記出力端子に接続されゲート電極が前
記第２の電源電圧供給端子か前記第２の信号端子か若く
は第３の信号端子のいずれか１つに接続されソース電極
が前記入力端子に接続され基板電極が前記第１のＭＩＳ
ＦＥＴのソース電極に接続される前記第１のＭＩＳＦＥ
Ｔと逆導電型のチャネルを有するエンハンストメント型
の第３のＭＩＳＦＥＴとを含むことを特徴とする半導体
装置。1. An input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied, an input circuit for receiving the input signal, and the first power supply voltage. An enhancement type first MISFET having an output terminal for outputting and a channel of one conductivity type in which a drain electrode is connected to the input terminal, a gate electrode is connected to a first signal terminal, and a substrate electrode is connected to a ground terminal. The drain electrode is connected to the second power supply voltage supply terminal, the gate electrode is connected to the second signal terminal, the source electrode is connected to the source electrode of the first MISFET, and the substrate electrode is connected to the ground terminal. Depletion-type second MISF having a channel of the same conductivity type as the first MISFET
ET, a drain electrode is connected to the output terminal, a gate electrode is connected to any one of the second power supply voltage supply terminal, the second signal terminal or a third signal terminal, and the source electrode is The substrate electrode connected to the input terminal is the first MIS.
The first MISFE connected to the source electrode of the FET
A semiconductor device comprising T and an enhancement type third MISFET having a channel of an opposite conductivity type.
第１の電源電圧のいずれか一方が印加される入力端子
と、 前記入力信号を受信する入力回路と、 前記第１の電源電圧を出力する出力端子と、 ドレイン電極が前記入力端子に接続されゲート電極が第
１の信号端子に接続され基板電極が接地端子に接続され
る一導電型のチャネルを有するエンハンストメント型の
第１のＭＩＳＦＥＴと、 ドレイン電極が第２の電源電圧供給端子に接続されゲー
ト電極が第２の信号端子に接続されソース電極が前記第
１のＭＩＳＦＥＴのソース電極に接続され基板電極が接
地端子に接続される前記第１のＭＩＳＦＥＴと同一導電
型のチャネルを有するデプレション型の第２のＭＩＳＦ
ＥＴと、 ドレイン電極が前記出力端子に接続されゲート電極が前
記第２の電源電圧供給端子か前記第２の信号端子か若く
は第３の信号端子のいずれか１つに接続されソース電極
が前記入力端子に接続され基板電極が前記第１のＭＩＳ
ＦＥＴのソース電極に接続される前記第１のＭＩＳＦＥ
Ｔと逆導電型のチャネルを有するエンハンストメント型
の第３のＭＩＳＦＥＴと、 ドレイン電極が前記第２の電源電圧供給端子に接続され
ゲート電極が前記第２の信号端子に接続されソース電極
が前期出力端子に接続され基板電極が接地端子に接続さ
れる前記第１のＭＩＳＦＥＴと同一導電型のチャネルを
有するデプレション型の第４のＭＩＳＦＥＴとを含むこ
とを特徴とする半導体装置。2. An input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied, an input circuit for receiving the input signal, and the first power supply voltage. An enhancement type first MISFET having an output terminal for outputting and a channel of one conductivity type in which a drain electrode is connected to the input terminal, a gate electrode is connected to a first signal terminal, and a substrate electrode is connected to a ground terminal. The drain electrode is connected to the second power supply voltage supply terminal, the gate electrode is connected to the second signal terminal, the source electrode is connected to the source electrode of the first MISFET, and the substrate electrode is connected to the ground terminal. Depletion-type second MISF having a channel of the same conductivity type as the first MISFET
ET, a drain electrode is connected to the output terminal, a gate electrode is connected to any one of the second power supply voltage supply terminal, the second signal terminal or a third signal terminal, and the source electrode is The substrate electrode connected to the input terminal is the first MIS.
The first MISFE connected to the source electrode of the FET
An enhancement-type third MISFET having a channel of a conductivity type opposite to that of T, a drain electrode connected to the second power supply voltage supply terminal, a gate electrode connected to the second signal terminal, and a source electrode output in the previous period. A semiconductor device comprising: a depletion type fourth MISFET having a channel of the same conductivity type as the first MISFET connected to a terminal and a substrate electrode connected to a ground terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60266408A JPH0622320B2 (en) | 1985-11-26 | 1985-11-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60266408A JPH0622320B2 (en) | 1985-11-26 | 1985-11-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62125711A JPS62125711A (en) | 1987-06-08 |
| JPH0622320B2 true JPH0622320B2 (en) | 1994-03-23 |
Family
ID=17430516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60266408A Expired - Lifetime JPH0622320B2 (en) | 1985-11-26 | 1985-11-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622320B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2570591B2 (en) * | 1993-09-16 | 1997-01-08 | 日本電気株式会社 | Transistor circuit |
| US8572893B2 (en) * | 2009-06-03 | 2013-11-05 | Sharp Kabushiki Kaisha | Display device |
-
1985
- 1985-11-26 JP JP60266408A patent/JPH0622320B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62125711A (en) | 1987-06-08 |
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| Date | Code | Title | Description |
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| EXPY | Cancellation because of completion of term |