JPH05326853A - Transistor circuit - Google Patents

Abstract

PURPOSE:To obtain a transistor circuit such as an open drain output circuit or the like which is kept stable in logic after an electrical power is applied to the circuit. CONSTITUTION:A protective transistor 4 is connected in series with an output transistor 1 so as to set an output terminal 2 to a high impedance level even while a gate input, is unstable in level after the application of an electric power. The gate level of the protective transistor 4 is controlled in delay time by a delay circuit 9 composed of a resistor 6 and a capacitor 7, and the delay time concerned is set longer than the level stabilization time of a gate input, whereby the time when the output terminal 2 is unastable in level at the application of an electric power can be eliminated. Therefore, a transistor can be protected against damage when a power is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor circuit such as a transistor open drain output circuit used as a part of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional N-channel transistor open drain output circuit. In the figure, reference numeral 1 is an N-channel transistor (hereinafter simply referred to as transistor), the source electrode of which is grounded. Reference numeral 2 is an output terminal provided on the drain electrode of the transistor 1, and reference numeral 3 is a control signal applied to the gate electrode as the control electrode of the transistor 1.

Next, the operation will be described. When the control signal 3 becomes "H" level, the transistor 1 becomes conductive and the output terminal 2 becomes "L" level. When the control signal goes to "L" level, the transistor 1 is cut off and the output terminal 2
Becomes a high impedance state.

[0004]

Since the conventional N-channel transistor open drain circuit is constructed as described above, when this circuit is used as a part of a semiconductor integrated circuit, power is supplied to this semiconductor integrated circuit. Shortly after
There may be a period in which the level of the gate electrode of the transistor 1 becomes unstable, and the transistor 1 may become conductive when the level of the gate electrode becomes high during that period.

In such a circuit, the output terminal 2 is current-limited through a resistor or the like if it is not particularly necessary to limit the output current for the purpose of preventing the output terminal 2 from being in an output state. Instead, it may be connected directly to the power supply.
In that case, if the transistor 1 is turned on during the period when the level of the gate electrode is unstable, an excessive current may flow in the transistor 1 because the output current is not limited, and the transistor 1 may be destroyed. There was a problem.

The present invention has been made in order to solve the above problems, and an object thereof is to obtain a transistor circuit such as a transistor drain open circuit in which a logic indeterminate period does not occur immediately after power-on. And

[0007]

In a transistor circuit according to the present invention, first and second transistors are connected in series between an output terminal and a reference potential such as a ground potential, and the first transistor is controlled by a control signal. To control it,
A power supply voltage is applied to the control electrode of the second transistor via a delay circuit.

[0008]

In the transistor circuit according to the present invention, when the power is turned on, the power supply voltage is delayed by the delay circuit to make the second transistor conductive. Therefore, during this delay time, the second transistor becomes non-conductive. , Therefore the first
The transistor is also non-conductive, the output terminal provided in the first transistor is held in a high impedance state, and an excessive current does not flow.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, portions corresponding to those in FIG. In FIG. 1, reference numeral 4 denotes an N-channel transistor (hereinafter simply referred to as a transistor), the source electrode of which is grounded and the drain electrode of which is connected to the source electrode of the transistor 1, so that these transistors 1 and 4 are connected in series. It is connected. Reference numeral 5 is a power supply terminal, 6 is a resistor connected between the power supply terminal 5 and a gate electrode as a control electrode of the transistor 4, 7 is a capacitor connected between the gate electrode and ground, and 8 is the gate electrode and ground. A pull-down resistor connected between 9 is a delay circuit composed of the resistor 6 and the capacitor 7. Note that the transistor 1 is a first transistor and the transistor 4 is a second transistor.

Next, the operation will be described. When the semiconductor integrated circuit including the circuit of FIG. 1 is powered on, the power supply voltage is applied from the power supply terminal 5 to the delay circuit 9. At this time, the transistor 4 is in a non-conducting state, so that the transistor 1 is also in a non-conducting state. Next, when the delay time of the delay circuit 9 has passed, the power supply voltage is applied to the gate electrode of the transistor 4, and the transistor 4 becomes conductive.

Therefore, even if the level of the gate electrode of the transistor 1 becomes unstable during this delay time, the transistor 1 will not become conductive. By selecting the time constant of the delay circuit 9 to be longer than the level instability period immediately after the power is turned on, the output terminal 1 can be held in the high impedance state during this period. In the high impedance state, when the control signal 3 is set to "H" level, the transistors 1 and 4 are turned on and the output terminal 2 is set to "L" level.

Example 2. Although the pull-down resistor 8 is connected to the gate electrode of the transistor 1 in the first embodiment, if the potential of the power supply terminal 5 before the power is turned on is the ground potential, as shown in FIG. The same effect can be obtained even if the resistor is omitted.

Embodiment 3. Although the N-channel transistor open drain output circuit is used in the first and second embodiments,
By setting the power supply terminal 5 to a voltage lower than the ground potential and making the transistors 1 and 4 P-channel transistors,
The channel transistor open drain output circuit also has the same effects as those of the first and second embodiments.

[0014]

As described above, according to the present invention, the two transistors are connected in cascade, and the power supply voltage is applied to the control electrode of the transistor on the reference potential side through the delay circuit. There is an effect that the unstable state can be eliminated and the destruction of the transistor can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional N-channel transistor open drain output circuit.

[Explanation of symbols]

 1 N-channel transistor (first transistor) 3 Control signal 4 N-channel transistor (second transistor) 5 Power supply terminal 9 Delay circuit

Claims (1)

[Claims] 1. A first transistor to which a control signal is applied to a control electrode, a second transistor connected in series between the first transistor and a reference potential, and control of the second transistor. A transistor circuit including a delay circuit connected between an electrode and a power supply terminal.