JPH0583851U - Information processing equipment - Google Patents

Abstract

(57) [Summary] [Purpose] If an access from the CPU card is not made within a certain period of time, it is judged as a CPU card error and the I / O card and external I / O equipment are placed in a fail-safe state. An information processing device capable of performing is realized. [Configuration] CPU card 2 and a plurality of I / O cards 3 are V
An information processing device connected by the ME bus 1, which is set by the CPU card and timer clear means 4 for generating a clear signal in the I / O card 3 by the regular access of the CPU card 2 in a normal state. The timer means 5 counts the fixed time to be counted, and when the clear signal from the timer clearing means 4 is given, the timer is cleared and the timer means 5 continues to count the fixed time from the beginning, and the timer means 5 counts up without being cleared. CPU card 2 when
An information processing apparatus, comprising: an abnormality detecting unit 6 that determines an abnormality and performs an abnormal condition process set in advance by the CPU card 2.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an information processing device, and more particularly, to improvement of a method of coping with a slave side when an abnormality occurs in a CPU card in an information processing device having a VMEbus system.

[0002]

[Prior Art]

 In a commonly used information processing device having a VME bus, a signal notifying an abnormality of the CPU card is not defined. Therefore, there is a problem that each I / O card (slave) cannot recognize the abnormality of the CPU card when the CPU card (master) is abnormal such as CPU runaway.

As an example of the construction of the VMEbus system, in a system in which the SY SRESET * signal is asserted when the CPU card (master) is abnormal, all I / O cards (slaves) are reset at the same time.

[0004]

[Problems to be solved by the device]

 However, even the above system may not be sufficient as fail-safe. That is, when the CPU card is abnormal, it is necessary for each I / O card to recognize it and take necessary measures so that the I / O card enters a fail-safe state.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object thereof is to judge that a CPU card is abnormal when an access from the CPU card is not made within a certain period of time. In other words, it is to realize an information processing device that can put an I / O card and an external I / O device in a fail-safe state.

[0006]

[Means for Solving the Problems]

 Means for solving the above-mentioned problem is an information processing device in which a CPU card and a plurality of I / O cards are connected by a VME bus, and the I / O card is periodically accessed during normal operation. The timer clear means for generating a clear signal and the fixed time set by the CPU card are counted, and when the clear signal from the timer clear means is given, the timer is cleared and the fixed time from the beginning is counted. A timer means for continuing and an abnormality detecting means for judging an abnormality in the CPU card when the timer means counts up without being cleared, and for performing abnormality processing set in advance by the CPU card. To do.

[0007]

[Action]

 In the present invention, the CPU card periodically outputs a specific address on the VME bus during normal operation. In the I / O card, the timer clear device decodes the address on the VME bus, and outputs the decode signal for the specific address to the timer as a clear signal. The timer counts the timer. When the clear signal is input from the timer clear device, the timer is cleared and the timer count continues. When the timer counts up to a predetermined value, the abnormality detection means generates an abnormality signal.

[0008]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the operating state of each part.

Here, in the case where the CPU card 2 uses the address only function of the VMEbus 1 as a means for periodically accessing the timer clearing device 4 in the plurality of I / O cards 3 provided. The configuration is shown.

In these drawings, the CPU card 2 is connected to the VMEbus 1 as a master, and the plurality of I / O cards 3 are connected to the VMEbus 1 as slaves. The I / O card 3 includes a timer clear device 4, a timer device 5, and a CPU card abnormality detection device. The timer device 5 is composed of a timer value setting register 7 and a timer 8.

The timer clear device 4 is an address decoding circuit, is connected to the VME bus by an address line and an AS * line, and outputs a clear signal to the timer 8. In the timer value setting register 7, the CPU card 2 sets the timer value counted by the timer 8. The timer 8 counts the timer value set by the timer value setting register 7, and when a clear signal is input from the timer clear signal 4, it clears and continues counting. When the timer 8 counts up, the CPU card abnormal signal generator 10 outputs a CPU card abnormal signal to the I / O card controller 11. The interrupt processing / reset setting register 9 is a register which is set in advance by the CPU card 2 as to whether the I / O card 11 is to be subjected to interrupt processing or the I / O card 3 is reset when the CPU card is abnormal. When the CPU card abnormality signal is input from the CPU card abnormality signal generation device 10, the I / O card control device 11 sets the interrupt processing / reset setting register 9 to the I / O card to the OR device 12. It outputs a reset signal or an interrupt signal to the I / O card. The OR device 12 resets the I / O card 3 when the I / O card reset signal is input by the I / O card control device 11 or the SYSRESET * signal is input by the VMEbus 1. Output a signal.

First, as initial settings, a timer value and CPU card abnormal processing (interrupt / reset) are set in advance (FIG. 2 CPU card side step 1). During the normal operation of the CPU card 2, a specific address is periodically output to the VMEbus 1 (at every fixed time less than the timer time set in the timer value setting register 7) (address Only cycle (Figure 2, CPU card side steps 2 and 3)). In the I / O card 3, the timer clearing device 4 decodes a specific address on the VMEbus 1. If a decode signal for the specific address is generated, it is output to the timer 8 as a clear signal. The timer 8 counts the timer, and when the clear signal is input from the timer clear device 4, the timer is cleared (steps 1 and 3 on the I / O card side in FIG. 2) and then the timer count is continued (FIG. 2 I / O). Card side step 2).

When the specific address is not generated on the VMEbus 1, the clear signal is not generated and the timer counts up to the predetermined value (FIG. 2, step 4 on the I / O card side). In this case, the CPU card abnormality signal generation device 10 in the CPU card abnormality detection device 6 generates a CPU card abnormality signal (step 5 in FIG. 2 I / O card side). The I / O card control device 11 that has received this CPU card abnormal signal follows the setting of the interrupt processing / reset setting register (step 1 on the CPU card side in FIG. 2) to reset the I / O card to the OR device 12, for example. The signal is output (step 7 in FIG. 2 I / O card side). Therefore, the reset signal output from the logical sum device 12 resets the I / O card 3 (step 8 in FIG. 2, I / O card side). Even when the SYSMESET * signal is generated on the VME bus 1, the OR signal is output from the OR device 12 and the I / O card 3 is reset. When an interrupt signal is output from the I / O card controller 11 (I / O card side step 9 in FIG. 2), the I / O card 3 executes interrupt processing (FIG. 2 I / O card side). Step 10).

As described above, each I / O card can recognize the abnormality of the CPU card in the VMEbus system by providing the function of monitoring the CPU card in each I / O card. It will be possible. Therefore, it becomes possible to deal with each I / O card by individually setting the I / O card itself and the external I / O device to a fail-safe state.

[0015]

[Effect of the device]

 As described in detail with the embodiments above, each I / O card recognizes a CPU card abnormality in the VMEbus system by providing the function of monitoring the CPU card in each I / O card. If the CPU card does not access within a certain period of time, it is judged as a CPU card error and the I / O card and external I / O device are placed in a fail-safe state. It is possible to realize an information processing device capable of

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an operation in one embodiment of the present invention.

[Explanation of symbols]

 1 VMEbus 2 CPU card 3 I / O card 4 Timer clear device 5 Timer device 6 CPU card error detection device 7 Timer value setting register 8 Timer 9 Interrupt processing / reset setting register 10 CPU card error signal generation device 11 I / O card Control device 12 OR device

Claims (1)

[Scope of utility model registration request] 1. An information processing apparatus comprising a CPU card (2) and a plurality of I / O cards (3) connected by a VMEbus (1), wherein the CPU card is provided in the I / O card (3). (2) A timer clear means (4) for generating a clear signal by the regular access during normal operation, and a constant time set by the CPU card (2) are counted, and a clear signal from the timer clear means (4) The timer means (5) keeps counting the constant time from the beginning and the CPU card (2) is judged to be abnormal when the timer means (5) is counted up without being cleared. In addition, the information processing apparatus is provided with an abnormality detecting unit (6) for performing abnormal time processing set in advance from the CPU card (2).