JPH0582778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has two types of operation: on-delay operation in which the output signal is turned on after a certain period of time after the input signal is turned on, and off-delay operation in which the output signal is turned off after a certain period of time after the input signal is turned off. The present invention relates to a timer circuit that can arbitrarily switch between different operating modes.

Conventionally, this type of timer circuit has been shown in FIG. As shown in the figure, three types of circuits are built in: a timer circuit 1 for on-delay operation, a timer circuit 2 for off-delay operation, and a timer circuit 3 for one-shot multivibrator operation. , 2, and 3 are operated selectively by changeover switches S1 and S2. In such a configuration, each of the three timer circuits 1, 2, and 3 is provided with overlapping time-limiting elements such as an integrating circuit, waveform shaping circuits, etc., so the overall number of circuit elements is large, and therefore expensive. It has no choice but to become a thing.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to enable the above-mentioned on-delay and off-delay operations to be performed with a minimum number of circuit elements by sharing most of the circuit elements. The purpose of the present invention is to provide a timer circuit with the following functions.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows a first embodiment of a timer circuit according to the invention.

This timer circuit has an input terminal IN to which a square wave input signal is given, and one input terminal (the upper input terminal in the diagram) that receives the input signal via this input terminal IN.
a first exclusive OR circuit 5 that applies a signal to A second exclusive OR circuit 7 to which an output signal is applied to one input terminal (the upper input terminal in the figure), an inverter 8 that inverts the output of this circuit 7, and a dual exclusive OR circuit 5 . , exclusive OR circuit 7, and inverter 8 to obtain either an on-delay output or an off-delay output signal.

Logic setting circuit 9 includes switch S4 and resistor R3.
When switch S4 is closed, the logic at the other input terminals of exclusive OR circuits 5 and 7 is set to L level via switch S4, while when switch S4 is opened, , the other input terminal of the exclusive OR circuits 5 and 7 is connected to the resistor R3.
It is connected to the power supply line +V via the power supply line +V, and its input logic is set to H level.

The integrating circuit 6 includes a transistor Q1 that is driven to conduct through a resistor R4 when the output b of the exclusive OR circuit 5 is at H level, and a transistor Q1 that is turned on via a resistor R4.
It consists of a resistor R5 and a resistor R6 connected in series between the collector of the power supply line and the power supply line +V, and a capacitor C2 connected in parallel with the resistor R6, and a delay operation is performed by the discharging operation of the capacitor C2. It's summery. Note that the resistor R6 is a variable resistor, and the delay time can be adjusted by adjusting the resistance value.

In the figure, numeral 4 is a differential circuit made up of a capacitor C1, a resistor R1, and a resistor R2, and 10 in the figure is a switching circuit made up of a switch S3 and diodes D1 and D2.

The differentiating circuit 4 is provided between the input terminal IN and the first and second exclusive OR circuits 5 and 7, and when the switch S3 of the switching circuit 10 is closed, the resistors R1,
It operates only when the connection point side of R2 is connected to the ground line G via diode D1 and switch R3, and outputs a pulse signal of a constant width in response to the rising edge of the input signal applied to the input terminal IN. , when the switch S3 is open, it does not function and the input terminal IN is directly connected to one input terminal of the exclusive OR circuit 5 via the resistors R1 and R2.

The switching circuit 10 operates by opening and closing the switch S3.
It is configured to switch between inputting the input signal directly to one input terminal of the exclusive OR circuit 5 or inputting the output signal of the differentiation circuit 4.

Depending on the switching state of the switch S3 of the switching circuit 10 and the switch S4 of the logic setting circuit 9, the exclusive OR circuit 7 and the inverter 8 output either an on-delay output, an off-delay output, or a one-shot multivibrator output. The output signal is obtained.

Next, the on-delay operation and off-delay operation of the timer circuit according to the present invention configured as described above will be explained in order according to the waveform diagram of FIG. 3.

First, the on-delay operation will be explained. In this case, the switch S3 is turned off to disable the differentiating circuit 4, and the switch S4 of the logic setting circuit 9 is turned off to supply an H level input signal to the other input terminal of each of the exclusive OR circuits 5 and 7. Apply. As a result, exclusive OR circuits 5 and 7 each function as an inverter. In this state, as shown in the on-delay part in FIG. It is directly input, and therefore, at the output terminal b of the exclusive OR circuit 5, a signal obtained by inverting the input signal IN is generated. The transistor Q1 of the integrating circuit 6 is conductive when the signal b is at H level.
Its output signal c is at L level. When the signal b falls to the L level from this state, the transistor Q1 is turned off based on the change in the falling level, and the output signal c becomes the H level. At this time, the capacitor C2 is discharged, so The rising of the output signal c from the L level to the H level is delayed in an exponential curve. SL shown in FIG. 3 is the threshold level of the exclusive OR circuit 7, and the output signal c of the integrating circuit 6 is binarized at this threshold level SL in the exclusive OR circuit 7. The signal is further inverted by the inverter 8 and sent to the output terminal OUT.
appears in As a result, the output signal as shown in the figure
OUT turns on with a delay of a certain time T1 after the input signal IN turns on. This is an on-delay operation.

Next, off-delay operation will be explained. In this case, the switch S3 is turned off in the same manner as above, the switch S4 of the logic setting circuit 9 is turned on, and an L level input signal is applied to the other input terminal of the exclusive OR circuits 5 and 7. OR circuits 5 and 7 are made to function as non-inverters. and,
As shown in FIG. 3, when the input signal IN which changes from the L level to the H level is applied, a square wave signal b having the same polarity as the input signal IN appears from the exclusive OR circuit 5. Therefore, the integrator circuit 6 receives the input signal
A signal obtained by starting integration based on a change in the falling edge of IN, performing a delay operation, and binarizing the output signal c of this integrating circuit 6 at a threshold level SL.
As shown in the figure, OUT will be turned off a certain period of time T1 after input IN is turned off. This is off-delay operation.

As is clear from the above description, the timer circuit according to the present invention includes a first exclusive OR circuit (exclusive logic) that outputs the exclusive OR of the logic of the input binary signal and the set logic. (equivalent to sum circuit 5) and
an integrating circuit (corresponding to the integrating circuit 6) that starts integration based on a change in either the rising edge or falling edge of the signal obtained from the first exclusive OR circuit, and is reset based on the other change; and a second exclusive OR circuit (exclusive OR circuit 7) that obtains an exclusive OR of the logic of the signal obtained from the integrating circuit and the set logic, and the first and second The set logic in the exclusive OR circuit is switched and set, and the first exclusive OR circuit functions as an inverter or a non-inverter for the logic of the input binary signal, while the second exclusive OR circuit functions as an inverter or a non-inverter for the logic of the input binary signal. A logic setting circuit (logic setting circuit 9) that causes the sum circuit to function as an inverter or non-inverter for the logic of the signal obtained from the integrating circuit.
(equivalent to)).

Therefore, if the respective logics of the first exclusive OR circuit and the second exclusive OR circuit are switched to either "H" or "L", the first exclusive OR circuit As a result of functioning as an inverter or non-inverter for the logic of a binary signal, the integrating circuit starts integration based on a change in either the rising edge or the falling edge of the signal obtained from the first exclusive OR circuit. , and is reset based on the change in the other, and this is waveform-shaped by the second exclusive OR circuit, thereby achieving the function of an on-delay timer or an off-delay timer.

In addition, when achieving the above on-delay and off-delay timer functions, the first exclusive OR circuit, the integrating circuit, the second exclusive OR circuit, etc. can be shared, so this type of timer circuit can be manufactured at low cost. can do.

In addition, in the description of this embodiment, the switching circuit 10
Turn off the switch S3 of the logic setting circuit 9 without making the differentiation circuit 4 function, and turn off the switch S4 of the logic setting circuit 9.
In the explanation above, the timer circuit is provided with on-delay and off-delay functions by turning on the timer circuit, but by turning on switch S3 and making the differentiator circuit 4 function effectively, the signal obtained by differentiating the rising edge of the input signal IN can be converted into an exclusive logic signal. The input signal is input to one input terminal a of the summation circuit 5, and the input signal is output as the output signal OUT.
A pulse signal of a constant width is output in response to the rising edge of IN, and it is also possible to give this timer circuit the function of a one-shot multivibrator.

Next, a second embodiment of the present invention will be described.

FIG. 4 shows a second embodiment of the timer circuit according to the invention.

This timer circuit basically has the same configuration as the first embodiment shown in FIG. 2, except that the operating polarity of the differentiating circuit 4 and the operating polarity of the switching circuit 10 are reversed. Since the elements have the same functions as those in the first embodiment, the same effects as in the first embodiment can be obtained.

In the above explanation, as also explained in FIG. 3, the integrating circuit 6 starts integration based on the change in the falling edge of the signal obtained from the first exclusive OR circuit 5, and integrates the signal based on the change in the rising edge. In the present invention, the integrating circuit 6 starts the integration based on the change in the rising edge of the signal obtained from the exclusive OR circuit 5, and resets the signal based on the change in the falling edge. It may be reset based on.

In other words, as shown in FIG.
is provided, and unlike the case of the timer circuit shown in FIG. Integration is started based on a change in the rising edge of the output signal and reset based on a change in the falling edge of the output signal.

In this way, as shown in FIG.
Unlike the waveform diagram shown in the figure, in the case of on-delay, the input signal b to the integrating circuit 6 is the input IN
In the case of off-delay, the input signal b to the integrating circuit 6 has the opposite polarity to the input IN. The integration circuit 6 starts integration based on the change in the rising edge of the input signal b, and resets it based on the change in the falling edge of the input signal b. Outputs the waveform. Therefore, the output OUT from the second exclusive OR circuit 8 is also the same as in the waveform diagram shown in FIG.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional timer circuit.
FIG. 2 is a circuit diagram showing a first embodiment of the timer circuit according to the present invention, FIG. 3 is a waveform diagram showing the operation of the timer circuit according to the first embodiment, and FIG. 4 is a circuit diagram showing the operation of the timer circuit according to the first embodiment. 2. A circuit diagram showing the second embodiment. FIG. 5 is a circuit diagram showing an example of a timer circuit when the integrating circuit starts integration based on a change in the rising edge of a signal. FIG. FIG. 3 is a waveform diagram showing the operation of the timer circuit when starting integration based on . 5...First exclusive OR circuit, 6...Integrator circuit, 7...Second exclusive OR circuit, 9...Logic setting circuit.

Claims (1)

[Claims] 1. A first exclusive OR circuit that outputs an exclusive OR between the logic of the input binary signal and the set logic; and a signal obtained from the first exclusive OR circuit. An integrating circuit that starts integration based on a change in either the rising edge or falling edge of a signal and is reset based on a change in the other, and the logic of the signal obtained from the integrating circuit and the set logic. a second exclusive OR circuit that obtains an exclusive OR; and a second exclusive OR circuit that switches and sets the set logic in the first and second exclusive OR circuits; a logic setting circuit that causes the second exclusive OR circuit to function as an inverter or non-inverter for the logic of the signal obtained from the integrating circuit, while functioning as an inverter or non-inverter for the logic of the input binary signal; A timer circuit characterized by: